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authorSteve Kipisz <s-kipisz2@ti.com>2013-07-18 15:13:03 -0400
committerTom Rini <trini@ti.com>2013-07-30 09:21:41 -0400
commitcd8845d7a49687e9e7f727c9d821accf22854dd3 (patch)
treea45912edaf22760b46f43ca03f8f7e10a81af7b7 /arch
parent392bba4ad0049832f50eb368a04992f9719744b0 (diff)
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am335x_evm: Add support for the NOR module on the memory cape
This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Clean up config changes slightly] Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/am33xx/mem.c4
-rw-r--r--arch/arm/include/asm/arch-am33xx/mem.h9
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c
index 03e8c66..b6eb466 100644
--- a/arch/arm/cpu/armv7/am33xx/mem.c
+++ b/arch/arm/cpu/armv7/am33xx/mem.c
@@ -71,7 +71,11 @@ void gpmc_init(void)
writel(0x00000008, &gpmc_cfg->sysconfig);
writel(0x00000000, &gpmc_cfg->irqstatus);
writel(0x00000000, &gpmc_cfg->irqenable);
+#ifdef CONFIG_NOR
+ writel(0x00000200, &gpmc_cfg->config);
+#else
writel(0x00000012, &gpmc_cfg->config);
+#endif
/*
* Disable the GPMC0 config set by ROM code
*/
diff --git a/arch/arm/include/asm/arch-am33xx/mem.h b/arch/arm/include/asm/arch-am33xx/mem.h
index aef4e82..983ea28 100644
--- a/arch/arm/include/asm/arch-am33xx/mem.h
+++ b/arch/arm/include/asm/arch-am33xx/mem.h
@@ -30,6 +30,7 @@
*
* Currently valid part Names are (PART):
* M_NAND - Micron NAND
+ * STNOR - STMicrolelctronics M29W128GL
*/
#define GPMC_SIZE_256M 0x0
#define GPMC_SIZE_128M 0x8
@@ -45,6 +46,14 @@
#define M_NAND_GPMC_CONFIG6 0x16000f80
#define M_NAND_GPMC_CONFIG7 0x00000008
+#define STNOR_GPMC_CONFIG1 0x00001200
+#define STNOR_GPMC_CONFIG2 0x00101000
+#define STNOR_GPMC_CONFIG3 0x00030301
+#define STNOR_GPMC_CONFIG4 0x10041004
+#define STNOR_GPMC_CONFIG5 0x000C1010
+#define STNOR_GPMC_CONFIG6 0x08070280
+#define STNOR_GPMC_CONFIG7 0x00000F48
+
/* max number of GPMC Chip Selects */
#define GPMC_MAX_CS 8
/* max number of GPMC regs */