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authorTom Rini <trini@ti.com>2013-08-20 08:53:45 -0400
committerTom Rini <trini@ti.com>2013-08-28 11:44:58 -0400
commitc3799fceda6c37ad04bd62b6dd0db6225c11626b (patch)
tree5c6d55b18287083ef32ecda2aa1957e173bd32fa /arch
parenta7142dd0963d44d446cf4be5ba710a04c2223e86 (diff)
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omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR
After examining both TRMs and doing some experimentation, we can rely on using the start of the download area for CONFIG_SPL_TEXT_BASE and then move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for peripheral boot modes such as UART. Signed-off-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 597c692..e9a51d3 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -153,6 +153,15 @@ struct s32ktimer {
#define EFUSE_4 0x45145100
#endif /* __ASSEMBLY__ */
+/*
+ * In all cases, the TRM defines the RAM Memory Map for the processor
+ * and indicates the area for the downloaded image. We use all of that
+ * space for download and once up and running may use other parts of the
+ * map for our needs. We set a scratch space that is at the end of the
+ * OMAP5 download area, but within the DRA7xx download area (as it is
+ * much larger) and do not, at this time, make use of the additional
+ * space.
+ */
#ifdef CONFIG_DRA7XX
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
@@ -160,7 +169,7 @@ struct s32ktimer {
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
#endif
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4031F000