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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-01-15 15:18:04 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-01-15 15:18:04 +0100
commitbf46e7d8d134521301ff02b6d97e8998aa10a83d (patch)
tree2c92b6fb6dc329695dc703293b6ea260263cca70 /arch
parent6ba2bc8fa9be4bd09ec43e39cb8e666480ef010c (diff)
parent3a21773129f6ef218f1978d05a1a5d5cf6801ab6 (diff)
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Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c8
-rw-r--r--arch/arm/include/asm/arch-mx6/clock.h9
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h4
3 files changed, 19 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index f12bba2..5617a41 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -323,7 +323,7 @@ static u32 get_mmdc_ch0_clk(void)
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(void)
+int enable_fec_anatop_clock(enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
@@ -331,7 +331,13 @@ int enable_fec_anatop_clock(void)
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ if (freq < ENET_25MHz || freq > ENET_125MHz)
+ return -EINVAL;
+
reg = readl(&anatop->pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= freq;
+
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 93f29a7..e31ba0a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -42,6 +42,13 @@ enum mxc_clock {
MXC_I2C_CLK,
};
+enum enet_freq {
+ ENET_25MHz,
+ ENET_50MHz,
+ ENET_100MHz,
+ ENET_125MHz,
+};
+
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
@@ -50,5 +57,5 @@ void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_ipu_clock(void);
-int enable_fec_anatop_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index fb0c4c7..7f89865 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -245,6 +245,10 @@ struct src {
u32 gpr10;
};
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)