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authorPrabhakar Kushwaha <prabhakar@freescale.com>2011-02-04 09:00:43 +0530
committerKumar Gala <galak@kernel.crashing.org>2011-04-04 09:24:41 -0500
commitb6ccd2c9dee758a70e761403a41e60c31a1cfcec (patch)
treec47fc0dc31ba8bf0f837eea05d0eebd48449cc4e /arch
parent24995d829aecc6abca0f1b41443ae0cd9b4fde5a (diff)
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fsl_pci: Add support for FSL PCIe controllers v2.x
FSL PCIe controller v2.1: - New MSI inbound window - Same Inbound windows address as PCIe controller v1.x Added new pit_t member(pmit) to struct ccsr_pci for MSI inbound window FSL PCIe controller v2.2 and v2.3: - Different addresses for PCIe inbound window 3,2,1 - Exposed PCIe inbound window 0 - New PCIe interrupt status register Added new Interrupt Status register to struct ccsr_pci & updated pit_t array size to reflect the 4 inbound windows. To maintain backward compatiblilty, on V2.2 or greater controllers we start with inbound window 1 and leave inbound 0 with its default value (which maps to CCSRBAR). Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/fsl_pci.h20
1 files changed, 16 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index 0a98bde..82d75be 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -25,6 +25,9 @@
#include <asm/fsl_serdes.h>
#include <pci.h>
+#define PEX_IP_BLK_REV_2_2 0x02080202
+#define PEX_IP_BLK_REV_2_3 0x02080203
+
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
void fsl_pci_config_unlock(struct pci_controller *hose);
@@ -73,7 +76,8 @@ typedef struct ccsr_pci {
u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */
u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */
u32 config; /* 0x014 - PCIE CONFIG Register */
- char res2[8];
+ u32 int_status; /* 0x018 - PCIE interrupt status register */
+ char res2[4];
u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */
u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */
@@ -83,8 +87,11 @@ typedef struct ccsr_pci {
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
- u32 res5[64];
- pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */
+ u32 res5[24];
+ pit_t pmit; /* 0xd00 - 0xd9c Inbound ATMU's MSI */
+ u32 res6[24];
+ pit_t pit[4]; /* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
+
#define PIT3 0
#define PIT2 1
#define PIT1 2
@@ -158,6 +165,11 @@ typedef struct ccsr_pci {
u32 pdb_stat; /* 0xf00 - PCIE Debug Status */
char res24[252];
} ccsr_fsl_pci_t;
+#define PCIE_CONFIG_PC 0x00020000
+#define PCIE_CONFIG_OB_CK 0x00002000
+#define PCIE_CONFIG_SAC 0x00000010
+#define PCIE_CONFIG_SP 0x80000002
+#define PCIE_CONFIG_SCC 0x80000001
struct fsl_pci_info {
unsigned long regs;