MLK-14419-3 imx: mx7d_arm2: add 19x19 LPDDR2/LPDDR3/DDR3 ARM2 support

Add 19x19 LPDDR2/LPDDR3/DDR3 ARM2 board supports.
Enable the OF_CONTROL and convert them to use DM driver. Since the DTB lacks
the support for some modules. We have to use QSPI and FEC with non-DM driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>

5 files changed, 1728 insertions, 1 deletions

diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig
index 2e02f13..c4ae258 100644
--- a/arch/arm/cpu/armv7/mx7/Kconfig
+++ b/arch/arm/cpu/armv7/mx7/Kconfig
@@ -37,6 +37,27 @@ config TARGET_MX7D_12X12_DDR3_ARM2
 	select DM
 	select DM_THERMAL
 
+config TARGET_MX7D_19X19_DDR3_ARM2
+	bool "Support mx7d_19x19_ddr3_arm2"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+
+config TARGET_MX7D_19X19_LPDDR3_ARM2
+	bool "Support mx7d_19x19_ddr3_arm2"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+
+config TARGET_MX7D_19X19_LPDDR2_ARM2
+	bool "Support mx7d_19x19_ddr3_arm2"
+	select BOARD_LATE_INIT
+	select MX7D
+	select DM
+	select DM_THERMAL
+
 config TARGET_WARP7
 	bool "warp7"
 	select BOARD_LATE_INIT
@@ -59,6 +80,8 @@ config SYS_SOC
 source "board/freescale/mx7dsabresd/Kconfig"
 source "board/freescale/mx7d_12x12_lpddr3_arm2/Kconfig"
 source "board/freescale/mx7d_12x12_ddr3_arm2/Kconfig"
+source "board/freescale/mx7d_19x19_ddr3_arm2/Kconfig"
+source "board/freescale/mx7d_19x19_lpddr3_arm2/Kconfig"
 source "board/toradex/colibri_imx7/Kconfig"
 source "board/warp7/Kconfig"
 
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3df711d..9680eeb 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -370,7 +370,10 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 		imx7d-12x12-lpddr3-arm2.dtb \
 		imx7d-12x12-lpddr3-arm2-ecspi.dtb \
 		imx7d-12x12-lpddr3-arm2-qspi.dtb \
-		imx7d-12x12-ddr3-arm2.dtb
+		imx7d-12x12-ddr3-arm2.dtb \
+		imx7d-19x19-ddr3-arm2.dtb \
+		imx7d-19x19-lpddr2-arm2.dtb \
+		imx7d-19x19-lpddr3-arm2.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
diff --git a/arch/arm/dts/imx7d-19x19-ddr3-arm2.dts b/arch/arm/dts/imx7d-19x19-ddr3-arm2.dts
new file mode 100644
index 0000000..d487d13
--- /dev/null
+++ b/arch/arm/dts/imx7d-19x19-ddr3-arm2.dts
@@ -0,0 +1,786 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "Freescale i.MX7 DDR3L 19x19 ARM2 Board";
+	compatible = "fsl,imx7d-19x19-ddr3-arm2", "fsl,imx7d";
+
+	max7322_reset: max7322-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <1>;
+		#reset-cells = <0>;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		/* gpios disconnected see resistors R601, R583 */
+		status = "disabled";
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_lcd_reset: lcd-reset {
+			compatible = "regulator-fixed";
+			regulator-name = "lcd-reset";
+			gpio = <&gpio3 4 0>;
+			enable-active-high;
+		};
+
+		reg_sd2_vmmc: sd2_vmmc{
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD2";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_sd3_vmmc: sd3_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD3";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		reg_coedc_5v: coedc_5v {
+			compatible = "regulator-fixed";
+			regulator-name = "CODEC_5V";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_aud_3v3: aud_3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "AUD_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_aud_1v8: aud_1v8 {
+			compatible = "regulator-fixed";
+			regulator-name = "AUD_1V8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+
+	pxp_v4l2_out {
+		compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
+		status = "okay";
+	};
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+};
+
+&ecspi1 {
+	    fsl,spi-num-chipselects = <1>;
+		cs-gpios = <&gpio4 19 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>;
+		status = "okay";
+
+	    flash: at45@0 {
+	        #address-cells = <1>;
+	        #size-cells = <1>;
+	        compatible = "atmel,at45";
+	        spi-max-frequency = <20000000>;
+	        reg = <0>;
+	    };
+};
+
+&epxp {
+        status = "okay";
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+		};
+
+		ethphy1: ethernet-phy@5 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <5>;
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>;
+	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	status = "okay";
+
+	pmic: pfuze3000@08 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3_1>;
+	status = "okay";
+
+	max7322: gpio@68 {
+		compatible = "maxim,max7322";
+		reg = <0x68>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		resets = <&max7322_reset>;
+	};
+	codec: wm8958@1a {
+		compatible = "wlf,wm8958";
+		reg = <0x1a>;
+		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>,
+		       <&clks IMX7D_CLK_DUMMY>;
+		clock-names = "mclk1", "mclk2";
+
+		DBVDD1-supply = <&reg_aud_1v8>;
+		DBVDD2-supply = <&reg_aud_1v8>;
+		DBVDD3-supply = <&reg_aud_3v3>;
+		AVDD2-supply = <&reg_aud_1v8>;
+		CPVDD-supply = <&reg_aud_1v8>;
+		SPKVDD1-supply = <&reg_coedc_5v>;
+		SPKVDD2-supply = <&reg_coedc_5v>;
+
+		wlf,ldo1ena;
+		wlf,ldo2ena;
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd3_vselect>;
+
+	imx7d-19x19-ddr3-arm2 {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO12__SD2_VSELECT   0x59
+				MX7D_PAD_SD2_CD_B__GPIO5_IO9       0x59
+				MX7D_PAD_SD2_WP__GPIO5_IO10        0x59
+				MX7D_PAD_SD2_RESET_B__GPIO5_IO11   0x59
+				MX7D_PAD_SD3_RESET_B__GPIO6_IO11   0x59
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14    0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15    0x59
+				MX7D_PAD_SD3_STROBE__GPIO6_IO10    0x59
+
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	  0x7F
+				MX7D_PAD_I2C4_SDA__GPIO4_IO15     0x7F
+			>;
+		};
+
+		pinctrl_hog_sd3_vselect: hoggrp_sd3vselect {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO13__SD3_VSELECT   0x59
+			>;
+		};
+
+		pinctrl_csi: csigrp-1 {
+			fsl,pins = <
+				MX7D_PAD_LCD_DATA04__CSI_VSYNC 	0x0F
+				MX7D_PAD_LCD_DATA05__CSI_HSYNC 	0x0F
+				MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x0F
+				MX7D_PAD_LCD_DATA07__CSI_MCLK 	0x0F
+				MX7D_PAD_LCD_DATA08__CSI_DATA9 	0x0F
+				MX7D_PAD_LCD_DATA09__CSI_DATA8 	0x0F
+				MX7D_PAD_LCD_DATA10__CSI_DATA7 	0x0F
+				MX7D_PAD_LCD_DATA11__CSI_DATA6 	0x0F
+				MX7D_PAD_LCD_DATA12__CSI_DATA5 	0x0F
+				MX7D_PAD_LCD_DATA13__CSI_DATA4 	0x0F
+				MX7D_PAD_LCD_DATA14__CSI_DATA3 	0x0F
+				MX7D_PAD_LCD_DATA15__CSI_DATA2 	0x0F
+				MX7D_PAD_LCD_DATA02__GPIO3_IO7 	0x0F
+				MX7D_PAD_LCD_DATA03__GPIO3_IO8 	0x0F
+			>;
+		};
+
+		pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 	0x2
+			>;
+		};
+
+		pinctrl_ecspi1_1: ecspi1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 	0x2
+				MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 	0x2
+				MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 	0x2
+			>;
+		};
+
+		pinctrl_enet1: enet1grp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
+				MX7D_PAD_GPIO1_IO11__ENET1_MDC  0x3
+				MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+				MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+				MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+				MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+				MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+				MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+				MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+				MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+				MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+				MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+				MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+				MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+			>;
+		};
+
+		pinctrl_enet2: enet2grp {
+			fsl,pins = <
+				MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC	0x1
+				MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0	0x1
+				MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1	0x1
+				MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2	0x1
+				MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3	0x1
+				MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL	0x1
+				MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC	0x1
+				MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0	0x1
+				MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1	0x1
+				MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2	0x1
+				MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3	0x1
+				MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x1
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c3_1: i2c3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C3_SDA__I2C3_SDA	     0x4000007f
+				MX7D_PAD_I2C3_SCL__I2C3_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c4_1: i2c4grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SDA__I2C4_SDA          0x4000007f
+				MX7D_PAD_I2C4_SCL__I2C4_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_lcdif_dat: lcdifdatgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_DATA00__LCD_DATA0	0x79
+				MX7D_PAD_LCD_DATA01__LCD_DATA1	0x79
+				MX7D_PAD_LCD_DATA02__LCD_DATA2	0x79
+				MX7D_PAD_LCD_DATA03__LCD_DATA3	0x79
+				MX7D_PAD_LCD_DATA04__LCD_DATA4	0x79
+				MX7D_PAD_LCD_DATA05__LCD_DATA5	0x79
+				MX7D_PAD_LCD_DATA06__LCD_DATA6	0x79
+				MX7D_PAD_LCD_DATA07__LCD_DATA7	0x79
+				MX7D_PAD_LCD_DATA08__LCD_DATA8	0x79
+				MX7D_PAD_LCD_DATA09__LCD_DATA9	0x79
+				MX7D_PAD_LCD_DATA10__LCD_DATA10	0x79
+				MX7D_PAD_LCD_DATA11__LCD_DATA11	0x79
+				MX7D_PAD_LCD_DATA12__LCD_DATA12	0x79
+				MX7D_PAD_LCD_DATA13__LCD_DATA13	0x79
+				MX7D_PAD_LCD_DATA14__LCD_DATA14	0x79
+				MX7D_PAD_LCD_DATA15__LCD_DATA15	0x79
+				MX7D_PAD_LCD_DATA16__LCD_DATA16	0x79
+				MX7D_PAD_LCD_DATA17__LCD_DATA17	0x79
+				MX7D_PAD_LCD_DATA18__LCD_DATA18	0x79
+				MX7D_PAD_LCD_DATA19__LCD_DATA19	0x79
+				MX7D_PAD_LCD_DATA20__LCD_DATA20	0x79
+				MX7D_PAD_LCD_DATA21__LCD_DATA21	0x79
+				MX7D_PAD_LCD_DATA22__LCD_DATA22	0x79
+				MX7D_PAD_LCD_DATA23__LCD_DATA23	0x79
+			>;
+		};
+
+		pinctrl_lcdif_ctrl: lcdifctrlgrp {
+			fsl,pins = <
+				MX7D_PAD_LCD_CLK__LCD_CLK	0x79
+				MX7D_PAD_LCD_ENABLE__LCD_ENABLE	0x79
+				MX7D_PAD_LCD_VSYNC__LCD_VSYNC	0x79
+				MX7D_PAD_LCD_HSYNC__LCD_HSYNC	0x79
+			>;
+		};
+
+		pinctrl_sai1: sai1grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+				MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK     0x1f
+				MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
+				MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC     0x1f
+				MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0    0x1f
+				MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0    0
+			>;
+		};
+
+		pinctrl_sai2: sai2grp {
+			fsl,pins = <
+				MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+				MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
+				MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
+				MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
+				MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0
+				MX7D_PAD_GPIO1_IO13__GPIO1_IO13		0x59
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS	0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS	0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+				MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x59
+				MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x59
+				MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x59
+				MX7D_PAD_ECSPI2_SS0__SD1_DATA7  0x59
+			>;
+		};
+
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     0x59
+				MX7D_PAD_SD2_CLK__SD2_CLK     0x19
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     0x5a
+				MX7D_PAD_SD2_CLK__SD2_CLK     0x1a
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD2_CMD__SD2_CMD     0x5b
+				MX7D_PAD_SD2_CLK__SD2_CLK     0x1b
+				MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b
+				MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b
+				MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b
+				MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b
+			>;
+		};
+
+		pinctrl_usdhc3: usdhc3grp {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD     0x59
+				MX7D_PAD_SD3_CLK__SD3_CLK     0x19
+				MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+				MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+				MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+				MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+				MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+				MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+				MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+				MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+			>;
+		};
+
+		pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD     0x5a
+				MX7D_PAD_SD3_CLK__SD3_CLK     0x1a
+				MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+				MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+				MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+				MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+				MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+				MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+				MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+				MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+			>;
+		};
+
+		pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD3_CMD__SD3_CMD     0x5b
+				MX7D_PAD_SD3_CLK__SD3_CLK     0x1b
+				MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+				MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+				MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+				MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+				MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+				MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+				MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+				MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-19x19-ddr3-arm2 {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x80000000
+				MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x80000000
+			>;
+		};
+
+		pinctrl_mipi_csi: mipicsigrp-1 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT 0x3
+			>;
+		};
+	};
+};
+
+&lcdif {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lcdif_dat
+		     &pinctrl_lcdif_ctrl>;
+	display = <&display0>;
+	status = "okay";
+
+	display0: display {
+		bits-per-pixel = <16>;
+		bus-width = <24>;
+
+		display-timings {
+			native-mode = <&timing0>;
+			timing0: timing0 {
+				clock-frequency = <33500000>;
+				hactive = <800>;
+				vactive = <480>;
+				hback-porch = <89>;
+				hfront-porch = <164>;
+				vback-porch = <23>;
+				vfront-porch = <10>;
+				hsync-len = <10>;
+				vsync-len = <10>;
+				hsync-active = <0>;
+				vsync-active = <0>;
+				de-active = <1>;
+				pixelclk-active = <0>;
+			};
+		};
+	};
+};
+
+&sai1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai1>;
+	status = "disabled";
+};
+
+&sai2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sai2>;
+	status = "disabled";
+};
+
+&sdma {
+	status = "okay";
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	pinctrl-0 = <&pinctrl_uart3dte_1>;
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+	cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	tuning-step = <2>;
+	vmmc-supply = <&reg_sd2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	tuning-step = <2>;
+	vmmc-supply = <&reg_sd3_vmmc>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7d-19x19-lpddr2-arm2.dts b/arch/arm/dts/imx7d-19x19-lpddr2-arm2.dts
new file mode 100644
index 0000000..2af374c
--- /dev/null
+++ b/arch/arm/dts/imx7d-19x19-lpddr2-arm2.dts
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "Freescale i.MX7D LPDDR2 19x19 ARM2 Board";
+	compatible = "fsl,imx7d-19x19-lpddr2-arm2", "fsl,imx7d";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		status = "disabled";
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD1";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x20000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	status = "okay";
+
+	pmic: pfuze3000@08 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7d-19x19-lpddr3-arm2 {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	   0x80000000
+
+				MX7D_PAD_SD1_CD_B__GPIO5_IO0 		0x59
+				MX7D_PAD_SD1_WP__GPIO5_IO1 			0x59
+				MX7D_PAD_SD1_RESET_B__GPIO5_IO2 	0x59
+
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14    	0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15    	0x59
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CLK__NAND_CLE			0x71
+				MX7D_PAD_SD3_CMD__NAND_ALE			0x71
+				MX7D_PAD_SAI1_MCLK__NAND_WP_B		0x71
+				MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+				MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	0x71
+				MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+				MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+				MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+				MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+				MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+				MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+				MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+				MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+				MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+				MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+				MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_weim_cs0_1: weim_cs0grp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA10__EIM_CS0_B      0x71
+			>;
+		};
+
+		pinctrl_weim_nor_1: weim_norgrp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA08__EIM_OE         0x71
+				MX7D_PAD_EPDC_DATA09__EIM_RW         0x71
+				MX7D_PAD_EPDC_DATA11__EIM_BCLK       0x71
+				MX7D_PAD_EPDC_DATA12__EIM_LBA_B      0x71
+				MX7D_PAD_EPDC_DATA13__EIM_WAIT       0x75
+				/* data */
+				MX7D_PAD_LCD_DATA00__EIM_DATA0       0x7d
+				MX7D_PAD_LCD_DATA01__EIM_DATA1       0x7d
+				MX7D_PAD_LCD_DATA02__EIM_DATA2       0x7d
+				MX7D_PAD_LCD_DATA03__EIM_DATA3       0x7d
+				MX7D_PAD_LCD_DATA04__EIM_DATA4       0x7d
+				MX7D_PAD_LCD_DATA05__EIM_DATA5       0x7d
+				MX7D_PAD_LCD_DATA06__EIM_DATA6       0x7d
+				MX7D_PAD_LCD_DATA07__EIM_DATA7       0x7d
+				MX7D_PAD_LCD_DATA08__EIM_DATA8       0x7d
+				MX7D_PAD_LCD_DATA09__EIM_DATA9       0x7d
+				MX7D_PAD_LCD_DATA10__EIM_DATA10      0x7d
+				MX7D_PAD_LCD_DATA11__EIM_DATA11      0x7d
+				MX7D_PAD_LCD_DATA12__EIM_DATA12      0x7d
+				MX7D_PAD_LCD_DATA13__EIM_DATA13      0x7d
+				MX7D_PAD_LCD_DATA14__EIM_DATA14      0x7d
+				MX7D_PAD_LCD_DATA15__EIM_DATA15      0x7d
+				/* address */
+				MX7D_PAD_EPDC_DATA00__EIM_AD0        0x71
+				MX7D_PAD_EPDC_DATA01__EIM_AD1        0x71
+				MX7D_PAD_EPDC_DATA02__EIM_AD2        0x71
+				MX7D_PAD_EPDC_DATA03__EIM_AD3        0x71
+				MX7D_PAD_EPDC_DATA04__EIM_AD4        0x71
+				MX7D_PAD_EPDC_DATA05__EIM_AD5        0x71
+				MX7D_PAD_EPDC_DATA06__EIM_AD6        0x71
+				MX7D_PAD_EPDC_DATA07__EIM_AD7        0x71
+				MX7D_PAD_EPDC_BDR1__EIM_AD8          0x71
+				MX7D_PAD_EPDC_PWR_COM__EIM_AD9       0x71
+				MX7D_PAD_EPDC_SDCLK__EIM_AD10        0x71
+				MX7D_PAD_EPDC_SDLE__EIM_AD11         0x71
+				MX7D_PAD_EPDC_SDOE__EIM_AD12         0x71
+				MX7D_PAD_EPDC_SDSHR__EIM_AD13        0x71
+				MX7D_PAD_EPDC_SDCE0__EIM_AD14        0x71
+				MX7D_PAD_EPDC_SDCE1__EIM_AD15        0x71
+				MX7D_PAD_EPDC_SDCE2__EIM_ADDR16      0x71
+				MX7D_PAD_EPDC_SDCE3__EIM_ADDR17      0x71
+				MX7D_PAD_EPDC_GDCLK__EIM_ADDR18      0x71
+				MX7D_PAD_EPDC_GDOE__EIM_ADDR19       0x71
+				MX7D_PAD_EPDC_GDRL__EIM_ADDR20       0x71
+				MX7D_PAD_EPDC_GDSP__EIM_ADDR21       0x71
+				MX7D_PAD_EPDC_BDR0__EIM_ADDR22       0x71
+				MX7D_PAD_LCD_DATA20__EIM_ADDR23      0x71
+				MX7D_PAD_LCD_DATA21__EIM_ADDR24      0x71
+				MX7D_PAD_LCD_DATA22__EIM_ADDR25      0x71
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS		0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS		0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS		0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS		0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5a
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1a
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5a
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5a
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5a
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5a
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5b
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1b
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5b
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5b
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5b
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5b
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-19x19-lpddr3-arm2 {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14
+				MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
+				MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
+			>;
+		};
+	};
+};
+
+&sdma {
+	status = "okay";
+};
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x28000000 0x08000000>;
+	status = "okay";
+
+	nor@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x08000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
+				0x0000c000 0x1404a38e 0x00000000>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	pinctrl-0 = <&pinctrl_uart3dte_1>;
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7d-19x19-lpddr3-arm2.dts b/arch/arm/dts/imx7d-19x19-lpddr3-arm2.dts
new file mode 100644
index 0000000..35f1bf7
--- /dev/null
+++ b/arch/arm/dts/imx7d-19x19-lpddr3-arm2.dts
@@ -0,0 +1,461 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "imx7d.dtsi"
+
+/ {
+	model = "Freescale i.MX7 LPDDR3 19x19 ARM2 Board";
+	compatible = "fsl,imx7d-19x19-lpddr3-arm2", "fsl,imx7d";
+
+	gpio-keys {
+		compatible = "gpio-keys";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_keys>;
+		status = "disabled";
+
+		volume-up {
+			label = "Volume Up";
+			gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEUP>;
+		};
+
+		volume-down {
+			label = "Volume Down";
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_VOLUMEDOWN>;
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_sd1_vmmc: sd1_vmmc {
+			compatible = "regulator-fixed";
+			regulator-name = "VCC_SD1";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+
+		reg_vref_1v8: regulator@2 {
+			compatible = "regulator-fixed";
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+	};
+
+	memory {
+		reg = <0x80000000 0x80000000>;
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+};
+
+&gpmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+	status = "okay";
+	nand-on-flash-bbt;
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_1>;
+	status = "okay";
+
+	pmic: pfuze3000@08 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+			/* use sw1c_reg to align with pfuze100/pfuze200 */
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2_1>;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7d-19x19-lpddr3-arm2 {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C4_SCL__GPIO4_IO14	   0x80000000
+
+				MX7D_PAD_SD1_CD_B__GPIO5_IO0 		0x59
+				MX7D_PAD_SD1_WP__GPIO5_IO1 			0x59
+				MX7D_PAD_SD1_RESET_B__GPIO5_IO2 	0x59
+
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14    	0x59
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15    	0x59
+			>;
+		};
+
+		pinctrl_gpio_keys: gpio_keysgrp {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32
+				MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32
+			>;
+		};
+
+		pinctrl_gpmi_nand_1: gpmi-nand-1 {
+			fsl,pins = <
+				MX7D_PAD_SD3_CLK__NAND_CLE			0x71
+				MX7D_PAD_SD3_CMD__NAND_ALE			0x71
+				MX7D_PAD_SAI1_MCLK__NAND_WP_B		0x71
+				MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	0x71
+				MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	0x71
+				MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	0x74
+				MX7D_PAD_SD3_STROBE__NAND_RE_B		0x71
+				MX7D_PAD_SD3_RESET_B__NAND_WE_B		0x71
+				MX7D_PAD_SD3_DATA0__NAND_DATA00		0x71
+				MX7D_PAD_SD3_DATA1__NAND_DATA01		0x71
+				MX7D_PAD_SD3_DATA2__NAND_DATA02		0x71
+				MX7D_PAD_SD3_DATA3__NAND_DATA03		0x71
+				MX7D_PAD_SD3_DATA4__NAND_DATA04		0x71
+				MX7D_PAD_SD3_DATA5__NAND_DATA05		0x71
+				MX7D_PAD_SD3_DATA6__NAND_DATA06		0x71
+				MX7D_PAD_SD3_DATA7__NAND_DATA07		0x71
+			>;
+		};
+
+		pinctrl_i2c1_1: i2c1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C1_SDA__I2C1_SDA          0x4000007f
+				MX7D_PAD_I2C1_SCL__I2C1_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_i2c2_1: i2c2grp-1 {
+			fsl,pins = <
+				MX7D_PAD_I2C2_SDA__I2C2_SDA          0x4000007f
+				MX7D_PAD_I2C2_SCL__I2C2_SCL          0x4000007f
+			>;
+		};
+
+		pinctrl_weim_cs0_1: weim_cs0grp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA10__EIM_CS0_B      0x71
+			>;
+		};
+
+		pinctrl_weim_nor_1: weim_norgrp-1 {
+			fsl,pins = <
+				MX7D_PAD_EPDC_DATA08__EIM_OE         0x71
+				MX7D_PAD_EPDC_DATA09__EIM_RW         0x71
+				MX7D_PAD_EPDC_DATA11__EIM_BCLK       0x71
+				MX7D_PAD_EPDC_DATA12__EIM_LBA_B      0x71
+				MX7D_PAD_EPDC_DATA13__EIM_WAIT       0x75
+				/* data */
+				MX7D_PAD_LCD_DATA00__EIM_DATA0       0x7d
+				MX7D_PAD_LCD_DATA01__EIM_DATA1       0x7d
+				MX7D_PAD_LCD_DATA02__EIM_DATA2       0x7d
+				MX7D_PAD_LCD_DATA03__EIM_DATA3       0x7d
+				MX7D_PAD_LCD_DATA04__EIM_DATA4       0x7d
+				MX7D_PAD_LCD_DATA05__EIM_DATA5       0x7d
+				MX7D_PAD_LCD_DATA06__EIM_DATA6       0x7d
+				MX7D_PAD_LCD_DATA07__EIM_DATA7       0x7d
+				MX7D_PAD_LCD_DATA08__EIM_DATA8       0x7d
+				MX7D_PAD_LCD_DATA09__EIM_DATA9       0x7d
+				MX7D_PAD_LCD_DATA10__EIM_DATA10      0x7d
+				MX7D_PAD_LCD_DATA11__EIM_DATA11      0x7d
+				MX7D_PAD_LCD_DATA12__EIM_DATA12      0x7d
+				MX7D_PAD_LCD_DATA13__EIM_DATA13      0x7d
+				MX7D_PAD_LCD_DATA14__EIM_DATA14      0x7d
+				MX7D_PAD_LCD_DATA15__EIM_DATA15      0x7d
+				/* address */
+				MX7D_PAD_EPDC_DATA00__EIM_AD0        0x71
+				MX7D_PAD_EPDC_DATA01__EIM_AD1        0x71
+				MX7D_PAD_EPDC_DATA02__EIM_AD2        0x71
+				MX7D_PAD_EPDC_DATA03__EIM_AD3        0x71
+				MX7D_PAD_EPDC_DATA04__EIM_AD4        0x71
+				MX7D_PAD_EPDC_DATA05__EIM_AD5        0x71
+				MX7D_PAD_EPDC_DATA06__EIM_AD6        0x71
+				MX7D_PAD_EPDC_DATA07__EIM_AD7        0x71
+				MX7D_PAD_EPDC_BDR1__EIM_AD8          0x71
+				MX7D_PAD_EPDC_PWR_COM__EIM_AD9       0x71
+				MX7D_PAD_EPDC_SDCLK__EIM_AD10        0x71
+				MX7D_PAD_EPDC_SDLE__EIM_AD11         0x71
+				MX7D_PAD_EPDC_SDOE__EIM_AD12         0x71
+				MX7D_PAD_EPDC_SDSHR__EIM_AD13        0x71
+				MX7D_PAD_EPDC_SDCE0__EIM_AD14        0x71
+				MX7D_PAD_EPDC_SDCE1__EIM_AD15        0x71
+				MX7D_PAD_EPDC_SDCE2__EIM_ADDR16      0x71
+				MX7D_PAD_EPDC_SDCE3__EIM_ADDR17      0x71
+				MX7D_PAD_EPDC_GDCLK__EIM_ADDR18      0x71
+				MX7D_PAD_EPDC_GDOE__EIM_ADDR19       0x71
+				MX7D_PAD_EPDC_GDRL__EIM_ADDR20       0x71
+				MX7D_PAD_EPDC_GDSP__EIM_ADDR21       0x71
+				MX7D_PAD_EPDC_BDR0__EIM_ADDR22       0x71
+				MX7D_PAD_LCD_DATA20__EIM_ADDR23      0x71
+				MX7D_PAD_LCD_DATA21__EIM_ADDR24      0x71
+				MX7D_PAD_LCD_DATA22__EIM_ADDR25      0x71
+			>;
+		};
+
+		pinctrl_uart1_1: uart1grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
+				MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
+			>;
+		};
+
+		pinctrl_uart3_1: uart3grp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS		0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS		0x79
+			>;
+		};
+
+		pinctrl_uart3dte_1: uart3dtegrp-1 {
+			fsl,pins = <
+				MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX	0x79
+				MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX	0x79
+				MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS		0x79
+				MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS		0x79
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5a
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1a
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5a
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5a
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5a
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5a
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+			fsl,pins = <
+				MX7D_PAD_SD1_CMD__SD1_CMD       0x5b
+				MX7D_PAD_SD1_CLK__SD1_CLK       0x1b
+				MX7D_PAD_SD1_DATA0__SD1_DATA0   0x5b
+				MX7D_PAD_SD1_DATA1__SD1_DATA1   0x5b
+				MX7D_PAD_SD1_DATA2__SD1_DATA2   0x5b
+				MX7D_PAD_SD1_DATA3__SD1_DATA3   0x5b
+			>;
+		};
+	};
+};
+
+&iomuxc_lpsr {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_2>;
+
+	imx7d-19x19-lpddr3-arm2 {
+		pinctrl_hog_2: hoggrp-2 {
+			fsl,pins = <
+				MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14
+				MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x14
+				MX7D_PAD_GPIO1_IO07__GPIO1_IO7 0x14
+			>;
+		};
+	};
+};
+
+&sdma {
+	status = "okay";
+};
+
+&weim {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
+	#address-cells = <2>;
+	#size-cells = <1>;
+	ranges = <0 0 0x28000000 0x08000000>;
+	status = "okay";
+
+	nor@0,0 {
+		compatible = "cfi-flash";
+		reg = <0 0 0x08000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		bank-width = <2>;
+		fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000
+				0x0000c000 0x1404a38e 0x00000000>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1_1>;
+	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3_1>;
+	fsl,uart-has-rtscts;
+	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+	/* for DTE mode, add below change */
+	/* fsl,dte-mode;*/
+	pinctrl-0 = <&pinctrl_uart3dte_1>;
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+	wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+	no-1-8-v;
+	keep-power-in-suspend;
+	enable-sdio-wakeup;
+	vmmc-supply = <&reg_sd1_vmmc>;
+	status = "okay";
+};