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authorLin Huang <hl@rock-chips.com>2016-02-17 15:55:05 +0800
committerSimon Glass <sjg@chromium.org>2016-03-10 08:32:01 -0700
commit99aaa930754cd9558e42d526029267a2c023016e (patch)
tree29e4398be0402f82ffbead3c62730b005ad96a6b /arch
parentdeff6fb3a7790e93264292982000275e78bb12e5 (diff)
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rockchip: rk3036: change ddr frequency to 400M
emac may use dpll as clock parent, and it request the clock frequency multiples of 50, so change ddr frequency to 400M. Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-rockchip/rk3036/sdram_rk3036.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
index e3ca870..ec8305c 100644
--- a/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
+++ b/arch/arm/mach-rockchip/rk3036/sdram_rk3036.c
@@ -37,7 +37,7 @@ struct rk3036_sdram_priv {
/* use integer mode, 396MHz dpll setting
* refdiv, fbdiv, postdiv1, postdiv2
*/
-const struct pll_div dpll_init_cfg = {1, 66, 4, 1};
+const struct pll_div dpll_init_cfg = {1, 50, 3, 1};
/* 396Mhz ddr timing */
const struct rk3036_ddr_timing ddr_timing = {0x18c,