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authorMichal Simek <michal.simek@xilinx.com>2014-01-20 11:05:37 +0100
committerMichal Simek <michal.simek@xilinx.com>2014-02-19 09:41:22 +0100
commit96a5d4dc1ec1ce26b32a3fa294816a47b62ae68a (patch)
tree9699d1c17c0cc165be902e49ad8255dbe4528fe1 /arch
parentd6c9bbaad194b48e799ed84df67b629424a56508 (diff)
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zynq: Update CLK in bdinfo
ARM has specific clk entries which should be also setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/zynq/clk.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/cpu/armv7/zynq/clk.c
index 4307111..d2885dc 100644
--- a/arch/arm/cpu/armv7/zynq/clk.c
+++ b/arch/arm/cpu/armv7/zynq/clk.c
@@ -161,6 +161,8 @@ static void init_ddr_clocks(void)
clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
DIV_ROUND_CLOSEST(prate, div0), div1);
clks[dci_clk].name = "dci";
+
+ gd->bd->bi_ddr_freq = clks[ddr3x_clk].frequency / 1000000;
}
static void init_cpu_clocks(void)
@@ -593,6 +595,9 @@ int set_cpu_clk_info(void)
init_periph_clocks();
init_aper_clocks();
+ gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+ gd->bd->bi_dsp_freq = 0;
+
return 0;
}