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authorEnric Balletbo i Serra <eballetbo@gmail.com>2010-10-14 16:53:27 -0400
committerWolfgang Denk <wd@denx.de>2010-10-17 20:14:39 +0200
commit84b6631038a869a604adc9ca60c5f545bbf2650e (patch)
tree6d97253041c2820f4532d931d48bafdc77402f53 /arch
parent57b512b2ecc9c7a6c8a39c5356ea80fc3164d9e4 (diff)
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OMAP3: SDRC: Introduce Numonyx DDR type
Introduce Numonyx DDR timings and provide CONFIG_OMAP3_NUMONYX_DDR config options to allow for platform files to setup their timings. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Acked-by: Steve Sakoman <steve.sakoman@linaro.org> Tested-by: Steve Sakoman <steve.sakoman@linaro.org> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-omap3/mem.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h
index a78cf9f..f165949 100644
--- a/arch/arm/include/asm/arch-omap3/mem.h
+++ b/arch/arm/include/asm/arch-omap3/mem.h
@@ -128,6 +128,45 @@ enum {
(MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
(MICRON_TWTR_165 << 16))
+/*
+ * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
+ * ACTIMA
+ * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
+ * TDPL (Twr) = 15/6 = 2.5 -> 3
+ * TRRD = 12/6 = 2
+ * TRCD = 22.5/6 = 3.75 -> 4
+ * TRP = 18/6 = 3
+ * TRAS = 42/6 = 7
+ * TRC = 60/6 = 10
+ * TRFC = 140/6 = 23.3 -> 24
+ * ACTIMB
+ * TWTR = 2
+ * TCKE = 2
+ * TXSR = 200/6 = 33.3 -> 34
+ * TXP = 1.0 + 1.1 = 2.1 -> 3
+ */
+#define NUMONYX_TDAL_165 6
+#define NUMONYX_TDPL_165 3
+#define NUMONYX_TRRD_165 2
+#define NUMONYX_TRCD_165 4
+#define NUMONYX_TRP_165 3
+#define NUMONYX_TRAS_165 7
+#define NUMONYX_TRC_165 10
+#define NUMONYX_TRFC_165 24
+#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
+ (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
+ (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
+ (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
+ (NUMONYX_TDAL_165))
+
+#define NUMONYX_TWTR_165 2
+#define NUMONYX_TCKE_165 2
+#define NUMONYX_TXP_165 3
+#define NUMONYX_XSR_165 34
+#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
+ (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
+ (NUMONYX_TWTR_165 << 16))
+
#ifdef CONFIG_OMAP3_INFINEON_DDR
#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
@@ -136,6 +175,10 @@ enum {
#define V_ACTIMA_165 MICRON_V_ACTIMA_165
#define V_ACTIMB_165 MICRON_V_ACTIMB_165
#endif
+#ifdef CONFIG_OMAP3_NUMONYX_DDR
+#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
+#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
+#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#error "Please choose the right DDR type in config header"