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authorTimur Tabi <timur@freescale.com>2010-05-28 15:05:30 -0500
committerKumar Gala <galak@kernel.crashing.org>2010-07-16 10:55:10 -0500
commit752bc335302d70d89c7e7cc711b9184260121b19 (patch)
tree94e9e2f769b4e03d0bceee4cf19b2fd0af01bd06 /arch
parentae3913922ad8d001310bdb74065d58b3baa0f537 (diff)
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fsl: add LAW target to fsl_pci_info structure
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that we can capture the LAW target for a given PCI or PCIE controller. Also update the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure. This will allow future PCI[E] code to configure the LAW target automatically, rather than requiring each board to it for each PCI controller separately. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/fsl_pci.h19
1 files changed, 11 insertions, 8 deletions
diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index db61e7e..bb87543 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -162,14 +162,15 @@ typedef struct ccsr_pci {
} ccsr_fsl_pci_t;
struct fsl_pci_info {
- unsigned long regs;
- pci_addr_t mem_bus;
- phys_size_t mem_phys;
- pci_size_t mem_size;
- pci_addr_t io_bus;
- phys_size_t io_phys;
- pci_size_t io_size;
- int pci_num;
+ unsigned long regs;
+ pci_addr_t mem_bus;
+ phys_size_t mem_phys;
+ pci_size_t mem_size;
+ pci_addr_t io_bus;
+ phys_size_t io_phys;
+ pci_size_t io_size;
+ enum law_trgt_if law;
+ int pci_num;
};
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
@@ -184,6 +185,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCI_##num; \
x.pci_num = num; \
}
@@ -196,6 +198,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
+ x.law = LAW_TRGT_IF_PCIE_##num; \
x.pci_num = num; \
}