diff options
author | Simon Glass <sjg@chromium.org> | 2016-01-17 16:11:16 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 12:08:16 +0800 |
commit | 655925a9c5bd756140f21dd935d1aca092ab7a01 (patch) | |
tree | b45efeb3f13f2e2b6279f0b43fdb3f13b1e4e3ea /arch | |
parent | e40a6e3f104fc632a66553e29a7ea1d4500e6189 (diff) | |
download | u-boot-imx-655925a9c5bd756140f21dd935d1aca092ab7a01.zip u-boot-imx-655925a9c5bd756140f21dd935d1aca092ab7a01.tar.gz u-boot-imx-655925a9c5bd756140f21dd935d1aca092ab7a01.tar.bz2 |
x86: ivybridge: Move northbridge init into the probe() method
Now that we have a proper driver for the nortbridge, set it up in by probing
it, and move the early init code into the probe() method.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 2 | ||||
-rw-r--r-- | arch/x86/cpu/ivybridge/early_init.c | 33 |
2 files changed, 21 insertions, 14 deletions
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 2a15fc0..f32b4a1 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -243,6 +243,8 @@ int print_cpuinfo(void) } /* Early chipset init required before RAM init can work */ + uclass_first_device(UCLASS_NORTHBRIDGE, &dev); + ret = uclass_first_device(UCLASS_PCH, &dev); if (ret) return ret; diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 945ae2d..c629f5b 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -123,20 +123,6 @@ void sandybridge_early_init(int chipset_type) pci_dev_t pch_dev = PCH_DEV; pci_dev_t video_dev = PCH_VIDEO_DEV; pci_dev_t lpc_dev = PCH_LPC_DEV; - u32 capid0_a; - u8 reg8; - - /* Device ID Override Enable should be done very early */ - capid0_a = x86_pci_read_config32(pch_dev, 0xe4); - if (capid0_a & (1 << 10)) { - reg8 = x86_pci_read_config8(pch_dev, 0xf3); - reg8 &= ~7; /* Clear 2:0 */ - - if (chipset_type == SANDYBRIDGE_MOBILE) - reg8 |= 1; /* Set bit 0 */ - - x86_pci_write_config8(pch_dev, 0xf3, reg8); - } /* Setup all BARs required for early PCIe and raminit */ sandybridge_setup_bars(pch_dev, lpc_dev); @@ -149,6 +135,25 @@ void sandybridge_early_init(int chipset_type) static int bd82x6x_northbridge_probe(struct udevice *dev) { + const int chipset_type = SANDYBRIDGE_MOBILE; + u32 capid0_a; + u8 reg8; + + if (gd->flags & GD_FLG_RELOC) + return 0; + + /* Device ID Override Enable should be done very early */ + dm_pci_read_config32(dev, 0xe4, &capid0_a); + if (capid0_a & (1 << 10)) { + dm_pci_read_config8(dev, 0xf3, ®8); + reg8 &= ~7; /* Clear 2:0 */ + + if (chipset_type == SANDYBRIDGE_MOBILE) + reg8 |= 1; /* Set bit 0 */ + + dm_pci_write_config8(dev, 0xf3, reg8); + } + return 0; } |