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authorTom Rini <trini@konsulko.com>2015-04-10 09:38:38 -0400
committerTom Rini <trini@konsulko.com>2015-04-10 11:54:07 -0400
commit59064346dd2713e5259a32d5ef55792a8f91171b (patch)
tree2192fa718f041119e9ba64a9d76f7fe7c546d480 /arch
parent6d0f45260846b8cafcae6a815178ff8ece7dea7a (diff)
parent412ae53aadb53cd63e754d638bafe6e426aeafee (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/Makefile32
-rw-r--r--arch/arm/cpu/arm1136/config.mk9
-rw-r--r--arch/arm/cpu/arm1176/config.mk9
-rw-r--r--arch/arm/cpu/arm720t/config.mk9
-rw-r--r--arch/arm/cpu/arm920t/config.mk8
-rw-r--r--arch/arm/cpu/arm926ejs/config.mk8
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/Makefile2
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/clk.c34
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/cpu.c10
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/devices.c43
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/dram.c77
-rw-r--r--arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S45
-rw-r--r--arch/arm/cpu/arm946es/config.mk8
-rw-r--r--arch/arm/cpu/armv7/config.mk5
-rw-r--r--arch/arm/cpu/armv8/config.mk2
-rw-r--r--arch/arm/cpu/pxa/config.mk2
-rw-r--r--arch/arm/cpu/sa1100/config.mk9
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/clk.h16
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/config.h3
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/cpu.h3
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/emc.h21
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/gpio.h43
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/mux.h18
-rw-r--r--arch/arm/include/asm/arch-lpc32xx/sys_proto.h10
25 files changed, 362 insertions, 70 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 80b0d34..086ca85 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -132,6 +132,11 @@ config TARGET_DEVKIT3250
bool "Support devkit3250"
select CPU_ARM926EJS
+config TARGET_WORK_92105
+ bool "Support work_92105"
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
config TARGET_MX25PDK
bool "Support mx25pdk"
select CPU_ARM926EJS
@@ -872,6 +877,7 @@ source "board/vpac270/Kconfig"
source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
+source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bac3cb2..6463c19 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -2,6 +2,38 @@
# SPDX-License-Identifier: GPL-2.0+
#
+# This selects which instruction set is used.
+arch-$(CONFIG_CPU_ARM720T) =-march=armv4
+arch-$(CONFIG_CPU_ARM920T) =-march=armv4
+arch-$(CONFIG_CPU_ARM926EJS) =-march=armv5te
+arch-$(CONFIG_CPU_ARM946ES) =-march=armv4
+arch-$(CONFIG_CPU_SA1100) =-march=armv4
+arch-$(CONFIG_CPU_PXA) =
+arch-$(CONFIG_CPU_ARM1136) =-march=armv5
+arch-$(CONFIG_CPU_ARM1176) =-march=armv5t
+arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, -march=armv5)
+arch-$(CONFIG_ARM64) =-march=armv8-a
+
+# Evaluate arch cc-option calls now
+arch-y := $(arch-y)
+
+# This selects how we optimise for the processor.
+tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
+tune-$(CONFIG_CPU_ARM920T) =
+tune-$(CONFIG_CPU_ARM926EJS) =
+tune-$(CONFIG_CPU_ARM946ES) =
+tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
+tune-$(CONFIG_CPU_PXA) =-mcpu=xscale
+tune-$(CONFIG_CPU_ARM1136) =
+tune-$(CONFIG_CPU_ARM1176) =
+tune-$(CONFIG_CPU_V7) =
+tune-$(CONFIG_ARM64) =
+
+# Evaluate tune cc-option calls now
+tune-y := $(tune-y)
+
+PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
+
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_AT91) += at91
diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk
deleted file mode 100644
index a82c6ce..0000000
--- a/arch/arm/cpu/arm1136/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk
deleted file mode 100644
index 5dc2ebb..0000000
--- a/arch/arm/cpu/arm1176/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk
deleted file mode 100644
index 772fb41..0000000
--- a/arch/arm/cpu/arm720t/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk
deleted file mode 100644
index 799afff..0000000
--- a/arch/arm/cpu/arm920t/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk
deleted file mode 100644
index bdb3da1..0000000
--- a/arch/arm/cpu/arm926ejs/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv5te
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
index 314f004..4837377 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -6,3 +6,5 @@
#
obj-y = cpu.o clk.o devices.o timer.o
+
+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d5..1ef8a36 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void)
return get_hclk_pll_rate() / get_periph_clk_div();
}
+unsigned int get_sdram_clk_rate(void)
+{
+ unsigned int src_clk;
+
+ if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
+ return get_sys_clk_rate();
+
+ src_clk = get_hclk_pll_rate();
+
+ if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
+ /* using DDR */
+ switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
+ case CLK_HCLK_DDRAM_HALF:
+ return src_clk/2;
+ case CLK_HCLK_DDRAM_NOMINAL:
+ return src_clk;
+ default:
+ return 0;
+ }
+ } else {
+ /* using SDR */
+ switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
+ case CLK_HCLK_ARM_PLL_DIV_4:
+ return src_clk/4;
+ case CLK_HCLK_ARM_PLL_DIV_2:
+ return src_clk/2;
+ case CLK_HCLK_ARM_PLL_DIV_1:
+ return src_clk;
+ default:
+ return 0;
+ }
+ }
+}
+
int get_serial_clock(void)
{
return get_periph_clk_rate();
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..f757474 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,9 +5,11 @@
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
@@ -55,3 +57,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,10 +8,13 @@
#include <asm/arch/cpu.h>
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
+#include <asm/arch/mux.h>
#include <asm/io.h>
+#include <dm.h>
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -37,3 +40,43 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
&clk->u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, &clk->macclk_ctrl);
+}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
+}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(&clk->i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, &clk->i2cclk_ctrl);
+}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = "gpio_lpc32xx"
+};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, &mux->p_mux_set);
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/dram.c b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c
new file mode 100644
index 0000000..1eea8e2
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/dram.c
@@ -0,0 +1,77 @@
+/*
+ * LPC32xx dram init
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * This is called by SPL to gain access to the SDR DRAM.
+ *
+ * This code runs from SRAM.
+ *
+ * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided
+ * by the board configuration file.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/wdt.h>
+#include <asm/arch/emc.h>
+#include <asm/io.h>
+
+static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
+static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
+
+void ddr_init(struct emc_dram_settings *dram)
+{
+ uint32_t ck;
+
+ /* Enable EMC interface and choose little endian mode */
+ writel(1, &emc->ctrl);
+ writel(0, &emc->config);
+ /* Select maximum EMC Dynamic Memory Refresh Time */
+ writel(0x7FF, &emc->refresh);
+ /* Determine CLK */
+ ck = get_sdram_clk_rate();
+ /* Configure SDRAM */
+ writel(dram->cmddelay, &clk->sdramclk_ctrl);
+ writel(dram->config0, &emc->config0);
+ writel(dram->rascas0, &emc->rascas0);
+ writel(dram->rdconfig, &emc->read_config);
+ /* Set timings */
+ writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
+ writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
+ writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
+ writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
+ writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
+ writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
+ writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
+ writel(dram->trrd, &emc->t_rrd);
+ writel(dram->tmrd, &emc->t_mrd);
+ writel(dram->tcdlr, &emc->t_cdlr);
+ /* Dynamic refresh */
+ writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+ udelay(10);
+ /* Force all clocks, enable inverted ck, issue NOP command */
+ writel(0x00000193, &emc->control);
+ udelay(100);
+ /* Keep all clocks enabled, issue a PRECHARGE ALL command */
+ writel(0x00000113, &emc->control);
+ /* Fast dynamic refresh for at least a few SDRAM ck cycles */
+ writel((((128) >> 4) & 0x7FF), &emc->refresh);
+ udelay(10);
+ /* set correct dynamic refresh timing */
+ writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
+ udelay(10);
+ /* set normal mode to CAS=3 */
+ writel(0x00000093, &emc->control);
+ readl(EMC_DYCS0_BASE | dram->mode);
+ /* set extended mode to all zeroes */
+ writel(0x00000093, &emc->control);
+ readl(EMC_DYCS0_BASE | dram->emode);
+ /* stop forcing clocks, keep inverted clock, issue normal mode */
+ writel(0x00000010, &emc->control);
+}
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
new file mode 100644
index 0000000..4b8053e
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
@@ -0,0 +1,45 @@
+/*
+ * WORK Microwave work_92105 board low level init
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * Low level init is called from SPL to set up the clocks.
+ * On entry, the LPC3250 is in Direct Run mode with all clocks
+ * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is
+ * 104 MHz and PCLK is 13 MHz.
+ *
+ * This code must run from SRAM so that the clock changes do
+ * not prevent it from executing.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+.globl lowlevel_init
+
+lowlevel_init:
+
+ /* Set ARM, HCLK, PCLK dividers for normal mode */
+ ldr r0, =0x0000003D
+ ldr r1, =0x40004040
+ str r0, [r1]
+
+ /* Start HCLK PLL for 208 MHz */
+ ldr r0, =0x0001401E
+ ldr r1, =0x40004058
+ str r0, [r1]
+
+ /* wait for HCLK PLL to lock */
+1:
+ ldr r0, [r1]
+ ands r0, r0, #1
+ beq 1b
+
+ /* switch to normal mode */
+ ldr r1, =0x40004044
+ ldr r0, [r1]
+ orr r0, #0x00000004
+ str r0, [r1]
+
+ /* Return to U-boot via saved link register */
+ mov pc, lr
diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk
deleted file mode 100644
index 438668d..0000000
--- a/arch/arm/cpu/arm946es/config.mk
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk
index 6c82c3b..63591d4 100644
--- a/arch/arm/cpu/armv7/config.mk
+++ b/arch/arm/cpu/armv7/config.mk
@@ -5,11 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# If armv7-a is not supported by GCC fall-back to armv5, which is
-# supported by more tool-chains
-PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
-
# On supported platforms we set the bit which causes us to trap on unaligned
# memory access. This is the opposite of what the compiler expects to be
# the default so we must pass in -mno-unaligned-access so that it is aware
diff --git a/arch/arm/cpu/armv8/config.mk b/arch/arm/cpu/armv8/config.mk
index f5b9559..6850258 100644
--- a/arch/arm/cpu/armv8/config.mk
+++ b/arch/arm/cpu/armv8/config.mk
@@ -6,7 +6,5 @@
#
PLATFORM_RELFLAGS += -fno-common -ffixed-x18
-PF_CPPFLAGS_ARMV8 := $(call cc-option, -march=armv8-a)
PF_NO_UNALIGNED := $(call cc-option, -mstrict-align)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV8)
PLATFORM_CPPFLAGS += $(PF_NO_UNALIGNED)
diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk
index 525f5d3..7fb5316 100644
--- a/arch/arm/cpu/pxa/config.mk
+++ b/arch/arm/cpu/pxa/config.mk
@@ -6,8 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-PLATFORM_CPPFLAGS += -mcpu=xscale
-
#
# !WARNING!
# The PXA's OneNAND SPL uses .text.0 and .text.1 segments to allow booting from
diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk
deleted file mode 100644
index 3afa685..0000000
--- a/arch/arm/cpu/sa1100/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
-# Marius Groeger <mgroeger@sysgo.de>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..9449869 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -71,6 +71,7 @@ struct clk_pm_regs {
};
/* HCLK Divider Control Register bits */
+#define CLK_HCLK_DDRAM_MASK (0x3 << 7)
#define CLK_HCLK_DDRAM_HALF (0x2 << 7)
#define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7)
#define CLK_HCLK_DDRAM_STOPPED (0x0 << 7)
@@ -123,6 +124,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 << 1)
#define CLK_MAC_REG (1 << 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE (1 << 1)
+#define CLK_I2C1_ENABLE (1 << 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 << 6)
#define CLK_TIMCLK_TIMER3 (1 << 5)
@@ -147,11 +152,22 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 << 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 << 1)
+#define CLK_NAND_MLC_INT (1 << 5)
+
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 << 0)
+
+/* SDRAMCLK register bits */
+#define CLK_SDRAM_DDR_SEL (1 << 1)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
unsigned int get_hclk_clk_rate(void);
unsigned int get_periph_clk_div(void);
unsigned int get_periph_clk_rate(void);
+unsigned int get_sdram_clk_rate(void);
#endif /* _LPC32XX_CLK_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h b/arch/arm/include/asm/arch-lpc32xx/config.h
index 564441c..d57bc48 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -52,6 +52,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..0b5dca1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -27,6 +27,7 @@
#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
#define RTC_BASE 0x40024000 /* RTC registers base */
#define GPIO_BASE 0x40028000 /* GPIO registers base */
+#define MUX_BASE 0x40028100 /* MUX registers base */
#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
@@ -37,6 +38,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base */
#define UART5_BASE 0x40090000 /* UART 5 registers base */
#define UART6_BASE 0x40098000 /* UART 6 registers base */
+#define I2C1_BASE 0x400A0000 /* I2C 1 registers base */
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base */
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/emc.h b/arch/arm/include/asm/arch-lpc32xx/emc.h
index 82d9bcc..1a2bab2 100644
--- a/arch/arm/include/asm/arch-lpc32xx/emc.h
+++ b/arch/arm/include/asm/arch-lpc32xx/emc.h
@@ -76,4 +76,25 @@ struct emc_regs {
#define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F)
#define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F)
+/* EMC settings for DRAM */
+struct emc_dram_settings {
+ u32 cmddelay;
+ u32 config0;
+ u32 rascas0;
+ u32 rdconfig;
+ u32 trp;
+ u32 tras;
+ u32 tsrex;
+ u32 twr;
+ u32 trc;
+ u32 trfc;
+ u32 txsr;
+ u32 trrd;
+ u32 tmrd;
+ u32 tcdlr;
+ u32 refresh;
+ u32 mode;
+ u32 emode;
+};
+
#endif /* _LPC32XX_EMC_H */
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 0000000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/mux.h b/arch/arm/include/asm/arch-lpc32xx/mux.h
new file mode 100644
index 0000000..dc1b5bc
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/mux.h
@@ -0,0 +1,18 @@
+/*
+ * LPC32xx MUX interface
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/**
+ * MUX register map for LPC32xx
+ */
+
+struct mux_regs {
+ u32 p_mux_set;
+ u32 p_mux_clr;
+ u32 p_mux_state;
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be3..c3d890d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -7,6 +7,14 @@
#ifndef _LPC32XX_SYS_PROTO_H
#define _LPC32XX_SYS_PROTO_H
-void lpc32xx_uart_init(unsigned int uart_id);
+#include <asm/arch/emc.h>
+void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
+#if defined(CONFIG_SPL_BUILD)
+void ddr_init(const struct emc_dram_settings *dram);
+#endif
#endif /* _LPC32XX_SYS_PROTO_H */