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authorTom Rini <trini@ti.com>2014-01-16 13:50:16 -0500
committerTom Rini <trini@ti.com>2014-01-16 13:50:16 -0500
commit4913fc23f0b19a82e2e9cc56f7ee0087839855c4 (patch)
treeb3229e94d952021236a6ec29e6bfe1d6fd050dee /arch
parentb5c068f3f8be5c2f73fc6699885aec0d342099bb (diff)
parentc71b4dd2da0dcddabd7c29e6c3dc8a495d4bd928 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c8
-rw-r--r--arch/arm/include/asm/arch-mx6/clock.h9
-rw-r--r--arch/arm/include/asm/arch-mx6/imx-regs.h4
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7790.h1
-rw-r--r--arch/arm/include/asm/arch-rmobile/r8a7791.h1
5 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index f12bba2..5617a41 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -323,7 +323,7 @@ static u32 get_mmdc_ch0_clk(void)
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(void)
+int enable_fec_anatop_clock(enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
@@ -331,7 +331,13 @@ int enable_fec_anatop_clock(void)
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+ if (freq < ENET_25MHz || freq > ENET_125MHz)
+ return -EINVAL;
+
reg = readl(&anatop->pll_enet);
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= freq;
+
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 93f29a7..e31ba0a 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -42,6 +42,13 @@ enum mxc_clock {
MXC_I2C_CLK,
};
+enum enet_freq {
+ ENET_25MHz,
+ ENET_50MHz,
+ ENET_100MHz,
+ ENET_125MHz,
+};
+
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
@@ -50,5 +57,5 @@ void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
void enable_ipu_clock(void);
-int enable_fec_anatop_clock(void);
+int enable_fec_anatop_clock(enum enet_freq freq);
#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index fb0c4c7..7f89865 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -245,6 +245,10 @@ struct src {
u32 gpr10;
};
+/* GPR1 bitfields */
+#define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
+#define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
+
/* GPR3 bitfields */
#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
index 42d65d3..d9ea71f 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -19,6 +19,7 @@
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index 2afda0a..ff30180 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -19,6 +19,7 @@
#define DBSC3_1_BASE 0xE67A0000
#define TMU_BASE 0xE61E0000
#define GPIO5_BASE 0xE6055000
+#define SH_QSPI_BASE 0xE6B10000
#define S3C_BASE 0xE6784000
#define S3C_INT_BASE 0xE6784A00