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authorMacpaul Lin <macpaul@andestech.com>2011-10-24 16:48:39 +0800
committerMacpaul Lin <macpaul@andestech.com>2011-11-01 12:47:17 +0800
commit466e73b19b34a1500303faffc4b17d849438fad0 (patch)
tree13a25eefcb34754baddf90c12fb79b9becdffa7e /arch
parent569bc625e3123f9c9bf7406c2cd37f93d2cdc416 (diff)
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nds32: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Add ARCH_DMA_MINALIGN definition to asm/cache.h Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/nds32/include/asm/cache.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/nds32/include/asm/cache.h b/arch/nds32/include/asm/cache.h
index d769196..fc22c7b 100644
--- a/arch/nds32/include/asm/cache.h
+++ b/arch/nds32/include/asm/cache.h
@@ -51,4 +51,15 @@ DEFINE_GET_SYS_REG(DCM_CFG);
#define DCM_CFG_OFF_DSZ 6 /* D-cache line size */
#define DCM_CFG_MSK_DSZ (0x7UL << DCM_CFG_OFF_DSZ)
+/*
+ * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
+ * We use that value for aligning DMA buffers unless the board config has
+ * specified an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN 32
+#endif
+
#endif /* _ASM_CACHE_H */