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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2015-01-19 22:31:10 +0900
committerMasahiro Yamada <yamada.m@jp.panasonic.com>2015-01-23 00:50:57 +0900
commit448437496b7cb2b7a80d4b3ada9f225506379c5c (patch)
tree12dc9f56fd38004aa88e646bd06e4f5983e8f171 /arch
parent061ae4c0bbe8df9aeedfa4a1e6a6dc122a4c157f (diff)
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ARM: UniPhier: fix IECTRL set code for PH1-Pro4
For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
index 2cc5df6..b7c4b10 100644
--- a/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
+++ b/arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
@@ -23,6 +23,6 @@ void sg_init(void)
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
- tmp |= 0x1;
+ tmp |= 1 << 6;
writel(tmp, SG_IECTRL);
}