Merge git://git.denx.de/u-boot

245 files changed, 7491 insertions, 8171 deletions

diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile
index c63dc92..c1d4d67 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/Makefile
+++ b/arch/arm/cpu/arm1176/tnetv107x/Makefile
@@ -21,7 +21,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= aemif.o clock.o init.o mux.o timer.o wdt.o
+COBJS	+= aemif.o clock.o init.o mux.o timer.o
 SOBJS	+= lowlevel_init.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c
index e26fec1..16876ae 100644
--- a/arch/arm/cpu/arm1176/tnetv107x/clock.c
+++ b/arch/arm/cpu/arm1176/tnetv107x/clock.c
@@ -168,10 +168,6 @@ static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff };
 #define tdm_extra_clk		{TDM_PLL, 1}
 #define tdm1_clk		{TDM_PLL, 2}
 
-/* Optimization barrier */
-#define barrier()	\
-	__asm__ __volatile__("mov r0, r0\n" : : : "memory");
-
 static const struct lpsc_map lpsc_clk_map[] = {
 	[TNETV107X_LPSC_ARM]			= sys_arm1176_clk,
 	[TNETV107X_LPSC_GEM]			= sys_dsp_clk,
diff --git a/arch/arm/cpu/arm1176/tnetv107x/wdt.c b/arch/arm/cpu/arm1176/tnetv107x/wdt.c
deleted file mode 100644
index 18aadb0..0000000
--- a/arch/arm/cpu/arm1176/tnetv107x/wdt.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * TNETV107X: Watchdog timer implementation (for reset)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-
-#define MAX_DIV		0xFFFE0001
-
-struct wdt_regs {
-	u32 kick_lock;
-#define KICK_LOCK_1	0x5555
-#define KICK_LOCK_2	0xaaaa
-	u32 kick;
-
-	u32 change_lock;
-#define CHANGE_LOCK_1	0x6666
-#define CHANGE_LOCK_2	0xbbbb
-	u32 change;
-
-	u32 disable_lock;
-#define DISABLE_LOCK_1	0x7777
-#define DISABLE_LOCK_2	0xcccc
-#define DISABLE_LOCK_3	0xdddd
-	u32 disable;
-
-	u32 prescale_lock;
-#define PRESCALE_LOCK_1	0x5a5a
-#define PRESCALE_LOCK_2	0xa5a5
-	u32 prescale;
-};
-
-static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE;
-
-#define wdt_reg_read(reg)	__raw_readl(&regs->reg)
-#define wdt_reg_write(reg, val)	__raw_writel((val), &regs->reg)
-
-static int write_prescale_reg(unsigned long prescale_value)
-{
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_1);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(prescale_lock, PRESCALE_LOCK_2);
-	if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(prescale, prescale_value);
-
-	return 0;
-}
-
-static int write_change_reg(unsigned long initial_timer_value)
-{
-	wdt_reg_write(change_lock, CHANGE_LOCK_1);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(change_lock, CHANGE_LOCK_2);
-	if ((wdt_reg_read(change_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(change, initial_timer_value);
-
-	return 0;
-}
-
-static int wdt_control(unsigned long disable_value)
-{
-	wdt_reg_write(disable_lock, DISABLE_LOCK_1);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_2);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x2)
-		return -1;
-
-	wdt_reg_write(disable_lock, DISABLE_LOCK_3);
-	if ((wdt_reg_read(disable_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(disable, disable_value);
-	return 0;
-}
-
-static int wdt_set_period(unsigned long msec)
-{
-	unsigned long change_value, count_value;
-	unsigned long prescale_value = 1;
-	unsigned long refclk_khz, maxdiv;
-	int ret;
-
-	refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM);
-	maxdiv = (MAX_DIV / refclk_khz);
-
-	if ((!msec) || (msec > maxdiv))
-		return -1;
-
-	count_value = refclk_khz * msec;
-	if (count_value > 0xffff) {
-		change_value = count_value / 0xffff + 1;
-		prescale_value = count_value / change_value;
-	} else {
-		change_value = count_value;
-	}
-
-	ret = write_prescale_reg(prescale_value - 1);
-	if (ret)
-		return ret;
-
-	ret = write_change_reg(change_value);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-unsigned long last_wdt = -1;
-
-int wdt_start(unsigned long msecs)
-{
-	int ret;
-	ret = wdt_control(0);
-	if (ret)
-		return ret;
-	ret = wdt_set_period(msecs);
-	if (ret)
-		return ret;
-	ret = wdt_control(1);
-	if (ret)
-		return ret;
-	ret = wdt_kick();
-	last_wdt = msecs;
-	return ret;
-}
-
-int wdt_stop(void)
-{
-	last_wdt = -1;
-	return wdt_control(0);
-}
-
-int wdt_kick(void)
-{
-	wdt_reg_write(kick_lock, KICK_LOCK_1);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x1)
-		return -1;
-
-	wdt_reg_write(kick_lock, KICK_LOCK_2);
-	if ((wdt_reg_read(kick_lock) & 0x3) != 0x3)
-		return -1;
-
-	wdt_reg_write(kick, 1);
-	return 0;
-}
-
-void reset_cpu(ulong addr)
-{
-	clk_enable(TNETV107X_LPSC_WDT_ARM);
-	wdt_start(1);
-	wdt_kick();
-}
diff --git a/arch/arm/cpu/arm720t/cpu.c b/arch/arm/cpu/arm720t/cpu.c
index ce7b3c9..820614e 100644
--- a/arch/arm/cpu/arm720t/cpu.c
+++ b/arch/arm/cpu/arm720t/cpu.c
@@ -27,34 +27,12 @@
  */
 
 /*
- * CPU specific code
+ * cleanup_before_linux() - Prepare the CPU to jump to Linux
+ *
+ * This function is called just before we call Linux, it
+ * prepares the processor for linux
  */
-
-#include <common.h>
-#include <command.h>
-#include <clps7111.h>
-#include <asm/hardware.h>
-#include <asm/system.h>
-
-int cleanup_before_linux (void)
+int cleanup_before_linux(void)
 {
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 * and we set the CPU-speed to 73 MHz - see start.S for details
-	 */
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292)
-	disable_interrupts ();
-	/* Nothing more needed */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No cleanup before linux for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-	/* No cleanup before linux for tegra as yet */
-#else
-#error No cleanup_before_linux() defined for this CPU type
-#endif
 	return 0;
 }
diff --git a/arch/arm/cpu/arm720t/interrupts.c b/arch/arm/cpu/arm720t/interrupts.c
index c2f898f..623a24b 100644
--- a/arch/arm/cpu/arm720t/interrupts.c
+++ b/arch/arm/cpu/arm720t/interrupts.c
@@ -27,266 +27,23 @@
  */
 
 #include <common.h>
-#include <clps7111.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/hardware.h>
-
-#ifndef CONFIG_NETARM
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-/* macro to read the 16 bit timer */
-#define READ_TIMER (IO_TC1D & 0xffff)
-
-#ifdef CONFIG_LPC2292
-#undef READ_TIMER
-#define READ_TIMER (0xFFFFFFFF - GET32(T0TC))
-#endif
-
-#else
-#define IRQEN	(*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_INTR_ENABLE))
-#define TM2CTRL (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_CONTROL))
-#define TM2STAT (*(volatile unsigned int *)(NETARM_GEN_MODULE_BASE + NETARM_GEN_TIMER2_STATUS))
-#define TIMER_LOAD_VAL NETARM_GEN_TSTAT_CTC_MASK
-#define READ_TIMER (TM2STAT & NETARM_GEN_TSTAT_CTC_MASK)
-#endif
-
-#ifdef CONFIG_S3C4510B
-/* require interrupts for the S3C4510B */
-# ifndef CONFIG_USE_IRQ
-#  error CONFIG_USE_IRQ _must_ be defined when using CONFIG_S3C4510B
-# else
-static struct _irq_handler IRQ_HANDLER[N_IRQS];
-# endif
-#endif	/* CONFIG_S3C4510B */
 
 #ifdef CONFIG_USE_IRQ
 void do_irq (struct pt_regs *pt_regs)
 {
-#if defined(CONFIG_S3C4510B)
-	unsigned int pending;
-
-	while ( (pending = GET_REG( REG_INTOFFSET)) != 0x54) {  /* sentinal value for no pending interrutps */
-		IRQ_HANDLER[pending>>2].m_func( IRQ_HANDLER[pending>>2].m_data);
-
-		/* clear pending interrupt */
-		PUT_REG( REG_INTPEND, (1<<(pending>>2)));
-	}
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No do_irq() for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-
-    void (*pfnct)(void);
-
-    pfnct = (void (*)(void))VICVectAddr;
-
-    (*pfnct)();
-#else
-#error do_irq() not defined for this CPU type
-#endif
-}
-#endif
-
-#ifdef CONFIG_S3C4510B
-static void default_isr( void *data) {
-	printf ("default_isr():  called for IRQ %d\n", (int)data);
-}
-
-static void timer_isr( void *data) {
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-	if ( !(*pTime % (CONFIG_SYS_HZ/4))) {
-		/* toggle LED 0 */
-		PUT_REG( REG_IOPDATA, GET_REG(REG_IOPDATA) ^ 0x1);
-	}
-
 }
 #endif
 
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* Use IntegratorAP routines in board/integratorap.c */
-#else
-
+#if defined(CONFIG_TEGRA)
 static ulong timestamp;
 static ulong lastdec;
 
-#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int arch_interrupt_init (void)
-{
-	int i;
-
-	/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
-	/* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-	lastdec = 0;
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
-	return 0;
-}
-#endif
-
 int timer_init (void)
 {
-#if defined(CONFIG_NETARM)
-	/* disable all interrupts */
-	IRQEN = 0;
-
-	/* operate timer 2 in non-prescale mode */
-	TM2CTRL = ( NETARM_GEN_TIMER_SET_HZ(CONFIG_SYS_HZ) |
-		    NETARM_GEN_TCTL_ENABLE |
-		    NETARM_GEN_TCTL_INIT_COUNT(TIMER_LOAD_VAL));
-
-	/* set timer 2 counter */
-	lastdec = TIMER_LOAD_VAL;
-#elif defined(CONFIG_S3C4510B)
-	/* configure free running timer 0 */
-	PUT_REG( REG_TMOD, 0x0);
-	/* Stop timer 0 */
-	CLR_REG( REG_TMOD, TM0_RUN);
-
-	/* Configure for interval mode */
-	CLR_REG( REG_TMOD, TM1_TOGGLE);
-
-	/*
-	 * Load Timer data register with count down value.
-	 * count_down_val = CONFIG_SYS_SYS_CLK_FREQ/CONFIG_SYS_HZ
-	 */
-	PUT_REG( REG_TDATA0, (CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ));
-
-	/*
-	 * Enable global interrupt
-	 * Enable timer0 interrupt
-	 */
-	CLR_REG( REG_INTMASK, ((1<<INT_GLOBAL) | (1<<INT_TIMER0)));
-
-	/* Start timer */
-	SET_REG( REG_TMOD, TM0_RUN);
-#elif defined(CONFIG_LPC2292)
-	PUT32(T0IR, 0);		/* disable all timer0 interrupts */
-	PUT32(T0TCR, 0);	/* disable timer0 */
-	PUT32(T0PR, CONFIG_SYS_SYS_CLK_FREQ / CONFIG_SYS_HZ);
-	PUT32(T0MCR, 0);
-	PUT32(T0TC, 0);
-	PUT32(T0TCR, 1);	/* enable timer0 */
-
-#elif defined(CONFIG_TEGRA)
 	/* No timer routines for tegra as yet */
 	lastdec = 0;
-#else
-#error No timer_init() defined for this CPU type
-#endif
 	timestamp = 0;
 
-	return (0);
-}
-
-#endif /* ! IntegratorAP */
-
-/*
- * timer without interrupts
- */
-
-
-#if defined(CONFIG_NETARM) || defined(CONFIG_LPC2292)
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 1000;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-#ifdef CONFIG_LPC2292
-		/* GJ - not sure whether this is really needed or a misunderstanding */
-		__asm__ __volatile__(" nop");
-#else
-		/*NOP*/;
-#endif
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-#elif defined(CONFIG_S3C4510B)
-
-ulong get_timer (ulong base)
-{
-	return timestamp - base;
-}
-
-void __udelay (unsigned long usec)
-{
-	u32 ticks;
-
-	ticks = (usec * CONFIG_SYS_HZ) / 1000000;
-
-	ticks += get_timer (0);
-
-	while (get_timer (0) < ticks)
-		/*NOP*/;
-
+	return 0;
 }
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No timer routines for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_TEGRA)
-	/* No timer routines for tegra as yet */
-#else
-#error Timer routines not defined for this CPU type
 #endif
diff --git a/arch/arm/cpu/arm720t/lpc2292/Makefile b/arch/arm/cpu/arm720t/lpc2292/Makefile
deleted file mode 100644
index 1b93008..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS	= flash.o mmc.o mmc_hw.o spi.o
-SOBJS	= $(obj)iap_entry.o
-
-SRCS	:= $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-# this MUST be compiled as thumb code!
-$(SOBJS):
-	$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/lpc2292/flash.c b/arch/arm/cpu/arm720t/lpc2292/flash.c
deleted file mode 100644
index 3d2dc32..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/flash.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
- *
- * Modified to remove all but the IAP-command related code by
- * Gary Jennejohn <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-/* IAP commands use 32 bytes at the top of CPU internal sram, we
-   use 512 bytes below that */
-#define COPY_BUFFER_LOCATION 0x40003de0
-
-#define IAP_LOCATION 0x7ffffff1
-#define IAP_CMD_PREPARE 50
-#define IAP_CMD_COPY 51
-#define IAP_CMD_ERASE 52
-#define IAP_CMD_CHECK 53
-#define IAP_CMD_ID 54
-#define IAP_CMD_VERSION 55
-#define IAP_CMD_COMPARE 56
-
-#define IAP_RET_CMD_SUCCESS 0
-
-static unsigned long command[5];
-static unsigned long result[2];
-
-extern void iap_entry(unsigned long * command, unsigned long * result);
-
-/*-----------------------------------------------------------------------
- *
- */
-static int get_flash_sector(flash_info_t * info, ulong flash_addr)
-{
-	int i;
-
-	for(i = 1; i < (info->sector_count); i++) {
-		if (flash_addr < (info->start[i]))
-			break;
-	}
-
-	return (i-1);
-}
-
-/*-----------------------------------------------------------------------
- * This function assumes that flash_addr is aligned on 512 bytes boundary
- * in flash. This function also assumes that prepare have been called
- * for the sector in question.
- */
-int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
-{
-	int first_sector;
-	int last_sector;
-
-	first_sector = get_flash_sector(info, flash_addr);
-	last_sector = get_flash_sector(info, flash_addr + 512 - 1);
-
-	/* prepare sectors for write */
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = first_sector;
-	command[2] = last_sector;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROG_ERROR;
-	}
-
-	command[0] = IAP_CMD_COPY;
-	command[1] = flash_addr;
-	command[2] = COPY_BUFFER_LOCATION;
-	command[3] = 512;
-	command[4] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP copy failed\n");
-		return 1;
-	}
-
-	return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag;
-	int prot;
-	int sect;
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-
-	flag = disable_interrupts();
-
-	printf ("Erasing %d sectors starting at sector %2d.\n"
-	"This make take some time ... ",
-	s_last - s_first + 1, s_first);
-
-	command[0] = IAP_CMD_PREPARE;
-	command[1] = s_first;
-	command[2] = s_last;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP prepare failed\n");
-		return ERR_PROTECTED;
-	}
-
-	command[0] = IAP_CMD_ERASE;
-	command[1] = s_first;
-	command[2] = s_last;
-	command[3] = CONFIG_SYS_SYS_CLK_FREQ >> 10;
-	iap_entry(command, result);
-	if (result[0] != IAP_RET_CMD_SUCCESS) {
-		printf("IAP erase failed\n");
-		return ERR_PROTECTED;
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return ERR_OK;
-}
-
-int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
-			ulong cnt)
-{
-	int first_copy_size;
-	int last_copy_size;
-	int first_block;
-	int last_block;
-	int nbr_mid_blocks;
-	uchar memmap_value;
-	ulong i;
-	uchar* src_org;
-	uchar* dst_org;
-	int ret = ERR_OK;
-
-	src_org = src;
-	dst_org = (uchar*)addr;
-
-	first_block = addr / 512;
-	last_block = (addr + cnt) / 512;
-	nbr_mid_blocks = last_block - first_block - 1;
-
-	first_copy_size = 512 - (addr % 512);
-	last_copy_size = (addr + cnt) % 512;
-
-	debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
-	(ulong)(first_block * 512),
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)src,
-	(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-	first_copy_size,
-	(ulong)COPY_BUFFER_LOCATION,
-	(ulong)(first_block * 512));
-
-	/* copy first block */
-	memcpy((void*)COPY_BUFFER_LOCATION,
-		(void*)(first_block * 512), 512);
-	memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
-		src, first_copy_size);
-	lpc2292_copy_buffer_to_flash(info, first_block * 512);
-	src += first_copy_size;
-	addr += first_copy_size;
-
-	/* copy middle blocks */
-	for (i = 0; i < nbr_mid_blocks; i++) {
-		debug("copy middle block: %lX -> %lX 512 bytes, "
-		"%lX -> %lX 512 bytes\n",
-		(ulong)src,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-
-		memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
-		lpc2292_copy_buffer_to_flash(info, addr);
-		src += 512;
-		addr += 512;
-	}
-
-
-	if (last_copy_size > 0) {
-		debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
-		"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
-		(ulong)(last_block * 512),
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)src,
-		(ulong)(COPY_BUFFER_LOCATION),
-		last_copy_size,
-		(ulong)COPY_BUFFER_LOCATION,
-		(ulong)addr);
-
-		/* copy last block */
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			(void*)(last_block * 512), 512);
-		memcpy((void*)COPY_BUFFER_LOCATION,
-			src, last_copy_size);
-		lpc2292_copy_buffer_to_flash(info, addr);
-	}
-
-	/* verify write */
-	memmap_value = GET8(MEMMAP);
-
-	disable_interrupts();
-
-	PUT8(MEMMAP, 01);		/* we must make sure that initial 64
-							   bytes are taken from flash when we
-							   do the compare */
-
-	for (i = 0; i < cnt; i++) {
-		if (*dst_org != *src_org){
-			printf("Write failed. Byte %lX differs\n", i);
-			ret = ERR_PROG_ERROR;
-			break;
-		}
-		dst_org++;
-		src_org++;
-	}
-
-	PUT8(MEMMAP, memmap_value);
-	enable_interrupts();
-
-	return ret;
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S b/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
deleted file mode 100644
index c31d519..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/iap_entry.S
+++ /dev/null
@@ -1,7 +0,0 @@
-IAP_ADDRESS:	.word	0x7FFFFFF1
-
-.globl iap_entry
-iap_entry:
-	ldr	r2, IAP_ADDRESS
-	bx	r2
-	mov	pc, lr
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc.c b/arch/arm/cpu/arm720t/lpc2292/mmc.c
deleted file mode 100644
index beaffe9..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc.c
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <common.h>
-#include <mmc.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <part.h>
-#include <fat.h>
-#include "mmc_hw.h"
-#include <asm/arch/spi.h>
-
-#ifdef CONFIG_MMC
-
-#undef MMC_DEBUG
-
-static block_dev_desc_t mmc_dev;
-
-/* these are filled out by a call to mmc_hw_get_parameters */
-static int hw_size;		/* in kbytes */
-static int hw_nr_sects;
-static int hw_sect_size;	/* in bytes */
-
-block_dev_desc_t * mmc_get_dev(int dev)
-{
-	return (block_dev_desc_t *)(&mmc_dev);
-}
-
-unsigned long mmc_block_read(int dev,
-			     unsigned long start,
-			     lbaint_t blkcnt,
-			     void *buffer)
-{
-	unsigned long rc = 0;
-	unsigned char *p = (unsigned char *)buffer;
-	unsigned long i;
-	unsigned long addr = start;
-
-#ifdef MMC_DEBUG
-	printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start,
-		 (unsigned long)blkcnt);
-#endif
-
-	for(i = 0; i < (unsigned long)blkcnt; i++) {
-#ifdef MMC_DEBUG
-		printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p);
-#endif
-		(void)mmc_read_sector(addr, p);
-		rc++;
-		addr++;
-		p += hw_sect_size;
-	}
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------------
- * Read hardware paramterers (sector size, size, number of sectors)
- */
-static int mmc_hw_get_parameters(void)
-{
-	unsigned char csddata[16];
-	unsigned int sizemult;
-	unsigned int size;
-
-	mmc_read_csd(csddata);
-	hw_sect_size = 1<<(csddata[5] & 0x0f);
-	size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0);
-	sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1);
-	hw_nr_sects = (size+1)*(1<<(sizemult+2));
-	hw_size = hw_nr_sects*hw_sect_size/1024;
-
-#ifdef MMC_DEBUG
-	printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, "
-		 "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size);
-#endif
-
-	return 0;
-}
-
-int mmc_legacy_init(int verbose)
-{
-	int ret = -ENODEV;
-
-	if (verbose)
-		printf("mmc_legacy_init\n");
-
-	spi_init();
-	/* this meeds to be done twice */
-	mmc_hw_init();
-	udelay(1000);
-	mmc_hw_init();
-
-	mmc_hw_get_parameters();
-
-	mmc_dev.if_type = IF_TYPE_MMC;
-	mmc_dev.part_type = PART_TYPE_DOS;
-	mmc_dev.dev = 0;
-	mmc_dev.lun = 0;
-	mmc_dev.type = 0;
-	mmc_dev.blksz = hw_sect_size;
-	mmc_dev.lba = hw_nr_sects;
-	sprintf((char*)mmc_dev.vendor, "Unknown vendor");
-	sprintf((char*)mmc_dev.product, "Unknown product");
-	sprintf((char*)mmc_dev.revision, "N/A");
-	mmc_dev.removable = 0;	/* should be true??? */
-	mmc_dev.block_read = mmc_block_read;
-
-	fat_register_device(&mmc_dev, 1);
-
-	ret = 0;
-
-	return ret;
-}
-
-#endif /* CONFIG_MMC */
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
deleted file mode 100644
index bd6a5b1..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
-    This code was original written by Ulrich Radig and modified by
-    Embedded Artists AB (www.embeddedartists.com).
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
-#define MMC_Disable() PUT32(IO1SET, 1l << 22)
-#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0);
-
-static unsigned char Write_Command_MMC (unsigned char *CMD);
-static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer,
-		    unsigned short int Bytes);
-
-/* initialize the hardware */
-int mmc_hw_init(void)
-{
-	unsigned long a;
-	unsigned short int Timeout = 0;
-	unsigned char b;
-	unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95};
-
-	/* set-up GPIO and SPI */
-	(*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */
-	(*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */
-
-	MMC_Disable();
-
-	spi_lock();
-	spi_set_clock(248);
-	spi_set_cfg(0, 1, 0);
-	MMC_Enable();
-
-	/* waste some time */
-	for(a=0; a < 20000; a++)
-		asm("nop");
-
-	/* Put the MMC/SD-card into SPI-mode */
-	for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */
-		spi_write(0xff);
-
-	/* Sends command CMD0 to MMC/SD-card */
-	while (Write_Command_MMC(CMD) != 1) {
-		if (Timeout++ > 200) {
-			MMC_Disable();
-			spi_unlock();
-			return(1); /* Abort with command 1 (return 1) */
-		}
-	}
-	/* Sends Command CMD1 an MMC/SD-card */
-	Timeout = 0;
-	CMD[0] = 0x41;/* Command 1 */
-	CMD[5] = 0xFF;
-
-	while (Write_Command_MMC(CMD) != 0) {
-		if (Timeout++ > 200) {
-			MMC_Disable();
-			spi_unlock();
-			return (2); /* Abort with command 2 (return 2) */
-		}
-	}
-
-	MMC_Disable();
-	spi_unlock();
-
-	return 0;
-}
-
-/* ############################################################################
-   Sends a command to the MMC/SD-card
-   ######################################################################### */
-static unsigned char Write_Command_MMC (unsigned char *CMD)
-{
-	unsigned char a, tmp = 0xff;
-	unsigned short int Timeout = 0;
-
-	MMC_Disable();
-	spi_write(0xFF);
-	MMC_Enable();
-
-	for (a = 0; a < 0x06; a++)
-		spi_write(*CMD++);
-
-	while (tmp == 0xff) {
-		tmp = spi_read();
-		if (Timeout++ > 5000)
-		  break;
-	}
-
-	return (tmp);
-}
-
-/* ############################################################################
-   Routine to read the CID register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short
-	int Bytes)
-{
-	unsigned short int a;
-
-	spi_lock();
-	mmc_spi_cfg();
-	MMC_Enable();
-
-	if (Write_Command_MMC(CMD) != 0) {
-		MMC_Disable();
-		spi_unlock();
-		return;
-	}
-
-	while (spi_read() != 0xfe) {};
-	for (a = 0; a < Bytes; a++)
-		*Buffer++ = spi_read();
-
-	/* Read the CRC-byte */
-	spi_read(); /* CRC - byte is discarded */
-	spi_read(); /* CRC - byte is discarded */
-	/* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */
-	MMC_Disable();
-	spi_unlock();
-
-	return;
-}
-
-/* ############################################################################
-   Routine to read a block (512 bytes) from the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer)
-{
-	/* Command 16 to read aBlocks from the MMC/SD - caed */
-	unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
-
-	/* The address on the MMC/SD-card is in bytes,
-	addr is transformed from blocks to bytes and the result is
-	placed into the command */
-
-	addr = addr << 9; /* addr = addr * 512 */
-
-	CMD[1] = ((addr & 0xFF000000) >> 24);
-	CMD[2] = ((addr & 0x00FF0000) >> 16);
-	CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-	MMC_Read_Block(CMD, Buffer, 512);
-
-	return (0);
-}
-
-/* ############################################################################
-   Routine to write a block (512 byte) to the MMC/SD-card
-   ######################################################################### */
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer)
-{
-	unsigned char tmp, a;
-	unsigned short int b;
-	/* Command 24 to write a block to the MMC/SD - card */
-	unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-	/* The address on the MMC/SD-card is in bytes,
-	addr is transformed from blocks to bytes and the result is
-	placed into the command */
-
-	addr = addr << 9; /* addr = addr * 512 */
-
-	CMD[1] = ((addr & 0xFF000000) >> 24);
-	CMD[2] = ((addr & 0x00FF0000) >> 16);
-	CMD[3] = ((addr & 0x0000FF00) >> 8 );
-
-	spi_lock();
-	mmc_spi_cfg();
-	MMC_Enable();
-
-	/* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */
-	tmp = Write_Command_MMC(CMD);
-	if (tmp != 0) {
-		MMC_Disable();
-		spi_unlock();
-		return(tmp);
-	}
-
-	/* Do a short delay and send a clock-pulse to the MMC/SD-card */
-	for (a = 0; a < 100; a++)
-		spi_read();
-
-	/* Send a start byte to the MMC/SD-card */
-	spi_write(0xFE);
-
-	/* Write the block (512 bytes) to the MMC/SD-card */
-	for (b = 0; b < 512; b++)
-		spi_write(*Buffer++);
-
-	/* write the CRC-Byte */
-	spi_write(0xFF); /* write a dummy CRC */
-	spi_write(0xFF); /* CRC code is not used */
-
-	/* Wait for MMC/SD-card busy */
-	while (spi_read() != 0xff) {};
-
-	/* set MMC_Chip_Select to high (MMC/SD-card inactive) */
-	MMC_Disable();
-	spi_unlock();
-	return (0);
-}
-
-/* #########################################################################
-   Routine to read the CSD register from the MMC/SD-card (16 bytes)
-   ######################################################################### */
-unsigned char mmc_read_csd (unsigned char *Buffer)
-{
-	/* Command to read the CSD register */
-	unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF};
-
-	MMC_Read_Block(CMD, Buffer, 16);
-
-	return (0);
-}
diff --git a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h b/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
deleted file mode 100644
index 3687dbf..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/mmc_hw.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
-    This module implements a linux character device driver for the 24c256 chip.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef _MMC_HW_
-#define _MMC_HW_
-
-unsigned char mmc_read_csd(unsigned char *Buffer);
-unsigned char mmc_read_sector (unsigned long addr,
-			       unsigned char *Buffer);
-unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer);
-int mmc_hw_init(void);
-
-#endif /* _MMC_HW_ */
diff --git a/arch/arm/cpu/arm720t/lpc2292/spi.c b/arch/arm/cpu/arm720t/lpc2292/spi.c
deleted file mode 100644
index d296bda..0000000
--- a/arch/arm/cpu/arm720t/lpc2292/spi.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-    This module implements an interface to the SPI on the lpc22xx.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/spi.h>
-
-unsigned long spi_flags;
-unsigned char spi_idle = 0x00;
-
-int spi_init(void)
-{
-	unsigned long pinsel0_value;
-
-	/* activate spi pins */
-	pinsel0_value = GET32(PINSEL0);
-	pinsel0_value &= ~(0xFFl << 8);
-	pinsel0_value |= (0x55l << 8);
-	PUT32(PINSEL0, pinsel0_value);
-
-	return 0;
-}
diff --git a/arch/arm/cpu/arm720t/s3c4510b/Makefile b/arch/arm/cpu/arm720t/s3c4510b/Makefile
deleted file mode 100644
index 5c6df08..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/Makefile
+++ /dev/null
@@ -1,45 +0,0 @@
-#
-# (C) Copyright 2000-2008
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).o
-
-COBJS-y	+= cache.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(LIB)
-
-$(LIB):	$(OBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/arm/cpu/arm720t/s3c4510b/cache.c b/arch/arm/cpu/arm720t/s3c4510b/cache.c
deleted file mode 100644
index 104d287..0000000
--- a/arch/arm/cpu/arm720t/s3c4510b/cache.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-void icache_enable (void)
-{
-	s32 i;
-
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-
-	/* 8KB cache, write enable */
-	SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01);
-
-	/* clear TAG RAM bits */
-	for ( i = 0; i < 256; i++)
-	  PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000);
-
-	/* clear SET0 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000);
-
-	/* clear SET1 RAM */
-	for(i=0; i < 1024; i++)
-	  PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000);
-
-	/* enable cache */
-	SET_REG( REG_SYSCFG, CACHE_ENABLE);
-
-}
-
-void icache_disable (void)
-{
-	/* disable all cache bits */
-	CLR_REG( REG_SYSCFG, 0x3F);
-}
-
-int icache_status (void)
-{
-	return GET_REG( REG_SYSCFG) & CACHE_ENABLE;
-}
-
-void dcache_enable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_enable();
-}
-
-void dcache_disable (void)
-{
-	/* we don't have seperate instruction/data caches */
-	icache_disable();
-}
-
-int dcache_status (void)
-{
-	/* we don't have seperate instruction/data caches */
-	return icache_status();
-}
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index 2f914e9..c2a7763 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -43,11 +43,7 @@ _start: b	reset
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
 	ldr	pc, _data_abort
-#ifdef CONFIG_LPC2292
-	.word	0xB4405F76 /* 2's complement of the checksum of the vectors */
-#else
 	ldr	pc, _not_used
-#endif
 	ldr	pc, _irq
 	ldr	pc, _fiq
 
@@ -151,10 +147,6 @@ reset:
 	bl	cpu_init_crit
 #endif
 
-#ifdef CONFIG_LPC2292
-	bl	lowlevel_init
-#endif
-
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
@@ -291,148 +283,9 @@ _dynsym_start_ofs:
  *************************************************************************
  */
 
-#if defined(CONFIG_LPC2292)
-PLLCFG_ADR:	.word	PLLCFG
-PLLFEED_ADR:	.word	PLLFEED
-PLLCON_ADR:	.word	PLLCON
-PLLSTAT_ADR:	.word	PLLSTAT
-VPBDIV_ADR:	.word	VPBDIV
-MEMMAP_ADR:	.word	MEMMAP
-
-#endif
-
 cpu_init_crit:
-#if defined(CONFIG_NETARM)
-	/*
-	 * prior to software reset : need to set pin PORTC4 to be *HRESET
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =(NETARM_GEN_PORT_MODE(0x10) | \
-			NETARM_GEN_PORT_DIR(0x10))
-	str	r1, [r0, #+NETARM_GEN_PORTC]
-	/*
-	 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
-	 *		    for an explanation of this process
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
-	/*
-	 * setup PLL and System Config
-	 */
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-
-	ldr	r1, =(	NETARM_GEN_SYS_CFG_LENDIAN | \
-			NETARM_GEN_SYS_CFG_BUSFULL | \
-			NETARM_GEN_SYS_CFG_USER_EN | \
-			NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
-			NETARM_GEN_SYS_CFG_BUSARB_INT | \
-			NETARM_GEN_SYS_CFG_BUSMON_EN )
-
-	str	r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
-
-#ifndef CONFIG_NETARM_PLL_BYPASS
-	ldr	r1, =(	NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
-			NETARM_GEN_PLL_CTL_POLTST_DEF | \
-			NETARM_GEN_PLL_CTL_INDIV(1) | \
-			NETARM_GEN_PLL_CTL_ICP_DEF | \
-			NETARM_GEN_PLL_CTL_OUTDIV(2) )
-	str	r1, [r0, #+NETARM_GEN_PLL_CONTROL]
-#endif
-
-	/*
-	 * mask all IRQs by clearing all bits in the INTMRs
-	 */
-	mov	r1, #0
-	ldr	r0, =NETARM_GEN_MODULE_BASE
-	str	r1, [r0, #+NETARM_GEN_INTR_ENABLE]
-
-#elif defined(CONFIG_S3C4510B)
 
-	/*
-	 * Mask off all IRQ sources
-	 */
-	ldr	r1, =REG_INTMASK
-	ldr	r0, =0x3FFFFF
-	str	r0, [r1]
-
-	/*
-	 * Disable Cache
-	 */
-	ldr r0, =REG_SYSCFG
-	ldr r1, =0x83ffffa0	/* cache-disabled  */
-	str r1, [r0]
-
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific initialisation for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	/* Set-up PLL */
-	mov	r3, #0xAA
-	mov	r4, #0x55
-	/* First disconnect and disable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x00
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set new M and P values */
-	ldr	r0, PLLCFG_ADR
-	mov	r1, #0x23	/* M=4 and P=2 */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Then enable the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x01	/* PLL enable bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Wait for the lock */
-	ldr	r0, PLLSTAT_ADR
-	mov	r1, #0x400	/* lock bit */
-lock_loop:
-	ldr	r2, [r0]
-	and	r2, r1, r2
-	cmp	r2, #0
-	beq	lock_loop
-	/* And finally connect the PLL */
-	ldr	r0, PLLCON_ADR
-	mov	r1, #0x03	/* PLL enable bit and connect bit */
-	str	r1, [r0]
-	ldr	r0, PLLFEED_ADR /* start feed sequence */
-	str	r3, [r0]
-	str	r4, [r0]	/* feed sequence done */
-	/* Set-up VPBDIV register */
-	ldr	r0, VPBDIV_ADR
-	mov	r1, #0x01	/* VPB clock is same as process clock */
-	str	r1, [r0]
-#elif defined(CONFIG_TEGRA)
-	/* No cpu_init_crit for tegra as yet */
-#else
-#error No cpu_init_crit() defined for current CPU type
-#endif
-
-#ifdef CONFIG_ARM7_REVD
-	/* set clock speed */
-	/* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
-	/* !!! not doing DRAM refresh properly! */
-	ldr	r0, SYSCON3
-	ldr	r1, [r0]
-	bic	r1, r1, #CLKCTL
-	orr	r1, r1, #CLKCTL_36
-	str	r1, [r0]
-#endif
-
-#if !defined(CONFIG_LPC2292) && !defined(CONFIG_TEGRA)
+#if !defined(CONFIG_TEGRA)
 	mov	ip, lr
 	/*
 	 * before relocating, we have to setup RAM timing
@@ -610,39 +463,3 @@ fiq:
 
 #endif
 #endif /* CONFIG_SPL_BUILD */
-
-#if defined(CONFIG_NETARM)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =NETARM_MEM_MODULE_BASE
-	ldr	r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
-	ldr	r1, =0xFFFFF000
-	and	r0, r1, r0
-	ldr	r1, =(relocate-CONFIG_SYS_TEXT_BASE)
-	add	r0, r1, r0
-	ldr	r4, =NETARM_GEN_MODULE_BASE
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETA
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	ldr	r1, =NETARM_GEN_SW_SVC_RESETB
-	str	r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
-	mov	pc, r0
-#elif defined(CONFIG_S3C4510B)
-/* Nothing done here as reseting the CPU is board specific, depending
- * on external peripherals such as watchdog timers, etc. */
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-	/* No specific reset actions for IntegratorAP/CM720T as yet */
-#elif defined(CONFIG_LPC2292)
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	mov	pc, r0
-#elif defined(CONFIG_TEGRA)
-	/* No specific reset actions for tegra as yet */
-#else
-#error No reset_cpu() defined for current CPU type
-#endif
diff --git a/arch/arm/cpu/arm720t/tegra-common/spl.c b/arch/arm/cpu/arm720t/tegra-common/spl.c
index 0d37ce8..c280ab7 100644
--- a/arch/arm/cpu/arm720t/tegra-common/spl.c
+++ b/arch/arm/cpu/arm720t/tegra-common/spl.c
@@ -23,105 +23,42 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <asm/u-boot.h>
-#include <asm/utils.h>
-#include <nand.h>
-#include <mmc.h>
-#include <fat.h>
-#include <version.h>
-#include <i2c.h>
-#include <image.h>
-#include <malloc.h>
-#include <linux/compiler.h>
 #include "cpu.h"
+#include <spl.h>
 
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/board.h>
-#include <asm/arch-tegra/clk_rst.h>
-#include <asm/arch-tegra/pmc.h>
-#include <asm/arch-tegra/scu.h>
-#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch/spl.h>
 
-DECLARE_GLOBAL_DATA_PTR;
 
-/* Define global data structure pointer to it*/
-static gd_t gdata __attribute__ ((section(".data")));
-static bd_t bdata __attribute__ ((section(".data")));
-
-inline void hang(void)
+void spl_board_init(void)
 {
-	puts("### ERROR ### Please RESET the board ###\n");
-	for (;;)
-		;
-}
+	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+
+	/* enable JTAG */
+	writel(0xC0, &pmt->pmt_cfg_ctl);
 
-void board_init_f(ulong dummy)
-{
 	board_init_uart_f();
 
 	/* Initialize periph GPIOs */
 	gpio_early_init_uart();
 
-	/*
-	 * We call relocate_code() with relocation target same as the
-	 * CONFIG_SYS_SPL_TEXT_BASE. This will result in relocation getting
-	 * skipped. Instead, only .bss initialization will happen. That's
-	 * all we need
-	 */
-	debug(">>board_init_f()\n");
-	relocate_code(CONFIG_SPL_STACK, &gdata, CONFIG_SPL_TEXT_BASE);
+	clock_early_init();
+	preloader_console_init();
 }
 
-/* This requires UART clocks to be enabled */
-static void preloader_console_init(void)
+u32 spl_boot_device(void)
 {
-	const char *u_boot_rev = U_BOOT_VERSION;
-
-	gd = &gdata;
-	gd->bd = &bdata;
-	gd->flags |= GD_FLG_RELOC;
-	gd->baudrate = CONFIG_BAUDRATE;
-
-	serial_init();		/* serial communications setup */
-
-	gd->have_console = 1;
-
-	/* Avoid a second "U-Boot" coming from this string */
-	u_boot_rev = &u_boot_rev[7];
-
-	printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE,
-		U_BOOT_TIME);
+	return BOOT_DEVICE_RAM;
 }
 
-void board_init_r(gd_t *id, ulong dummy)
+void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 {
-	struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-
-	/* enable JTAG */
-	writel(0xC0, &pmt->pmt_cfg_ctl);
-
-	debug(">>spl:board_init_r()\n");
-
-	mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
-			CONFIG_SYS_SPL_MALLOC_SIZE);
-
-#ifdef CONFIG_SPL_BOARD_INIT
-	spl_board_init();
-#endif
+	debug("image entry point: 0x%X\n", spl_image->entry_point);
 
-	clock_early_init();
-	serial_init();
-	preloader_console_init();
-
-	start_cpu((u32)CONFIG_SYS_TEXT_BASE);
+	start_cpu((u32)spl_image->entry_point);
 	halt_avp();
-	/* not reached */
-}
-
-int board_usb_init(const void *blob)
-{
-	return 0;
 }
diff --git a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
index dc6ba34..008ae89 100644
--- a/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
+++ b/arch/arm/cpu/arm920t/ep93xx/u-boot.lds
@@ -48,9 +48,11 @@ SECTIONS
 	.got : { *(.got) }
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 	__bss_start = .;
diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
index e9f1227..1bba571 100644
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
@@ -72,10 +72,10 @@ lowlevel_init:
 	 * enable UART for early debug trace
 	 */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR)
-	mov	r2, #0xd9
-	str	r2, [r1]		/* 115200 baud */
+	mov	r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE)
+	str	r2, [r1]
 	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL)
-	mov	r2, #0x03
+	mov	r2, #KS8695_UART_LINEC_WLEN8
 	str	r2, [r1]		/* 8 data bits, no parity, 1 stop */
 	ldr	r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING)
 	mov	r2, #0x41
diff --git a/arch/arm/cpu/arm920t/s3c24x0/Makefile b/arch/arm/cpu/arm920t/s3c24x0/Makefile
index 0029700..808ab8f 100644
--- a/arch/arm/cpu/arm920t/s3c24x0/Makefile
+++ b/arch/arm/cpu/arm920t/s3c24x0/Makefile
@@ -29,9 +29,6 @@ COBJS-$(CONFIG_USE_IRQ) += interrupts.o
 COBJS-$(CONFIG_DISPLAY_CPUINFO)	+= cpu_info.o
 COBJS-y	+= speed.o
 COBJS-y	+= timer.o
-COBJS-y	+= usb.o
-COBJS-y	+= usb_ohci.o
-
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb.c b/arch/arm/cpu/arm920t/s3c24x0/usb.c
deleted file mode 100644
index 226a3f6..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && \
-    defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-    defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-
-int usb_cpu_init(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-	/*
-	 * Set the 48 MHz UPLL clocking. Values are taken from
-	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-	 */
-	writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
-	/* 1 = use pads related USB for USB host */
-	writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
-
-	/*
-	 * Enable USB host clock.
-	 */
-	writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
-
-	return 0;
-}
-
-int usb_cpu_stop(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	/* may not want to do this */
-	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-	return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI_NEW) && \
-	   defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
-	   defined(CONFIG_S3C24X0) */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
deleted file mode 100644
index 944bb32..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.c
+++ /dev/null
@@ -1,1757 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB on the S3C2400.
- *
- * (C) Copyright 2003
- * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
- *
- * Note: Much of this code has been derived from Linux 2.4
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2002 David Brownell
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-/*
- * IMPORTANT NOTES
- * 1 - this driver is intended for use with USB Mass Storage Devices
- *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
- */
-
-#include <common.h>
-/* #include <pci.h> no PCI on the S3C24X0 */
-
-#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <usb.h>
-#include "usb_ohci.h"
-
-#define OHCI_USE_NPS		/* force NoPowerSwitching mode */
-#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
-
-
-/* For initializing controller (mask in an HCFS mode too) */
-#define	OHCI_CONTROL_INIT \
-	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-
-#define min_t(type, x, y) \
-	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
-
-#undef DEBUG
-#ifdef DEBUG
-#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
-#else
-#define dbg(format, arg...) do {} while(0)
-#endif /* DEBUG */
-#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
-#undef SHOW_INFO
-#ifdef SHOW_INFO
-#define info(format, arg...) printf("INFO: " format "\n", ## arg)
-#else
-#define info(format, arg...) do {} while(0)
-#endif
-
-#define m16_swap(x) swap_16(x)
-#define m32_swap(x) swap_32(x)
-
-/* global struct ohci */
-static struct ohci gohci;
-/* this must be aligned to a 256 byte boundary */
-struct ohci_hcca ghcca[1];
-/* a pointer to the aligned storage */
-struct ohci_hcca *phcca;
-/* this allocates EDs for all possible endpoints */
-struct ohci_device ohci_dev;
-/* urb_priv */
-struct urb_priv urb_priv;
-/* RHSC flag */
-int got_rhsc;
-/* device which was disconnected */
-struct usb_device *devgone;
-/* flag guarding URB transation */
-int urb_finished = 0;
-
-/*-------------------------------------------------------------------------*/
-
-/* AMD-756 (D2 rev) reports corrupt register contents in some cases.
- * The erratum (#4) description is incorrect.  AMD's workaround waits
- * till some bits (mostly reserved) are clear; ok for all revs.
- */
-#define OHCI_QUIRK_AMD756 0xabcd
-#define read_roothub(hc, register, mask) ({ \
-	u32 temp = readl (&hc->regs->roothub.register); \
-	if (hc->flags & OHCI_QUIRK_AMD756) \
-		while (temp & mask) \
-			temp = readl (&hc->regs->roothub.register); \
-	temp; })
-
-static u32 roothub_a(struct ohci *hc)
-{
-	return read_roothub(hc, a, 0xfc0fe000);
-}
-static inline u32 roothub_b(struct ohci *hc)
-{
-	return readl(&hc->regs->roothub.b);
-}
-static inline u32 roothub_status(struct ohci *hc)
-{
-	return readl(&hc->regs->roothub.status);
-}
-static u32 roothub_portstatus(struct ohci *hc, int i)
-{
-	return read_roothub(hc, portstatus[i], 0xffe0fce0);
-}
-
-/* forward declaration */
-static int hc_interrupt(void);
-static void td_submit_job(struct usb_device *dev, unsigned long pipe,
-			  void *buffer, int transfer_len,
-			  struct devrequest *setup, struct urb_priv *urb,
-			  int interval);
-
-/*-------------------------------------------------------------------------*
- * URB support functions
- *-------------------------------------------------------------------------*/
-
-/* free HCD-private data associated with this URB */
-
-static void urb_free_priv(struct urb_priv *urb)
-{
-	int i;
-	int last;
-	struct td *td;
-
-	last = urb->length - 1;
-	if (last >= 0) {
-		for (i = 0; i <= last; i++) {
-			td = urb->td[i];
-			if (td) {
-				td->usb_dev = NULL;
-				urb->td[i] = NULL;
-			}
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-static int sohci_get_current_frame_number(struct usb_device *dev);
-
-/* debug| print the main components of an URB
- * small: 0) header + data packets 1) just header */
-
-static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
-		      int transfer_len, struct devrequest *setup, char *str,
-		      int small)
-{
-	struct urb_priv *purb = &urb_priv;
-
-	dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
-	    str,
-	    sohci_get_current_frame_number(dev),
-	    usb_pipedevice(pipe),
-	    usb_pipeendpoint(pipe),
-	    usb_pipeout(pipe) ? 'O' : 'I',
-	    usb_pipetype(pipe) < 2 ?
-		(usb_pipeint(pipe) ? "INTR" : "ISOC") :
-		(usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
-	    purb->actual_length, transfer_len, dev->status);
-#ifdef	OHCI_VERBOSE_DEBUG
-	if (!small) {
-		int i, len;
-
-		if (usb_pipecontrol(pipe)) {
-			printf(__FILE__ ": cmd(8):");
-			for (i = 0; i < 8; i++)
-				printf(" %02x", ((__u8 *) setup)[i]);
-			printf("\n");
-		}
-		if (transfer_len > 0 && buffer) {
-			printf(__FILE__ ": data(%d/%d):",
-			       purb->actual_length, transfer_len);
-			len = usb_pipeout(pipe) ?
-			    transfer_len : purb->actual_length;
-			for (i = 0; i < 16 && i < len; i++)
-				printf(" %02x", ((__u8 *) buffer)[i]);
-			printf("%s\n", i < len ? "..." : "");
-		}
-	}
-#endif
-}
-
-/* just for debugging; prints non-empty branches of the
-   int ed tree inclusive iso eds*/
-void ep_print_int_eds(struct ohci *ohci, char *str)
-{
-	int i, j;
-	__u32 *ed_p;
-	for (i = 0; i < 32; i++) {
-		j = 5;
-		ed_p = &(ohci->hcca->int_table[i]);
-		if (*ed_p == 0)
-			continue;
-		printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
-		while (*ed_p != 0 && j--) {
-			struct ed *ed = (struct ed *) m32_swap(ed_p);
-			printf(" ed: %4x;", ed->hwINFO);
-			ed_p = &ed->hwNextED;
-		}
-		printf("\n");
-	}
-}
-
-static void ohci_dump_intr_mask(char *label, __u32 mask)
-{
-	dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
-	    label,
-	    mask,
-	    (mask & OHCI_INTR_MIE) ? " MIE" : "",
-	    (mask & OHCI_INTR_OC) ? " OC" : "",
-	    (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
-	    (mask & OHCI_INTR_FNO) ? " FNO" : "",
-	    (mask & OHCI_INTR_UE) ? " UE" : "",
-	    (mask & OHCI_INTR_RD) ? " RD" : "",
-	    (mask & OHCI_INTR_SF) ? " SF" : "",
-	    (mask & OHCI_INTR_WDH) ? " WDH" : "",
-	    (mask & OHCI_INTR_SO) ? " SO" : "");
-}
-
-static void maybe_print_eds(char *label, __u32 value)
-{
-	struct ed *edp = (struct ed *) value;
-
-	if (value) {
-		dbg("%s %08x", label, value);
-		dbg("%08x", edp->hwINFO);
-		dbg("%08x", edp->hwTailP);
-		dbg("%08x", edp->hwHeadP);
-		dbg("%08x", edp->hwNextED);
-	}
-}
-
-static char *hcfs2string(int state)
-{
-	switch (state) {
-	case OHCI_USB_RESET:
-		return "reset";
-	case OHCI_USB_RESUME:
-		return "resume";
-	case OHCI_USB_OPER:
-		return "operational";
-	case OHCI_USB_SUSPEND:
-		return "suspend";
-	}
-	return "?";
-}
-
-/* dump control and status registers */
-static void ohci_dump_status(struct ohci *controller)
-{
-	struct ohci_regs *regs = controller->regs;
-	__u32 temp;
-
-	temp = readl(&regs->revision) & 0xff;
-	if (temp != 0x10)
-		dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
-	temp = readl(&regs->control);
-	dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
-	    (temp & OHCI_CTRL_RWE) ? " RWE" : "",
-	    (temp & OHCI_CTRL_RWC) ? " RWC" : "",
-	    (temp & OHCI_CTRL_IR) ? " IR" : "",
-	    hcfs2string(temp & OHCI_CTRL_HCFS),
-	    (temp & OHCI_CTRL_BLE) ? " BLE" : "",
-	    (temp & OHCI_CTRL_CLE) ? " CLE" : "",
-	    (temp & OHCI_CTRL_IE) ? " IE" : "",
-	    (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
-
-	temp = readl(&regs->cmdstatus);
-	dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
-	    (temp & OHCI_SOC) >> 16,
-	    (temp & OHCI_OCR) ? " OCR" : "",
-	    (temp & OHCI_BLF) ? " BLF" : "",
-	    (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
-
-	ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
-	ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
-
-	maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
-
-	maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
-	maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
-
-	maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
-	maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
-
-	maybe_print_eds("donehead", readl(&regs->donehead));
-}
-
-static void ohci_dump_roothub(struct ohci *controller, int verbose)
-{
-	__u32 temp, ndp, i;
-
-	temp = roothub_a(controller);
-	ndp = (temp & RH_A_NDP);
-
-	if (verbose) {
-		dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
-		    ((temp & RH_A_POTPGT) >> 24) & 0xff,
-		    (temp & RH_A_NOCP) ? " NOCP" : "",
-		    (temp & RH_A_OCPM) ? " OCPM" : "",
-		    (temp & RH_A_DT) ? " DT" : "",
-		    (temp & RH_A_NPS) ? " NPS" : "",
-		    (temp & RH_A_PSM) ? " PSM" : "", ndp);
-		temp = roothub_b(controller);
-		dbg("roothub.b: %08x PPCM=%04x DR=%04x",
-		    temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
-		    );
-		temp = roothub_status(controller);
-		dbg("roothub.status: %08x%s%s%s%s%s%s",
-		    temp,
-		    (temp & RH_HS_CRWE) ? " CRWE" : "",
-		    (temp & RH_HS_OCIC) ? " OCIC" : "",
-		    (temp & RH_HS_LPSC) ? " LPSC" : "",
-		    (temp & RH_HS_DRWE) ? " DRWE" : "",
-		    (temp & RH_HS_OCI) ? " OCI" : "",
-		    (temp & RH_HS_LPS) ? " LPS" : "");
-	}
-
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus(controller, i);
-		dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
-		    i,
-		    temp,
-		    (temp & RH_PS_PRSC) ? " PRSC" : "",
-		    (temp & RH_PS_OCIC) ? " OCIC" : "",
-		    (temp & RH_PS_PSSC) ? " PSSC" : "",
-		    (temp & RH_PS_PESC) ? " PESC" : "",
-		    (temp & RH_PS_CSC) ? " CSC" : "",
-		    (temp & RH_PS_LSDA) ? " LSDA" : "",
-		    (temp & RH_PS_PPS) ? " PPS" : "",
-		    (temp & RH_PS_PRS) ? " PRS" : "",
-		    (temp & RH_PS_POCI) ? " POCI" : "",
-		    (temp & RH_PS_PSS) ? " PSS" : "",
-		    (temp & RH_PS_PES) ? " PES" : "",
-		    (temp & RH_PS_CCS) ? " CCS" : "");
-	}
-}
-
-static void ohci_dump(struct ohci *controller, int verbose)
-{
-	dbg("OHCI controller usb-%s state", controller->slot_name);
-
-	/* dumps some of the state we know about */
-	ohci_dump_status(controller);
-	if (verbose)
-		ep_print_int_eds(controller, "hcca");
-	dbg("hcca frame #%04x", controller->hcca->frame_no);
-	ohci_dump_roothub(controller, 1);
-}
-
-#endif /* DEBUG */
-
-/*-------------------------------------------------------------------------*
- * Interface functions (URB)
- *-------------------------------------------------------------------------*/
-
-/* get a transfer request */
-
-int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
-		     int transfer_len, struct devrequest *setup, int interval)
-{
-	struct ohci *ohci;
-	struct ed *ed;
-	struct urb_priv *purb_priv;
-	int i, size = 0;
-
-	ohci = &gohci;
-
-	/* when controller's hung, permit only roothub cleanup attempts
-	 * such as powering down ports */
-	if (ohci->disabled) {
-		err("sohci_submit_job: EPIPE");
-		return -1;
-	}
-
-	/* if we have an unfinished URB from previous transaction let's
-	 * fail and scream as quickly as possible so as not to corrupt
-	 * further communication */
-	if (!urb_finished) {
-		err("sohci_submit_job: URB NOT FINISHED");
-		return -1;
-	}
-	/* we're about to begin a new transaction here
-	   so mark the URB unfinished */
-	urb_finished = 0;
-
-	/* every endpoint has a ed, locate and fill it */
-	ed = ep_add_ed(dev, pipe);
-	if (!ed) {
-		err("sohci_submit_job: ENOMEM");
-		return -1;
-	}
-
-	/* for the private part of the URB we need the number of TDs (size) */
-	switch (usb_pipetype(pipe)) {
-	case PIPE_BULK:
-		/* one TD for every 4096 Byte */
-		size = (transfer_len - 1) / 4096 + 1;
-		break;
-	case PIPE_CONTROL:
-		/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
-		size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
-		break;
-	}
-
-	if (size >= (N_URB_TD - 1)) {
-		err("need %d TDs, only have %d", size, N_URB_TD);
-		return -1;
-	}
-	purb_priv = &urb_priv;
-	purb_priv->pipe = pipe;
-
-	/* fill the private part of the URB */
-	purb_priv->length = size;
-	purb_priv->ed = ed;
-	purb_priv->actual_length = 0;
-
-	/* allocate the TDs */
-	/* note that td[0] was allocated in ep_add_ed */
-	for (i = 0; i < size; i++) {
-		purb_priv->td[i] = td_alloc(dev);
-		if (!purb_priv->td[i]) {
-			purb_priv->length = i;
-			urb_free_priv(purb_priv);
-			err("sohci_submit_job: ENOMEM");
-			return -1;
-		}
-	}
-
-	if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
-		urb_free_priv(purb_priv);
-		err("sohci_submit_job: EINVAL");
-		return -1;
-	}
-
-	/* link the ed into a chain if is not already */
-	if (ed->state != ED_OPER)
-		ep_link(ohci, ed);
-
-	/* fill the TDs and link it to the ed */
-	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
-		      interval);
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef DEBUG
-/* tell us the current USB frame number */
-
-static int sohci_get_current_frame_number(struct usb_device *usb_dev)
-{
-	struct ohci *ohci = &gohci;
-
-	return m16_swap(ohci->hcca->frame_no);
-}
-#endif
-
-/*-------------------------------------------------------------------------*
- * ED handling functions
- *-------------------------------------------------------------------------*/
-
-/* link an ed into one of the HC chains */
-
-static int ep_link(struct ohci *ohci, struct ed *edi)
-{
-	struct ed *ed = edi;
-
-	ed->state = ED_OPER;
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		ed->hwNextED = 0;
-		if (ohci->ed_controltail == NULL) {
-			writel((u32)ed, &ohci->regs->ed_controlhead);
-		} else {
-			ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
-		}
-		ed->ed_prev = ohci->ed_controltail;
-		if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
-		    !ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_CLE;
-			writel(ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_controltail = edi;
-		break;
-
-	case PIPE_BULK:
-		ed->hwNextED = 0;
-		if (ohci->ed_bulktail == NULL) {
-			writel((u32)ed, &ohci->regs->ed_bulkhead);
-		} else {
-			ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
-		}
-		ed->ed_prev = ohci->ed_bulktail;
-		if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
-		    !ohci->ed_rm_list[1] && !ohci->sleeping) {
-			ohci->hc_control |= OHCI_CTRL_BLE;
-			writel(ohci->hc_control, &ohci->regs->control);
-		}
-		ohci->ed_bulktail = edi;
-		break;
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* unlink an ed from one of the HC chains.
- * just the link to the ed is unlinked.
- * the link from the ed still points to another operational ed or 0
- * so the HC can eventually finish the processing of the unlinked ed */
-
-static int ep_unlink(struct ohci *ohci, struct ed *ed)
-{
-	struct ed *next;
-	ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
-
-	switch (ed->type) {
-	case PIPE_CONTROL:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_CLE;
-				writel(ohci->hc_control, &ohci->regs->control);
-			}
-			writel(m32_swap(*((__u32 *) &ed->hwNextED)),
-			       &ohci->regs->ed_controlhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_controltail == ed) {
-			ohci->ed_controltail = ed->ed_prev;
-		} else {
-			next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
-			next->ed_prev = ed->ed_prev;
-		}
-		break;
-
-	case PIPE_BULK:
-		if (ed->ed_prev == NULL) {
-			if (!ed->hwNextED) {
-				ohci->hc_control &= ~OHCI_CTRL_BLE;
-				writel(ohci->hc_control, &ohci->regs->control);
-			}
-			writel(m32_swap(*((__u32 *) &ed->hwNextED)),
-			       &ohci->regs->ed_bulkhead);
-		} else {
-			ed->ed_prev->hwNextED = ed->hwNextED;
-		}
-		if (ohci->ed_bulktail == ed) {
-			ohci->ed_bulktail = ed->ed_prev;
-		} else {
-			next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
-			next->ed_prev = ed->ed_prev;
-		}
-		break;
-	}
-	ed->state = ED_UNLINK;
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration
- * command, but the USB stack is a little bit stateless  so we do it at every
- * transaction. If the state of the ed is ED_NEW then a dummy td is added and
- * the state is changed to ED_UNLINK. In all other cases the state is left
- * unchanged. The ed info fields are setted anyway even though most of them
- * should not change */
-
-static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
-{
-	struct td *td;
-	struct ed *ed_ret;
-	struct ed *ed;
-
-	ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
-				   (usb_pipecontrol(pipe) ? 0 :
-				    usb_pipeout(pipe))];
-
-	if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
-		err("ep_add_ed: pending delete");
-		/* pending delete request */
-		return NULL;
-	}
-
-	if (ed->state == ED_NEW) {
-		ed->hwINFO = m32_swap(OHCI_ED_SKIP);	/* skip ed */
-		/* dummy td; end of td list for ed */
-		td = td_alloc(usb_dev);
-		ed->hwTailP = (__u32) m32_swap(td);
-		ed->hwHeadP = ed->hwTailP;
-		ed->state = ED_UNLINK;
-		ed->type = usb_pipetype(pipe);
-		ohci_dev.ed_cnt++;
-	}
-
-	ed->hwINFO = m32_swap(usb_pipedevice(pipe)
-			      | usb_pipeendpoint(pipe) << 7
-			      | (usb_pipeisoc(pipe) ? 0x8000 : 0)
-			      | (usb_pipecontrol(pipe) ? 0 :
-				 (usb_pipeout(pipe) ? 0x800 : 0x1000))
-			      | usb_pipeslow(pipe) << 13 |
-			      usb_maxpacket(usb_dev, pipe) << 16);
-
-	return ed_ret;
-}
-
-/*-------------------------------------------------------------------------*
- * TD handling functions
- *-------------------------------------------------------------------------*/
-
-/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-
-static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
-		    struct usb_device *dev, int index,
-		    struct urb_priv *urb_priv)
-{
-	struct td *td, *td_pt;
-#ifdef OHCI_FILL_TRACE
-	int i;
-#endif
-
-	if (index > urb_priv->length) {
-		err("index > length");
-		return;
-	}
-	/* use this td as the next dummy */
-	td_pt = urb_priv->td[index];
-	td_pt->hwNextTD = 0;
-
-	/* fill the old dummy TD */
-	td = urb_priv->td[index] =
-	    (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
-
-	td->ed = urb_priv->ed;
-	td->next_dl_td = NULL;
-	td->index = index;
-	td->data = (__u32) data;
-#ifdef OHCI_FILL_TRACE
-	if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
-		for (i = 0; i < len; i++)
-			printf("td->data[%d] %#2x ", i,
-			       ((unsigned char *)td->data)[i]);
-		printf("\n");
-	}
-#endif
-	if (!len)
-		data = 0;
-
-	td->hwINFO = (__u32) m32_swap(info);
-	td->hwCBP = (__u32) m32_swap(data);
-	if (data)
-		td->hwBE = (__u32) m32_swap(data + len - 1);
-	else
-		td->hwBE = 0;
-	td->hwNextTD = (__u32) m32_swap(td_pt);
-
-	/* append to queue */
-	td->ed->hwTailP = td->hwNextTD;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* prepare all TDs of a transfer */
-
-static void td_submit_job(struct usb_device *dev, unsigned long pipe,
-			  void *buffer, int transfer_len,
-			  struct devrequest *setup, struct urb_priv *urb,
-			  int interval)
-{
-	struct ohci *ohci = &gohci;
-	int data_len = transfer_len;
-	void *data;
-	int cnt = 0;
-	__u32 info = 0;
-	unsigned int toggle = 0;
-
-	/* OHCI handles the DATA-toggles itself, we just
-	   use the USB-toggle bits for reseting */
-	if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
-		toggle = TD_T_TOGGLE;
-	} else {
-		toggle = TD_T_DATA0;
-		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
-			      1);
-	}
-	urb->td_cnt = 0;
-	if (data_len)
-		data = buffer;
-	else
-		data = 0;
-
-	switch (usb_pipetype(pipe)) {
-	case PIPE_BULK:
-		info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
-		while (data_len > 4096) {
-			td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
-				4096, dev, cnt, urb);
-			data += 4096;
-			data_len -= 4096;
-			cnt++;
-		}
-		info = usb_pipeout(pipe) ?
-				TD_CC | TD_DP_OUT :
-				TD_CC | TD_R | TD_DP_IN;
-		td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
-			data_len, dev, cnt, urb);
-		cnt++;
-
-		if (!ohci->sleeping)
-			/* start bulk list */
-			writel(OHCI_BLF, &ohci->regs->cmdstatus);
-		break;
-
-	case PIPE_CONTROL:
-		info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
-		td_fill(ohci, info, setup, 8, dev, cnt++, urb);
-		if (data_len > 0) {
-			info = usb_pipeout(pipe) ?
-			    TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
-			    TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
-			/* NOTE:  mishandles transfers >8K, some >4K */
-			td_fill(ohci, info, data, data_len, dev, cnt++, urb);
-		}
-		info = usb_pipeout(pipe) ?
-		    TD_CC | TD_DP_IN | TD_T_DATA1 :
-		    TD_CC | TD_DP_OUT | TD_T_DATA1;
-		td_fill(ohci, info, data, 0, dev, cnt++, urb);
-		if (!ohci->sleeping)
-			/* start Control list */
-			writel(OHCI_CLF, &ohci->regs->cmdstatus);
-		break;
-	}
-	if (urb->length != cnt)
-		dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
-}
-
-/*-------------------------------------------------------------------------*
- * Done List handling functions
- *-------------------------------------------------------------------------*/
-
-
-/* calculate the transfer length and update the urb */
-
-static void dl_transfer_length(struct td *td)
-{
-	__u32 tdBE, tdCBP;
-	struct urb_priv *lurb_priv = &urb_priv;
-
-	tdBE = m32_swap(td->hwBE);
-	tdCBP = m32_swap(td->hwCBP);
-
-	if (!(usb_pipecontrol(lurb_priv->pipe) &&
-	      ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
-		if (tdBE != 0) {
-			if (td->hwCBP == 0)
-				lurb_priv->actual_length += tdBE - td->data + 1;
-			else
-				lurb_priv->actual_length += tdCBP - td->data;
-		}
-	}
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* replies to the request have to be on a FIFO basis so
- * we reverse the reversed done-list */
-
-static struct td *dl_reverse_done_list(struct ohci *ohci)
-{
-	__u32 td_list_hc;
-	__u32 tmp;
-	struct td *td_rev = NULL;
-	struct td *td_list = NULL;
-	struct urb_priv *lurb_priv = NULL;
-
-	td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
-	ohci->hcca->done_head = 0;
-
-	while (td_list_hc) {
-		td_list = (struct td *) td_list_hc;
-
-		if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
-			lurb_priv = &urb_priv;
-			dbg(" USB-error/status: %x : %p",
-			    TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
-			if (td_list->ed->hwHeadP & m32_swap(0x1)) {
-				if (lurb_priv &&
-				    ((td_list->index+1) < lurb_priv->length)) {
-					tmp = lurb_priv->length - 1;
-					td_list->ed->hwHeadP =
-						(lurb_priv->td[tmp]->hwNextTD &
-						 m32_swap(0xfffffff0)) |
-						 (td_list->ed->hwHeadP &
-						  m32_swap(0x2));
-					lurb_priv->td_cnt += lurb_priv->length -
-							     td_list->index - 1;
-				} else
-					td_list->ed->hwHeadP &=
-					    m32_swap(0xfffffff2);
-			}
-		}
-
-		td_list->next_dl_td = td_rev;
-		td_rev = td_list;
-		td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
-	}
-
-	return td_list;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* td done list */
-static int dl_done_list(struct ohci *ohci, struct td *td_list)
-{
-	struct td *td_list_next = NULL;
-	struct ed *ed;
-	int cc = 0;
-	int stat = 0;
-	/* urb_t *urb; */
-	struct urb_priv *lurb_priv;
-	__u32 tdINFO, edHeadP, edTailP;
-
-	while (td_list) {
-		td_list_next = td_list->next_dl_td;
-
-		lurb_priv = &urb_priv;
-		tdINFO = m32_swap(td_list->hwINFO);
-
-		ed = td_list->ed;
-
-		dl_transfer_length(td_list);
-
-		/* error code of transfer */
-		cc = TD_CC_GET(tdINFO);
-		if (cc != 0) {
-			dbg("ConditionCode %#x", cc);
-			stat = cc_to_error[cc];
-		}
-
-		/* see if this done list makes for all TD's of current URB,
-		 * and mark the URB finished if so */
-		if (++(lurb_priv->td_cnt) == lurb_priv->length) {
-			if ((ed->state & (ED_OPER | ED_UNLINK)))
-				urb_finished = 1;
-			else
-				dbg("dl_done_list: strange.., ED state %x, "
-				    "ed->state\n");
-		} else
-			dbg("dl_done_list: processing TD %x, len %x\n",
-			    lurb_priv->td_cnt, lurb_priv->length);
-
-		if (ed->state != ED_NEW) {
-			edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
-			edTailP = m32_swap(ed->hwTailP);
-
-			/* unlink eds if they are not busy */
-			if ((edHeadP == edTailP) && (ed->state == ED_OPER))
-				ep_unlink(ohci, ed);
-		}
-
-		td_list = td_list_next;
-	}
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*
- * Virtual Root Hub
- *-------------------------------------------------------------------------*/
-
-/* Device descriptor */
-static __u8 root_hub_dev_des[] = {
-	0x12,	/*  __u8  bLength; */
-	0x01,	/*  __u8  bDescriptorType; Device */
-	0x10,	/*  __u16 bcdUSB; v1.1 */
-	0x01,
-	0x09,	/*  __u8  bDeviceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  bDeviceSubClass; */
-	0x00,	/*  __u8  bDeviceProtocol; */
-	0x08,	/*  __u8  bMaxPacketSize0; 8 Bytes */
-	0x00,	/*  __u16 idVendor; */
-	0x00,
-	0x00,	/*  __u16 idProduct; */
-	0x00,
-	0x00,	/*  __u16 bcdDevice; */
-	0x00,
-	0x00,	/*  __u8  iManufacturer; */
-	0x01,	/*  __u8  iProduct; */
-	0x00,	/*  __u8  iSerialNumber; */
-	0x01	/*  __u8  bNumConfigurations; */
-};
-
-/* Configuration descriptor */
-static __u8 root_hub_config_des[] = {
-	0x09,	/*  __u8  bLength; */
-	0x02,	/*  __u8  bDescriptorType; Configuration */
-	0x19,	/*  __u16 wTotalLength; */
-	0x00,
-	0x01,	/*  __u8  bNumInterfaces; */
-	0x01,	/*  __u8  bConfigurationValue; */
-	0x00,	/*  __u8  iConfiguration; */
-	0x40,	/*  __u8  bmAttributes;
-		   Bit 7: Bus-powered, 6: Self-powered,
-		   5 Remote-wakwup, 4..0: resvd */
-	0x00,	/*  __u8  MaxPower; */
-
-	/* interface */
-	0x09,	/*  __u8  if_bLength; */
-	0x04,	/*  __u8  if_bDescriptorType; Interface */
-	0x00,	/*  __u8  if_bInterfaceNumber; */
-	0x00,	/*  __u8  if_bAlternateSetting; */
-	0x01,	/*  __u8  if_bNumEndpoints; */
-	0x09,	/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
-	0x00,	/*  __u8  if_bInterfaceSubClass; */
-	0x00,	/*  __u8  if_bInterfaceProtocol; */
-	0x00,	/*  __u8  if_iInterface; */
-
-	/* endpoint */
-	0x07,	/*  __u8  ep_bLength; */
-	0x05,	/*  __u8  ep_bDescriptorType; Endpoint */
-	0x81,	/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
-	0x03,	/*  __u8  ep_bmAttributes; Interrupt */
-	0x02,	/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
-	0x00,
-	0xff	/*  __u8  ep_bInterval; 255 ms */
-};
-
-static unsigned char root_hub_str_index0[] = {
-	0x04,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	0x09,	/*  __u8  lang ID */
-	0x04,	/*  __u8  lang ID */
-};
-
-static unsigned char root_hub_str_index1[] = {
-	28,	/*  __u8  bLength; */
-	0x03,	/*  __u8  bDescriptorType; String-descriptor */
-	'O',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'C',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'I',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'R',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'o',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	't',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	' ',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'H',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'u',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-	'b',	/*  __u8  Unicode */
-	0,	/*  __u8  Unicode */
-};
-
-/* Hub class-specific descriptor is constructed dynamically */
-
-
-/*-------------------------------------------------------------------------*/
-
-#define OK(x)			len = (x); break
-#ifdef DEBUG
-#define WR_RH_STAT(x) \
-{ \
-	info("WR:status %#8x", (x)); \
-	writel((x), &gohci.regs->roothub.status); \
-}
-#define WR_RH_PORTSTAT(x) \
-{ \
-	info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
-	writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
-}
-#else
-#define WR_RH_STAT(x) \
-	writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x)\
-	writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
-#endif
-#define RD_RH_STAT	roothub_status(&gohci)
-#define RD_RH_PORTSTAT	roothub_portstatus(&gohci, wIndex-1)
-
-/* request to virtual root hub */
-
-int rh_check_port_status(struct ohci *controller)
-{
-	__u32 temp, ndp, i;
-	int res;
-
-	res = -1;
-	temp = roothub_a(controller);
-	ndp = (temp & RH_A_NDP);
-	for (i = 0; i < ndp; i++) {
-		temp = roothub_portstatus(controller, i);
-		/* check for a device disconnect */
-		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
-		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
-			res = i;
-			break;
-		}
-	}
-	return res;
-}
-
-static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
-			      void *buffer, int transfer_len,
-			      struct devrequest *cmd)
-{
-	void *data = buffer;
-	int leni = transfer_len;
-	int len = 0;
-	int stat = 0;
-	union {
-		__u32 word[4];
-		__u16 hword[8];
-		__u8 byte[16];
-	} datab;
-	__u8 *data_buf = datab.byte;
-	__u16 bmRType_bReq;
-	__u16 wValue;
-	__u16 wIndex;
-	__u16 wLength;
-
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (usb_pipeint(pipe)) {
-		info("Root-Hub submit IRQ: NOT implemented");
-		return 0;
-	}
-
-	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
-	wValue = m16_swap(cmd->value);
-	wIndex = m16_swap(cmd->index);
-	wLength = m16_swap(cmd->length);
-
-	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
-	     dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
-
-	switch (bmRType_bReq) {
-		/* Request Destination:
-		   without flags: Device,
-		   RH_INTERFACE: interface,
-		   RH_ENDPOINT: endpoint,
-		   RH_CLASS means HUB here,
-		   RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
-		 */
-
-	case RH_GET_STATUS:
-		datab.hword[0] = m16_swap(1);
-		OK(2);
-	case RH_GET_STATUS | RH_INTERFACE:
-		datab.hword[0] = m16_swap(0);
-		OK(2);
-	case RH_GET_STATUS | RH_ENDPOINT:
-		datab.hword[0] = m16_swap(0);
-		OK(2);
-	case RH_GET_STATUS | RH_CLASS:
-		datab.word[0] =
-		    m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
-		OK(4);
-	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
-		datab.word[0] = m32_swap(RD_RH_PORTSTAT);
-		OK(4);
-
-	case RH_CLEAR_FEATURE | RH_ENDPOINT:
-		switch (wValue) {
-		case (RH_ENDPOINT_STALL):
-			OK(0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_CLASS:
-		switch (wValue) {
-		case RH_C_HUB_LOCAL_POWER:
-			OK(0);
-		case (RH_C_HUB_OVER_CURRENT):
-			WR_RH_STAT(RH_HS_OCIC);
-			OK(0);
-		}
-		break;
-
-	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-		case (RH_PORT_ENABLE):
-			WR_RH_PORTSTAT(RH_PS_CCS);
-			OK(0);
-		case (RH_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_POCI);
-			OK(0);
-		case (RH_PORT_POWER):
-			WR_RH_PORTSTAT(RH_PS_LSDA);
-			OK(0);
-		case (RH_C_PORT_CONNECTION):
-			WR_RH_PORTSTAT(RH_PS_CSC);
-			OK(0);
-		case (RH_C_PORT_ENABLE):
-			WR_RH_PORTSTAT(RH_PS_PESC);
-			OK(0);
-		case (RH_C_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_PSSC);
-			OK(0);
-		case (RH_C_PORT_OVER_CURRENT):
-			WR_RH_PORTSTAT(RH_PS_OCIC);
-			OK(0);
-		case (RH_C_PORT_RESET):
-			WR_RH_PORTSTAT(RH_PS_PRSC);
-			OK(0);
-		}
-		break;
-
-	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
-		switch (wValue) {
-		case (RH_PORT_SUSPEND):
-			WR_RH_PORTSTAT(RH_PS_PSS);
-			OK(0);
-		case (RH_PORT_RESET):	/* BUG IN HUP CODE ******** */
-			if (RD_RH_PORTSTAT & RH_PS_CCS)
-				WR_RH_PORTSTAT(RH_PS_PRS);
-			OK(0);
-		case (RH_PORT_POWER):
-			WR_RH_PORTSTAT(RH_PS_PPS);
-			OK(0);
-		case (RH_PORT_ENABLE):	/* BUG IN HUP CODE ******** */
-			if (RD_RH_PORTSTAT & RH_PS_CCS)
-				WR_RH_PORTSTAT(RH_PS_PES);
-			OK(0);
-		}
-		break;
-
-	case RH_SET_ADDRESS:
-		gohci.rh.devnum = wValue;
-		OK(0);
-
-	case RH_GET_DESCRIPTOR:
-		switch ((wValue & 0xff00) >> 8) {
-		case (0x01):	/* device descriptor */
-			len = min_t(unsigned int,
-				    leni,
-				    min_t(unsigned int,
-					  sizeof(root_hub_dev_des), wLength));
-			data_buf = root_hub_dev_des;
-			OK(len);
-		case (0x02):	/* configuration descriptor */
-			len = min_t(unsigned int,
-				    leni,
-				    min_t(unsigned int,
-					  sizeof(root_hub_config_des),
-					  wLength));
-			data_buf = root_hub_config_des;
-			OK(len);
-		case (0x03):	/* string descriptors */
-			if (wValue == 0x0300) {
-				len = min_t(unsigned int,
-					    leni,
-					    min_t(unsigned int,
-						  sizeof(root_hub_str_index0),
-						  wLength));
-				data_buf = root_hub_str_index0;
-				OK(len);
-			}
-			if (wValue == 0x0301) {
-				len = min_t(unsigned int,
-					    leni,
-					    min_t(unsigned int,
-						  sizeof(root_hub_str_index1),
-						  wLength));
-				data_buf = root_hub_str_index1;
-				OK(len);
-			}
-		default:
-			stat = USB_ST_STALLED;
-		}
-		break;
-
-	case RH_GET_DESCRIPTOR | RH_CLASS:
-		{
-			__u32 temp = roothub_a(&gohci);
-
-			data_buf[0] = 9;	/* min length; */
-			data_buf[1] = 0x29;
-			data_buf[2] = temp & RH_A_NDP;
-			data_buf[3] = 0;
-			if (temp & RH_A_PSM)
-				/* per-port power switching? */
-				data_buf[3] |= 0x1;
-			if (temp & RH_A_NOCP)
-				/* no overcurrent reporting? */
-				data_buf[3] |= 0x10;
-			else if (temp & RH_A_OCPM)
-				/* per-port overcurrent reporting? */
-				data_buf[3] |= 0x8;
-
-			/* corresponds to data_buf[4-7] */
-			datab.word[1] = 0;
-			data_buf[5] = (temp & RH_A_POTPGT) >> 24;
-			temp = roothub_b(&gohci);
-			data_buf[7] = temp & RH_B_DR;
-			if (data_buf[2] < 7) {
-				data_buf[8] = 0xff;
-			} else {
-				data_buf[0] += 2;
-				data_buf[8] = (temp & RH_B_DR) >> 8;
-				data_buf[10] = data_buf[9] = 0xff;
-			}
-
-			len = min_t(unsigned int, leni,
-				    min_t(unsigned int, data_buf[0], wLength));
-			OK(len);
-		}
-
-	case RH_GET_CONFIGURATION:
-		*(__u8 *) data_buf = 0x01;
-		OK(1);
-
-	case RH_SET_CONFIGURATION:
-		WR_RH_STAT(0x10000);
-		OK(0);
-
-	default:
-		dbg("unsupported root hub command");
-		stat = USB_ST_STALLED;
-	}
-
-#ifdef	DEBUG
-	ohci_dump_roothub(&gohci, 1);
-#else
-	mdelay(1);
-#endif
-
-	len = min_t(int, len, leni);
-	if (data != data_buf)
-		memcpy(data, data_buf, len);
-	dev->act_len = len;
-	dev->status = stat;
-
-#ifdef DEBUG
-	if (transfer_len)
-		urb_priv.actual_length = transfer_len;
-	pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
-		  0 /*usb_pipein(pipe) */);
-#else
-	mdelay(1);
-#endif
-
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* common code for handling submit messages - used for all but root hub */
-/* accesses. */
-int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		      int transfer_len, struct devrequest *setup, int interval)
-{
-	int stat = 0;
-	int maxsize = usb_maxpacket(dev, pipe);
-	int timeout;
-
-	/* device pulled? Shortcut the action. */
-	if (devgone == dev) {
-		dev->status = USB_ST_CRC_ERR;
-		return 0;
-	}
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (!maxsize) {
-		err("submit_common_message: pipesize for pipe %lx is zero",
-		    pipe);
-		return -1;
-	}
-
-	if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
-	    0) {
-		err("sohci_submit_job failed");
-		return -1;
-	}
-
-	mdelay(10);
-	/* ohci_dump_status(&gohci); */
-
-	/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO	 5000		/* timeout in milliseconds */
-	if (usb_pipebulk(pipe))
-		timeout = BULK_TO;
-	else
-		timeout = 100;
-
-	/* wait for it to complete */
-	for (;;) {
-		/* check whether the controller is done */
-		stat = hc_interrupt();
-
-		if (stat < 0) {
-			stat = USB_ST_CRC_ERR;
-			break;
-		}
-
-		/* NOTE: since we are not interrupt driven in U-Boot and always
-		 * handle only one URB at a time, we cannot assume the
-		 * transaction finished on the first successful return from
-		 * hc_interrupt().. unless the flag for current URB is set,
-		 * meaning that all TD's to/from device got actually
-		 * transferred and processed. If the current URB is not
-		 * finished we need to re-iterate this loop so as
-		 * hc_interrupt() gets called again as there needs to be some
-		 * more TD's to process still */
-		if ((stat >= 0) && (stat != 0xff) && (urb_finished)) {
-			/* 0xff is returned for an SF-interrupt */
-			break;
-		}
-
-		if (--timeout) {
-			mdelay(1);
-			if (!urb_finished)
-				dbg("\%");
-
-		} else {
-			err("CTL:TIMEOUT ");
-			dbg("submit_common_msg: TO status %x\n", stat);
-			stat = USB_ST_CRC_ERR;
-			urb_finished = 1;
-			break;
-		}
-	}
-
-#if 0
-	/* we got an Root Hub Status Change interrupt */
-	if (got_rhsc) {
-#ifdef DEBUG
-		ohci_dump_roothub(&gohci, 1);
-#endif
-		got_rhsc = 0;
-		/* abuse timeout */
-		timeout = rh_check_port_status(&gohci);
-		if (timeout >= 0) {
-#if 0			/* this does nothing useful, but leave it here
-			   in case that changes */
-			/* the called routine adds 1 to the passed value */
-			usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
-#endif
-			/*
-			 * XXX
-			 * This is potentially dangerous because it assumes
-			 * that only one device is ever plugged in!
-			 */
-			devgone = dev;
-		}
-	}
-#endif
-
-	dev->status = stat;
-	dev->act_len = transfer_len;
-
-#ifdef DEBUG
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-
-	/* free TDs in urb_priv */
-	urb_free_priv(&urb_priv);
-	return 0;
-}
-
-/* submit routines called from usb.c */
-int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		    int transfer_len)
-{
-	info("submit_bulk_msg");
-	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
-}
-
-int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		       int transfer_len, struct devrequest *setup)
-{
-	int maxsize = usb_maxpacket(dev, pipe);
-
-	info("submit_control_msg");
-#ifdef DEBUG
-	urb_priv.actual_length = 0;
-	pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
-		  usb_pipein(pipe));
-#else
-	mdelay(1);
-#endif
-	if (!maxsize) {
-		err("submit_control_message: pipesize for pipe %lx is zero",
-		    pipe);
-		return -1;
-	}
-	if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
-		gohci.rh.dev = dev;
-		/* root hub - redirect */
-		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
-					  setup);
-	}
-
-	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
-}
-
-int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
-		   int transfer_len, int interval)
-{
-	info("submit_int_msg");
-	return -1;
-}
-
-/*-------------------------------------------------------------------------*
- * HC functions
- *-------------------------------------------------------------------------*/
-
-/* reset the HC and BUS */
-
-static int hc_reset(struct ohci *ohci)
-{
-	int timeout = 30;
-	int smm_timeout = 50;	/* 0,5 sec */
-
-	if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-		/* SMM owns the HC - request ownership */
-		writel(OHCI_OCR, &ohci->regs->cmdstatus);
-		info("USB HC TakeOver from SMM");
-		while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
-			mdelay(10);
-			if (--smm_timeout == 0) {
-				err("USB HC TakeOver failed!");
-				return -1;
-			}
-		}
-	}
-
-	/* Disable HC interrupts */
-	writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
-
-	dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
-	    ohci->slot_name, readl(&ohci->regs->control));
-
-	/* Reset USB (needed by some controllers) */
-	writel(0, &ohci->regs->control);
-
-	/* HC Reset requires max 10 us delay */
-	writel(OHCI_HCR, &ohci->regs->cmdstatus);
-	while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
-		if (--timeout == 0) {
-			err("USB HC reset timed out!");
-			return -1;
-		}
-		udelay(1);
-	}
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* Start an OHCI controller, set the BUS operational
- * enable interrupts
- * connect the virtual root hub */
-
-static int hc_start(struct ohci *ohci)
-{
-	__u32 mask;
-	unsigned int fminterval;
-
-	ohci->disabled = 1;
-
-	/* Tell the controller where the control and bulk lists are
-	 * The lists are empty now. */
-
-	writel(0, &ohci->regs->ed_controlhead);
-	writel(0, &ohci->regs->ed_bulkhead);
-
-	/* a reset clears this */
-	writel((__u32) ohci->hcca, &ohci->regs->hcca);
-
-	fminterval = 0x2edf;
-	writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
-	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
-	writel(fminterval, &ohci->regs->fminterval);
-	writel(0x628, &ohci->regs->lsthresh);
-
-	/* start controller operations */
-	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
-	ohci->disabled = 0;
-	writel(ohci->hc_control, &ohci->regs->control);
-
-	/* disable all interrupts */
-	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
-		OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
-		OHCI_INTR_OC | OHCI_INTR_MIE);
-	writel(mask, &ohci->regs->intrdisable);
-	/* clear all interrupts */
-	mask &= ~OHCI_INTR_MIE;
-	writel(mask, &ohci->regs->intrstatus);
-	/* Choose the interrupts we care about now  - but w/o MIE */
-	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
-	writel(mask, &ohci->regs->intrenable);
-
-#ifdef	OHCI_USE_NPS
-	/* required for AMD-756 and some Mac platforms */
-	writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
-	       &ohci->regs->roothub.a);
-	writel(RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
-
-	/* POTPGT delay is bits 24-31, in 2 ms units. */
-	mdelay((roothub_a(ohci) >> 23) & 0x1fe);
-
-	/* connect the virtual root hub */
-	ohci->rh.devnum = 0;
-
-	return 0;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/* an interrupt happens */
-
-static int hc_interrupt(void)
-{
-	struct ohci *ohci = &gohci;
-	struct ohci_regs *regs = ohci->regs;
-	int ints;
-	int stat = -1;
-
-	if ((ohci->hcca->done_head != 0) &&
-	    !(m32_swap(ohci->hcca->done_head) & 0x01)) {
-
-		ints = OHCI_INTR_WDH;
-
-	} else {
-		ints = readl(&regs->intrstatus);
-		if (ints == ~(u32) 0) {
-			ohci->disabled++;
-			err("%s device removed!", ohci->slot_name);
-			return -1;
-		}
-		ints &= readl(&regs->intrenable);
-		if (ints == 0) {
-			dbg("hc_interrupt: returning..\n");
-			return 0xff;
-		}
-	}
-
-	/* dbg("Interrupt: %x frame: %x", ints,
-	    le16_to_cpu(ohci->hcca->frame_no)); */
-
-	if (ints & OHCI_INTR_RHSC) {
-		got_rhsc = 1;
-		stat = 0xff;
-	}
-
-	if (ints & OHCI_INTR_UE) {
-		ohci->disabled++;
-		err("OHCI Unrecoverable Error, controller usb-%s disabled",
-		    ohci->slot_name);
-		/* e.g. due to PCI Master/Target Abort */
-
-#ifdef	DEBUG
-		ohci_dump(ohci, 1);
-#else
-		mdelay(1);
-#endif
-		/* FIXME: be optimistic, hope that bug won't repeat often. */
-		/* Make some non-interrupt context restart the controller. */
-		/* Count and limit the retries though; either hardware or */
-		/* software errors can go forever... */
-		hc_reset(ohci);
-		return -1;
-	}
-
-	if (ints & OHCI_INTR_WDH) {
-		mdelay(1);
-
-		writel(OHCI_INTR_WDH, &regs->intrdisable);
-		stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
-		writel(OHCI_INTR_WDH, &regs->intrenable);
-	}
-
-	if (ints & OHCI_INTR_SO) {
-		dbg("USB Schedule overrun\n");
-		writel(OHCI_INTR_SO, &regs->intrenable);
-		stat = -1;
-	}
-
-	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
-	if (ints & OHCI_INTR_SF) {
-		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
-		mdelay(1);
-		writel(OHCI_INTR_SF, &regs->intrdisable);
-		if (ohci->ed_rm_list[frame] != NULL)
-			writel(OHCI_INTR_SF, &regs->intrenable);
-		stat = 0xff;
-	}
-
-	writel(ints, &regs->intrstatus);
-	return stat;
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*-------------------------------------------------------------------------*/
-
-/* De-allocate all resources.. */
-
-static void hc_release_ohci(struct ohci *ohci)
-{
-	dbg("USB HC release ohci usb-%s", ohci->slot_name);
-
-	if (!ohci->disabled)
-		hc_reset(ohci);
-}
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * low level initalisation routine, called from usb.c
- */
-static char ohci_inited = 0;
-
-int usb_lowlevel_init(int index, void **controller)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
-	/*
-	 * Set the 48 MHz UPLL clocking. Values are taken from
-	 * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
-	 */
-	clk_power->upllcon = ((40 << 12) + (1 << 4) + 2);
-	gpio->misccr |= 0x8;	/* 1 = use pads related USB for USB host */
-
-	/*
-	 * Enable USB host clock.
-	 */
-	clk_power->clkcon |= (1 << 4);
-
-	memset(&gohci, 0, sizeof(struct ohci));
-	memset(&urb_priv, 0, sizeof(struct urb_priv));
-
-	/* align the storage */
-	if ((__u32) &ghcca[0] & 0xff) {
-		err("HCCA not aligned!!");
-		return -1;
-	}
-	phcca = &ghcca[0];
-	info("aligned ghcca %p", phcca);
-	memset(&ohci_dev, 0, sizeof(struct ohci_device));
-	if ((__u32) &ohci_dev.ed[0] & 0x7) {
-		err("EDs not aligned!!");
-		return -1;
-	}
-	memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
-	if ((__u32) gtd & 0x7) {
-		err("TDs not aligned!!");
-		return -1;
-	}
-	ptd = gtd;
-	gohci.hcca = phcca;
-	memset(phcca, 0, sizeof(struct ohci_hcca));
-
-	gohci.disabled = 1;
-	gohci.sleeping = 0;
-	gohci.irq = -1;
-	gohci.regs = (struct ohci_regs *)S3C24X0_USB_HOST_BASE;
-
-	gohci.flags = 0;
-	gohci.slot_name = "s3c2400";
-
-	if (hc_reset(&gohci) < 0) {
-		hc_release_ohci(&gohci);
-		/* Initialization failed */
-		clk_power->clkcon &= ~(1 << 4);
-		return -1;
-	}
-
-	/* FIXME this is a second HC reset; why?? */
-	gohci.hc_control = OHCI_USB_RESET;
-	writel(gohci.hc_control, &gohci.regs->control);
-	mdelay(10);
-
-	if (hc_start(&gohci) < 0) {
-		err("can't start usb-%s", gohci.slot_name);
-		hc_release_ohci(&gohci);
-		/* Initialization failed */
-		clk_power->clkcon &= ~(1 << 4);
-		return -1;
-	}
-#ifdef	DEBUG
-	ohci_dump(&gohci, 1);
-#else
-	mdelay(1);
-#endif
-	ohci_inited = 1;
-	urb_finished = 1;
-
-	return 0;
-}
-
-int usb_lowlevel_stop(int index)
-{
-	struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
-
-	/* this gets called really early - before the controller has */
-	/* even been initialized! */
-	if (!ohci_inited)
-		return 0;
-	/* TODO release any interrupts, etc. */
-	/* call hc_release_ohci() here ? */
-	hc_reset(&gohci);
-	/* may not want to do this */
-	clk_power->clkcon &= ~(1 << 4);
-	return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
diff --git a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h b/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
deleted file mode 100644
index f272d78..0000000
--- a/arch/arm/cpu/arm920t/s3c24x0/usb_ohci.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * URB OHCI HCD (Host Controller Driver) for USB.
- *
- * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
- * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
- *
- * usb-ohci.h
- */
-
-
-static int cc_to_error[16] = {
-
-/* mapping of the OHCI CC status to error codes */
-	/* No  Error  */ 0,
-	/* CRC Error  */ USB_ST_CRC_ERR,
-	/* Bit Stuff  */ USB_ST_BIT_ERR,
-	/* Data Togg  */ USB_ST_CRC_ERR,
-	/* Stall      */ USB_ST_STALLED,
-	/* DevNotResp */ -1,
-	/* PIDCheck   */ USB_ST_BIT_ERR,
-	/* UnExpPID   */ USB_ST_BIT_ERR,
-	/* DataOver   */ USB_ST_BUF_ERR,
-	/* DataUnder  */ USB_ST_BUF_ERR,
-	/* reservd    */ -1,
-	/* reservd    */ -1,
-	/* BufferOver */ USB_ST_BUF_ERR,
-	/* BuffUnder  */ USB_ST_BUF_ERR,
-	/* Not Access */ -1,
-	/* Not Access */ -1
-};
-
-/* ED States */
-#define ED_NEW		0x00
-#define ED_UNLINK	0x01
-#define ED_OPER		0x02
-#define ED_DEL		0x04
-#define ED_URB_DEL	0x08
-
-/* usb_ohci_ed */
-struct ed {
-	__u32 hwINFO;
-	__u32 hwTailP;
-	__u32 hwHeadP;
-	__u32 hwNextED;
-
-	struct ed *ed_prev;
-	__u8 int_period;
-	__u8 int_branch;
-	__u8 int_load;
-	__u8 int_interval;
-	__u8 state;
-	__u8 type;
-	__u16 last_iso;
-	struct ed *ed_rm_list;
-
-	struct usb_device *usb_dev;
-	__u32 unused[3];
-} __attribute__ ((aligned(16)));
-
-/* TD info field */
-#define TD_CC			0xf0000000
-#define TD_CC_GET(td_p)		(((td_p) >> 28) & 0x0f)
-#define TD_CC_SET(td_p, cc) \
-	{(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
-#define TD_EC			0x0C000000
-#define TD_T			0x03000000
-#define TD_T_DATA0		0x02000000
-#define TD_T_DATA1		0x03000000
-#define TD_T_TOGGLE		0x00000000
-#define TD_R			0x00040000
-#define TD_DI			0x00E00000
-#define TD_DI_SET(X)		(((X) & 0x07)<< 21)
-#define TD_DP			0x00180000
-#define TD_DP_SETUP		0x00000000
-#define TD_DP_IN		0x00100000
-#define TD_DP_OUT		0x00080000
-
-#define TD_ISO			0x00010000
-#define TD_DEL			0x00020000
-
-/* CC Codes */
-#define TD_CC_NOERROR		0x00
-#define TD_CC_CRC		0x01
-#define TD_CC_BITSTUFFING	0x02
-#define TD_CC_DATATOGGLEM	0x03
-#define TD_CC_STALL		0x04
-#define TD_DEVNOTRESP		0x05
-#define TD_PIDCHECKFAIL	0x06
-#define TD_UNEXPECTEDPID	0x07
-#define TD_DATAOVERRUN		0x08
-#define TD_DATAUNDERRUN	0x09
-#define TD_BUFFEROVERRUN	0x0C
-#define TD_BUFFERUNDERRUN	0x0D
-#define TD_NOTACCESSED		0x0F
-
-
-#define MAXPSW 1
-
-struct td {
-	__u32 hwINFO;
-	__u32 hwCBP;		/* Current Buffer Pointer */
-	__u32 hwNextTD;		/* Next TD Pointer */
-	__u32 hwBE;		/* Memory Buffer End Pointer */
-
-	__u8 unused;
-	__u8 index;
-	struct ed *ed;
-	struct td *next_dl_td;
-	struct usb_device *usb_dev;
-	int transfer_len;
-	__u32 data;
-
-	__u32 unused2[2];
-} __attribute__ ((aligned(32)));
-
-#define OHCI_ED_SKIP	(1 << 14)
-
-/*
- * The HCCA (Host Controller Communications Area) is a 256 byte
- * structure defined in the OHCI spec. that the host controller is
- * told the base address of.  It must be 256-byte aligned.
- */
-
-#define NUM_INTS 32		/* part of the OHCI standard */
-struct ohci_hcca {
-	__u32 int_table[NUM_INTS];	/* Interrupt ED table */
-	__u16 frame_no;		/* current frame number */
-	__u16 pad1;		/* set to 0 on each frame_no change */
-	__u32 done_head;	/* info returned for an interrupt */
-	u8 reserved_for_hc[116];
-} __attribute__ ((aligned(256)));
-
-/*
- * Maximum number of root hub ports.
- */
-#define MAX_ROOT_PORTS	15	/* maximum OHCI root hub ports */
-
-/*
- * This is the structure of the OHCI controller's memory mapped I/O
- * region.  This is Memory Mapped I/O.	You must use the readl() and
- * writel() macros defined in asm/io.h to access these!!
- */
-struct ohci_regs {
-	/* control and status registers */
-	__u32 revision;
-	__u32 control;
-	__u32 cmdstatus;
-	__u32 intrstatus;
-	__u32 intrenable;
-	__u32 intrdisable;
-	/* memory pointers */
-	__u32 hcca;
-	__u32 ed_periodcurrent;
-	__u32 ed_controlhead;
-	__u32 ed_controlcurrent;
-	__u32 ed_bulkhead;
-	__u32 ed_bulkcurrent;
-	__u32 donehead;
-	/* frame counters */
-	__u32 fminterval;
-	__u32 fmremaining;
-	__u32 fmnumber;
-	__u32 periodicstart;
-	__u32 lsthresh;
-	/* Root hub ports */
-	struct ohci_roothub_regs {
-		__u32 a;
-		__u32 b;
-		__u32 status;
-		__u32 portstatus[MAX_ROOT_PORTS];
-	} roothub;
-} __attribute__ ((aligned(32)));
-
-/* OHCI CONTROL AND STATUS REGISTER MASKS */
-
-/*
- * HcControl (control) register masks
- */
-#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
-#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
-#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
-#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
-#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
-#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
-#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
-#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
-#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
-
-/* pre-shifted values for HCFS */
-#	define OHCI_USB_RESET	(0 << 6)
-#	define OHCI_USB_RESUME	(1 << 6)
-#	define OHCI_USB_OPER	(2 << 6)
-#	define OHCI_USB_SUSPEND	(3 << 6)
-
-/*
- * HcCommandStatus (cmdstatus) register masks
- */
-#define OHCI_HCR	(1 << 0)	/* host controller reset */
-#define OHCI_CLF	(1 << 1)	/* control list filled */
-#define OHCI_BLF	(1 << 2)	/* bulk list filled */
-#define OHCI_OCR	(1 << 3)	/* ownership change request */
-#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
-
-/*
- * masks used with interrupt registers:
- * HcInterruptStatus (intrstatus)
- * HcInterruptEnable (intrenable)
- * HcInterruptDisable (intrdisable)
- */
-#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
-#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
-#define OHCI_INTR_SF	(1 << 2)	/* start frame */
-#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
-#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
-#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
-#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
-#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
-#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
-
-/* Virtual Root HUB */
-struct virt_root_hub {
-	int devnum;		/* Address of Root Hub endpoint */
-	void *dev;		/* was urb */
-	void *int_addr;
-	int send;
-	int interval;
-};
-
-/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
-
-/* destination of request */
-#define RH_INTERFACE		0x01
-#define RH_ENDPOINT		0x02
-#define RH_OTHER		0x03
-
-#define RH_CLASS		0x20
-#define RH_VENDOR		0x40
-
-/* Requests: bRequest << 8 | bmRequestType */
-#define RH_GET_STATUS		0x0080
-#define RH_CLEAR_FEATURE	0x0100
-#define RH_SET_FEATURE		0x0300
-#define RH_SET_ADDRESS		0x0500
-#define RH_GET_DESCRIPTOR	0x0680
-#define RH_SET_DESCRIPTOR	0x0700
-#define RH_GET_CONFIGURATION	0x0880
-#define RH_SET_CONFIGURATION	0x0900
-#define RH_GET_STATE		0x0280
-#define RH_GET_INTERFACE	0x0A80
-#define RH_SET_INTERFACE	0x0B00
-#define RH_SYNC_FRAME		0x0C80
-/* Our Vendor Specific Request */
-#define RH_SET_EP		0x2000
-
-
-/* Hub port features */
-#define RH_PORT_CONNECTION	0x00
-#define RH_PORT_ENABLE		0x01
-#define RH_PORT_SUSPEND		0x02
-#define RH_PORT_OVER_CURRENT	0x03
-#define RH_PORT_RESET		0x04
-#define RH_PORT_POWER		0x08
-#define RH_PORT_LOW_SPEED	0x09
-
-#define RH_C_PORT_CONNECTION	0x10
-#define RH_C_PORT_ENABLE	0x11
-#define RH_C_PORT_SUSPEND	0x12
-#define RH_C_PORT_OVER_CURRENT	0x13
-#define RH_C_PORT_RESET		0x14
-
-/* Hub features */
-#define RH_C_HUB_LOCAL_POWER	0x00
-#define RH_C_HUB_OVER_CURRENT	0x01
-
-#define RH_DEVICE_REMOTE_WAKEUP 0x00
-#define RH_ENDPOINT_STALL	0x01
-
-#define RH_ACK			0x01
-#define RH_REQ_ERR		-1
-#define RH_NACK			0x00
-
-
-/* OHCI ROOT HUB REGISTER MASKS */
-
-/* roothub.portstatus [i] bits */
-#define RH_PS_CCS		0x00000001 /* current connect status */
-#define RH_PS_PES		0x00000002 /* port enable status */
-#define RH_PS_PSS		0x00000004 /* port suspend status */
-#define RH_PS_POCI		0x00000008 /* port over current indicator */
-#define RH_PS_PRS		0x00000010 /* port reset status */
-#define RH_PS_PPS		0x00000100 /* port power status */
-#define RH_PS_LSDA		0x00000200 /* low speed device attached */
-#define RH_PS_CSC		0x00010000 /* connect status change */
-#define RH_PS_PESC		0x00020000 /* port enable status change */
-#define RH_PS_PSSC		0x00040000 /* port suspend status change */
-#define RH_PS_OCIC		0x00080000 /* over current indicator change */
-#define RH_PS_PRSC		0x00100000 /* port reset status change */
-
-/* roothub.status bits */
-#define RH_HS_LPS		0x00000001 /* local power status */
-#define RH_HS_OCI		0x00000002 /* over current indicator */
-#define RH_HS_DRWE		0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC		0x00010000 /* local power status change */
-#define RH_HS_OCIC		0x00020000 /* over current indicator change */
-#define RH_HS_CRWE		0x80000000 /* clear remote wakeup enable */
-
-/* roothub.b masks */
-#define RH_B_DR			0x0000ffff /* device removable flags */
-#define RH_B_PPCM		0xffff0000 /* port power control mask */
-
-/* roothub.a masks */
-#define	RH_A_NDP		(0xff << 0)  /* number of downstream ports */
-#define	RH_A_PSM		(1 << 8)     /* power switching mode */
-#define	RH_A_NPS		(1 << 9)     /* no power switching */
-#define	RH_A_DT			(1 << 10)    /* device type (mbz) */
-#define	RH_A_OCPM		(1 << 11)    /* over current protection mode */
-#define	RH_A_NOCP		(1 << 12)    /* no over current protection */
-#define	RH_A_POTPGT		(0xff << 24) /* power on to power good time */
-
-/* urb */
-#define N_URB_TD 48
-struct urb_priv {
-	struct ed *ed;
-	__u16 length;		/* number of tds associated with this request */
-	__u16 td_cnt;		/* number of tds already serviced */
-	int state;
-	unsigned long pipe;
-	int actual_length;
-	struct td *td[N_URB_TD];	/* list pointer to all corresponding TDs
-					   associated with this request */
-};
-#define URB_DEL 1
-
-/*
- * This is the full ohci controller description
- *
- * Note how the "proper" USB information is just
- * a subset of what the full implementation needs. (Linus)
- */
-
-
-struct ohci {
-	struct ohci_hcca *hcca;	/* hcca */
-	/*dma_addr_t hcca_dma; */
-
-	int irq;
-	int disabled;		/* e.g. got a UE, we're hung */
-	int sleeping;
-	unsigned long flags;	/* for HC bugs */
-
-	struct ohci_regs *regs;	/* OHCI controller's memory */
-
-	struct ed *ed_rm_list[2];  /* lists of all endpoints to be removed */
-	struct ed *ed_bulktail;    /* last endpoint of bulk list */
-	struct ed *ed_controltail; /* last endpoint of control list */
-	int intrstatus;
-	__u32 hc_control;	/* copy of the hc control reg */
-	struct usb_device *dev[32];
-	struct virt_root_hub rh;
-
-	const char *slot_name;
-};
-
-#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
-
-struct ohci_device {
-	struct ed ed[NUM_EDS];
-	int ed_cnt;
-};
-
-/* hcd */
-/* endpoint */
-static int ep_link(struct ohci *ohci, struct ed *ed);
-static int ep_unlink(struct ohci *ohci, struct ed *ed);
-static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
-
-/*-------------------------------------------------------------------------*/
-
-/* we need more TDs than EDs */
-#define NUM_TD 64
-
-/* +1 so we can align the storage */
-struct td gtd[NUM_TD + 1];
-
-/* pointers to aligned storage */
-struct td *ptd;
-
-/* TDs ... */
-static inline struct td *td_alloc(struct usb_device *usb_dev)
-{
-	int i;
-	struct td *td;
-
-	td = NULL;
-	for (i = 0; i < NUM_TD; i++) {
-		if (ptd[i].usb_dev == NULL) {
-			td = &ptd[i];
-			td->usb_dev = usb_dev;
-			break;
-		}
-	}
-
-	return td;
-}
-
-static inline void ed_free(struct ed *ed)
-{
-	ed->usb_dev = NULL;
-}
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
index 6d77219..9348552 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
@@ -118,6 +118,21 @@ void at91_serial2_hw_init(void)
 	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
+void at91_mci_hw_init(void)
+{
+	/* Initialize the MCI0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 17, 1);	/* MCCK */
+	at91_set_a_periph(AT91_PIO_PORTA, 16, 1);	/* MCCDA */
+	at91_set_a_periph(AT91_PIO_PORTA, 15, 1);	/* MCDA0 */
+	at91_set_a_periph(AT91_PIO_PORTA, 18, 1);	/* MCDA1 */
+	at91_set_a_periph(AT91_PIO_PORTA, 19, 1);	/* MCDA2 */
+	at91_set_a_periph(AT91_PIO_PORTA, 20, 1);	/* MCDA3 */
+
+	/* Enable clock for MCI0 */
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
+}
+
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index f8ea38c..6dc681a 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -50,9 +50,10 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index afd3381..f3bd5e7 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -50,9 +50,10 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile
index 7768912..74875b3 100644
--- a/arch/arm/cpu/armv7/am33xx/Makefile
+++ b/arch/arm/cpu/armv7/am33xx/Makefile
@@ -21,6 +21,7 @@ COBJS	+= sys_info.o
 COBJS	+= ddr.o
 COBJS	+= emif4.o
 COBJS	+= board.o
+COBJS	+= mux.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 978b184..e4c123c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -36,9 +36,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
-
 static const struct gpio_bank gpio_bank_am33xx[4] = {
 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -48,153 +45,11 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
 
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 
-/* MII mode defines */
-#define MII_MODE_ENABLE		0x0
-#define RGMII_MODE_ENABLE	0xA
-
-/* GPIO that controls power to DDR on EVM-SK */
-#define GPIO_DDR_VTT_EN		7
-
-static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
-
-static struct am335x_baseboard_id __attribute__((section (".data"))) header;
-
-static inline int board_is_bone(void)
-{
-	return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
-}
-
-static inline int board_is_evm_sk(void)
-{
-	return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
-}
-
-/*
- * Read header information from EEPROM into global structure.
- */
-static int read_eeprom(void)
-{
-	/* Check if baseboard eeprom is available */
-	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
-		puts("Could not probe the EEPROM; something fundamentally "
-			"wrong on the I2C bus.\n");
-		return -ENODEV;
-	}
-
-	/* read the eeprom using i2c */
-	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
-							sizeof(header))) {
-		puts("Could not read the EEPROM; something fundamentally"
-			" wrong on the I2C bus.\n");
-		return -EIO;
-	}
-
-	if (header.magic != 0xEE3355AA) {
-		/*
-		 * read the eeprom using i2c again,
-		 * but use only a 1 byte address
-		 */
-		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
-					(uchar *)&header, sizeof(header))) {
-			puts("Could not read the EEPROM; something "
-				"fundamentally wrong on the I2C bus.\n");
-			return -EIO;
-		}
-
-		if (header.magic != 0xEE3355AA) {
-			printf("Incorrect magic number (0x%x) in EEPROM\n",
-					header.magic);
-			return -EINVAL;
-		}
-	}
-
-	return 0;
-}
-
-/* UART Defines */
-#ifdef CONFIG_SPL_BUILD
-#define UART_RESET		(0x1 << 1)
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-#endif
-
-/*
- * Determine what type of DDR we have.
- */
-static short inline board_memory_type(void)
-{
-	/* The following boards are known to use DDR3. */
-	if (board_is_evm_sk())
-		return EMIF_REG_SDRAM_TYPE_DDR3;
-
-	return EMIF_REG_SDRAM_TYPE_DDR2;
-}
-
-/*
- * early system init of muxing and clocks.
- */
-void s_init(void)
-{
-	/* WDT1 is already running when the bootloader gets control
-	 * Disable it to avoid "random" resets
-	 */
-	writel(0xAAAA, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-	writel(0x5555, &wdtimer->wdtwspr);
-	while (readl(&wdtimer->wdtwwps) != 0x0)
-		;
-
-#ifdef CONFIG_SPL_BUILD
-	/* Setup the PLLs and the clocks for the peripherals */
-	pll_init();
-
-	/* UART softreset */
-	u32 regVal;
-
-	enable_uart0_pin_mux();
-
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_RESET;
-	writel(regVal, &uart_base->uartsyscfg);
-	while ((readl(&uart_base->uartsyssts) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	regVal = readl(&uart_base->uartsyscfg);
-	regVal |= UART_SMART_IDLE_EN;
-	writel(regVal, &uart_base->uartsyscfg);
-
-	gd = &gdata;
-
-	preloader_console_init();
-
-	/* Initalize the board header */
-	enable_i2c0_pin_mux();
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
-	enable_board_pin_mux(&header);
-	if (board_is_evm_sk()) {
-		/*
-		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
-		 * This is safe enough to do on older revs.
-		 */
-		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
-		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
-	}
-
-	config_ddr(board_memory_type());
-#endif
-}
-
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
-int board_mmc_init(bd_t *bis)
+int cpu_mmc_init(bd_t *bis)
 {
 	int ret;
-	
+
 	ret = omap_mmc_init(0, 0, 0);
 	if (ret)
 		return ret;
@@ -208,93 +63,3 @@ void setup_clocks_for_console(void)
 	/* Not yet implemented */
 	return;
 }
-
-/*
- * Basic board specific setup.  Pinmux has been handled already.
- */
-int board_init(void)
-{
-	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-	if (read_eeprom() < 0)
-		puts("Could not get board ID.\n");
-
-	gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
-
-	return 0;
-}
-
-#ifdef CONFIG_DRIVER_TI_CPSW
-static void cpsw_control(int enabled)
-{
-	/* VTP can be added here */
-
-	return;
-}
-
-static struct cpsw_slave_data cpsw_slaves[] = {
-	{
-		.slave_reg_ofs	= 0x208,
-		.sliver_reg_ofs	= 0xd80,
-		.phy_id		= 0,
-	},
-	{
-		.slave_reg_ofs	= 0x308,
-		.sliver_reg_ofs	= 0xdc0,
-		.phy_id		= 1,
-	},
-};
-
-static struct cpsw_platform_data cpsw_data = {
-	.mdio_base		= AM335X_CPSW_MDIO_BASE,
-	.cpsw_base		= AM335X_CPSW_BASE,
-	.mdio_div		= 0xff,
-	.channels		= 8,
-	.cpdma_reg_ofs		= 0x800,
-	.slaves			= 1,
-	.slave_data		= cpsw_slaves,
-	.ale_reg_ofs		= 0xd00,
-	.ale_entries		= 1024,
-	.host_port_reg_ofs	= 0x108,
-	.hw_stats_reg_ofs	= 0x900,
-	.mac_control		= (1 << 5),
-	.control		= cpsw_control,
-	.host_port_num		= 0,
-	.version		= CPSW_CTRL_VERSION_2,
-};
-
-int board_eth_init(bd_t *bis)
-{
-	uint8_t mac_addr[6];
-	uint32_t mac_hi, mac_lo;
-
-	if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
-		debug("<ethaddr> not set. Reading from E-fuse\n");
-		/* try reading mac address from efuse */
-		mac_lo = readl(&cdev->macid0l);
-		mac_hi = readl(&cdev->macid0h);
-		mac_addr[0] = mac_hi & 0xFF;
-		mac_addr[1] = (mac_hi & 0xFF00) >> 8;
-		mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
-		mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
-		mac_addr[4] = mac_lo & 0xFF;
-		mac_addr[5] = (mac_lo & 0xFF00) >> 8;
-
-		if (is_valid_ether_addr(mac_addr))
-			eth_setenv_enetaddr("ethaddr", mac_addr);
-		else
-			return -1;
-	}
-
-	if (board_is_bone()) {
-		writel(MII_MODE_ENABLE, &cdev->miisel);
-		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-				PHY_INTERFACE_MODE_MII;
-	} else {
-		writel(RGMII_MODE_ENABLE, &cdev->miisel);
-		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
-				PHY_INTERFACE_MODE_RGMII;
-	}
-
-	return cpsw_register(&cpsw_data);
-}
-#endif
diff --git a/arch/arm/cpu/armv7/am33xx/clock.c b/arch/arm/cpu/armv7/am33xx/clock.c
index 2b19506..bc2abb6 100644
--- a/arch/arm/cpu/armv7/am33xx/clock.c
+++ b/arch/arm/cpu/armv7/am33xx/clock.c
@@ -44,6 +44,7 @@
 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
+const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
 
 static void enable_interface_clocks(void)
 {
@@ -114,6 +115,41 @@ static void enable_per_clocks(void)
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
 
+	/* UART1 */
+#ifdef CONFIG_SERIAL2
+	writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
+	while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL2 */
+
+	/* UART2 */
+#ifdef CONFIG_SERIAL3
+	writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
+	while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL3 */
+
+	/* UART3 */
+#ifdef CONFIG_SERIAL4
+	writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
+	while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL4 */
+
+	/* UART4 */
+#ifdef CONFIG_SERIAL5
+	writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
+	while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL5 */
+
+	/* UART5 */
+#ifdef CONFIG_SERIAL6
+	writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
+	while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
+		;
+#endif /* CONFIG_SERIAL6 */
+
 	/* MMC0*/
 	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
@@ -153,6 +189,11 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
 	while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
 		;
+
+	/* RTC */
+	writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
+	while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)
diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk
index 5750bbd..babf0eb 100644
--- a/arch/arm/cpu/armv7/am33xx/config.mk
+++ b/arch/arm/cpu/armv7/am33xx/config.mk
@@ -13,6 +13,7 @@
 #
 ifdef CONFIG_SPL_BUILD
 ALL-y	+= $(OBJTREE)/MLO
+ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap
 else
 ALL-y	+= $(obj)u-boot.img
 endif
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c
index b2d7c0d..01e3a52 100644
--- a/arch/arm/cpu/armv7/am33xx/emif4.c
+++ b/arch/arm/cpu/armv7/am33xx/emif4.c
@@ -47,78 +47,6 @@ void dram_init_banksize(void)
 static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
 
-static const struct ddr_data ddr2_data = {
-	.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
-				|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
-	.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
-				|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
-	.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
-				|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
-	.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
-				|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
-	.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
-				|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
-	.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
-				|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
-	.datauserank0delay = DDR2_PHY_RANK0_DELAY,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr2_cmd_ctrl_data = {
-	.cmd0csratio = DDR2_RATIO,
-	.cmd0dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd0iclkout = DDR2_INVERT_CLKOUT,
-
-	.cmd1csratio = DDR2_RATIO,
-	.cmd1dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd1iclkout = DDR2_INVERT_CLKOUT,
-
-	.cmd2csratio = DDR2_RATIO,
-	.cmd2dldiff = DDR2_DLL_LOCK_DIFF,
-	.cmd2iclkout = DDR2_INVERT_CLKOUT,
-};
-
-static const struct emif_regs ddr2_emif_reg_data = {
-	.sdram_config = DDR2_EMIF_SDCFG,
-	.ref_ctrl = DDR2_EMIF_SDREF,
-	.sdram_tim1 = DDR2_EMIF_TIM1,
-	.sdram_tim2 = DDR2_EMIF_TIM2,
-	.sdram_tim3 = DDR2_EMIF_TIM3,
-	.emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
-};
-
-static const struct ddr_data ddr3_data = {
-	.datardsratio0 = DDR3_RD_DQS,
-	.datawdsratio0 = DDR3_WR_DQS,
-	.datafwsratio0 = DDR3_PHY_FIFO_WE,
-	.datawrsratio0 = DDR3_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
-};
-
-static const struct cmd_control ddr3_cmd_ctrl_data = {
-	.cmd0csratio = DDR3_RATIO,
-	.cmd0dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd0iclkout = DDR3_INVERT_CLKOUT,
-
-	.cmd1csratio = DDR3_RATIO,
-	.cmd1dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd1iclkout = DDR3_INVERT_CLKOUT,
-
-	.cmd2csratio = DDR3_RATIO,
-	.cmd2dldiff = DDR3_DLL_LOCK_DIFF,
-	.cmd2iclkout = DDR3_INVERT_CLKOUT,
-};
-
-static struct emif_regs ddr3_emif_reg_data = {
-	.sdram_config = DDR3_EMIF_SDCFG,
-	.ref_ctrl = DDR3_EMIF_SDREF,
-	.sdram_tim1 = DDR3_EMIF_TIM1,
-	.sdram_tim2 = DDR3_EMIF_TIM2,
-	.sdram_tim3 = DDR3_EMIF_TIM3,
-	.zq_config = DDR3_ZQ_CFG,
-	.emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
-};
-
 static void config_vtp(void)
 {
 	writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
@@ -134,46 +62,26 @@ static void config_vtp(void)
 		;
 }
 
-void config_ddr(short ddr_type)
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs)
 {
-	int ddr_pll, ioctrl_val;
-	const struct emif_regs *emif_regs;
-	const struct ddr_data *ddr_data;
-	const struct cmd_control *cmd_ctrl_data;
-
-	if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
-		ddr_pll = 266;
-		cmd_ctrl_data = &ddr2_cmd_ctrl_data;
-		ddr_data = &ddr2_data;
-		ioctrl_val = DDR2_IOCTRL_VALUE;
-		emif_regs = &ddr2_emif_reg_data;
-	} else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
-		ddr_pll = 303;
-		cmd_ctrl_data = &ddr3_cmd_ctrl_data;
-		ddr_data = &ddr3_data;
-		ioctrl_val = DDR3_IOCTRL_VALUE;
-		emif_regs = &ddr3_emif_reg_data;
-	} else {
-		puts("Unknown memory type");
-		hang();
-	}
-
 	enable_emif_clocks();
-	ddr_pll_config(ddr_pll);
+	ddr_pll_config(pll);
 	config_vtp();
-	config_cmd_ctrl(cmd_ctrl_data);
+	config_cmd_ctrl(ctrl);
 
-	config_ddr_data(0, ddr_data);
-	config_ddr_data(1, ddr_data);
+	config_ddr_data(0, data);
+	config_ddr_data(1, data);
 
-	config_io_ctrl(ioctrl_val);
+	config_io_ctrl(ioctrl);
 
 	/* Set CKE to be controlled by EMIF/DDR PHY */
 	writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
 
 	/* Program EMIF instance */
-	config_ddr_phy(emif_regs);
-	set_sdram_timings(emif_regs);
-	config_sdram(emif_regs);
+	config_ddr_phy(regs);
+	set_sdram_timings(regs);
+	config_sdram(regs);
 }
 #endif
diff --git a/arch/arm/cpu/armv7/am33xx/mux.c b/arch/arm/cpu/armv7/am33xx/mux.c
new file mode 100644
index 0000000..2ded472
--- /dev/null
+++ b/arch/arm/cpu/armv7/am33xx/mux.c
@@ -0,0 +1,33 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
+{
+	int i;
+
+	if (!mod_pin_mux)
+		return;
+
+	for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
+		MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
+}
diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
index 1d8efb2..9979c30 100644
--- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
+++ b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds
@@ -47,6 +47,11 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
+
 	. = ALIGN(4);
 	__image_copy_end = .;
 	_end = .;
diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 9cee1d9..f3cd81a 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -50,7 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
+#ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_invalidate_l2_cache_secure(void);
+#endif
 
 static const struct gpio_bank gpio_bank_34xx[6] = {
 	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
@@ -410,19 +412,6 @@ static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
 	}
 }
 
-static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
-{
-	u32 acr;
-
-	/* Read ACR */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-	acr &= ~clear_bits;
-	acr |= set_bits;
-
-	/* Write ACR - affects non-secure banked bits */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
-}
-
 static void omap3_setup_aux_cr(void)
 {
 	/* Workaround for Cortex-A8 errata: #454179 #430973
@@ -436,6 +425,19 @@ static void omap3_setup_aux_cr(void)
 }
 
 #ifndef CONFIG_SYS_L2CACHE_OFF
+static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
+{
+	u32 acr;
+
+	/* Read ACR */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
+	acr &= ~clear_bits;
+	acr |= set_bits;
+
+	/* Write ACR - affects non-secure banked bits */
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
+}
+
 /* Invalidate the entire L2 cache from secure mode */
 static void omap3_invalidate_l2_cache_secure(void)
 {
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 944238b..84216eb 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -21,7 +21,6 @@
 #include <asm/utils.h>
 #include <version.h>
 #include <image.h>
-#include <malloc.h>
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
 
@@ -37,9 +36,6 @@ u32 spl_boot_device(void)
  */
 void spl_board_init(void)
 {
-	/* init timer for enabling delay function */
-	timer_init();
-
 	/* de-assert reset for peripherals and bridges based on handoff */
 	reset_deassert_peripherals_handoff();
 
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index 7199de4..81d954f 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -46,9 +46,11 @@ SECTIONS
 	. = ALIGN(4);
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/arm/cpu/lh7a40x/speed.c b/arch/arm/cpu/lh7a40x/speed.c
deleted file mode 100644
index 333ebb5..0000000
--- a/arch/arm/cpu/lh7a40x/speed.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_PLLCLK (void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-	ulong maindiv1, maindiv2, prediv, ps;
-
-	/*
-	 * from userguide 6.1.1.2
-	 *
-	 * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
-	 *                   ((PREDIV+2) * (2^PS))
-	 */
-	maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
-	maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
-	prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
-	ps = (csc->clkset & CLKSET_PS) >> 16;
-
-	return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
-		((prediv + 2) * (1 << ps)));
-}
-
-
-/* return HCLK frequency */
-ulong get_HCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-	return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
-}
-
-/* return PCLK frequency */
-ulong get_PCLK (void)
-{
-	lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
-	return (get_HCLK () /
-		(1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
-}
diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S
deleted file mode 100644
index 33b9269..0000000
--- a/arch/arm/cpu/lh7a40x/start.S
+++ /dev/null
@@ -1,506 +0,0 @@
-/*
- *  armboot - Startup Code for ARM920 CPU-core
- *
- *  Copyright (c) 2001	Marius Gröger <mag@sysgo.de>
- *  Copyright (c) 2002	Alex Züpke <azu@sysgo.de>
- *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start:	b       reset
-	ldr	pc, _undefined_instruction
-	ldr	pc, _software_interrupt
-	ldr	pc, _prefetch_abort
-	ldr	pc, _data_abort
-	ldr	pc, _not_used
-	ldr	pc, _irq
-	ldr	pc, _fiq
-
-_undefined_instruction:	.word undefined_instruction
-_software_interrupt:	.word software_interrupt
-_prefetch_abort:	.word prefetch_abort
-_data_abort:		.word data_abort
-_not_used:		.word not_used
-_irq:			.word irq
-_fiq:			.word fiq
-
-	.balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
-	.word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
-	.word __bss_end__ - _start
-
-.globl _end_ofs
-_end_ofs:
-	.word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
-	.word	0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
-	.word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
-	.word	0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
-	/*
-	 * set the cpu to SVC32 mode
-	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
-
-#define pWDTCTL		0x80001400  /* Watchdog Timer control register */
-#define pINTENC		0x8000050C  /* Interrupt-Controller enable clear register */
-#define pCLKSET		0x80000420  /* clock divisor register */
-
-	/* disable watchdog, set watchdog control register to
-	 * all zeros (default reset)
-	 */
-	ldr     r0, =pWDTCTL
-	mov     r1, #0x0
-	str     r1, [r0]
-
-	/*
-	 * mask all IRQs by setting all bits in the INTENC register (default)
-	 */
-	mov	r1, #0xffffffff
-	ldr	r0, =pINTENC
-	str	r1, [r0]
-
-	/* FCLK:HCLK:PCLK = 1:2:2 */
-	/* default FCLK is 200 MHz, using 14.7456 MHz fin */
-	ldr	r0, =pCLKSET
-	ldr r1, =0x0004ee39
-@	ldr r1, =0x0005ee39	@ 1: 2: 4
-	str	r1, [r0]
-
-	/*
-	 * we do sys-critical inits only at reboot,
-	 * not when booting from ram!
-	 */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-	bl	cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
-	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
-	bic	sp, sp, #7 /* 8-byte alignment for ABI compliance */
-	ldr	r0,=0x00000000
-	bl	board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
-	.globl	relocate_code
-relocate_code:
-	mov	r4, r0	/* save addr_sp */
-	mov	r5, r1	/* save addr of gd */
-	mov	r6, r2	/* save addr of destination */
-
-	/* Set up the stack						    */
-stack_setup:
-	mov	sp, r4
-
-	adr	r0, _start
-	cmp	r0, r6
-	moveq	r9, #0		/* no relocation. relocation offset(r9) = 0 */
-	beq	clear_bss		/* skip relocation */
-	mov	r1, r6			/* r1 <- scratch for copy_loop */
-	ldr	r3, _bss_start_ofs
-	add	r2, r0, r3		/* r2 <- source end address	    */
-
-copy_loop:
-	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
-	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
-	cmp	r0, r2			/* until source end address [r2]    */
-	blo	copy_loop
-
-#ifndef CONFIG_SPL_BUILD
-	/*
-	 * fix .rel.dyn relocations
-	 */
-	ldr	r0, _TEXT_BASE		/* r0 <- Text base */
-	sub	r9, r6, r0		/* r9 <- relocation offset */
-	ldr	r10, _dynsym_start_ofs	/* r10 <- sym table ofs */
-	add	r10, r10, r0		/* r10 <- sym table in FLASH */
-	ldr	r2, _rel_dyn_start_ofs	/* r2 <- rel dyn start ofs */
-	add	r2, r2, r0		/* r2 <- rel dyn start in FLASH */
-	ldr	r3, _rel_dyn_end_ofs	/* r3 <- rel dyn end ofs */
-	add	r3, r3, r0		/* r3 <- rel dyn end in FLASH */
-fixloop:
-	ldr	r0, [r2]		/* r0 <- location to fix up, IN FLASH! */
-	add	r0, r0, r9		/* r0 <- location to fix up in RAM */
-	ldr	r1, [r2, #4]
-	and	r7, r1, #0xff
-	cmp	r7, #23			/* relative fixup? */
-	beq	fixrel
-	cmp	r7, #2			/* absolute fixup? */
-	beq	fixabs
-	/* ignore unknown type of fixup */
-	b	fixnext
-fixabs:
-	/* absolute fix: set location to (offset) symbol value */
-	mov	r1, r1, LSR #4		/* r1 <- symbol index in .dynsym */
-	add	r1, r10, r1		/* r1 <- address of symbol in table */
-	ldr	r1, [r1, #4]		/* r1 <- symbol value */
-	add	r1, r1, r9		/* r1 <- relocated sym addr */
-	b	fixnext
-fixrel:
-	/* relative fix: increase location by offset */
-	ldr	r1, [r0]
-	add	r1, r1, r9
-fixnext:
-	str	r1, [r0]
-	add	r2, r2, #8		/* each rel.dyn entry is 8 bytes */
-	cmp	r2, r3
-	blo	fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
-	ldr	r0, _bss_start_ofs
-	ldr	r1, _bss_end_ofs
-	mov	r4, r6			/* reloc addr */
-	add	r0, r0, r4
-	add	r1, r1, r4
-	mov	r2, #0x00000000		/* clear			    */
-
-clbss_l:cmp	r0, r1			/* clear loop... */
-	bhs	clbss_e			/* if reached end of bss, exit */
-	str	r2, [r0]
-	add	r0, r0, #4
-	b	clbss_l
-clbss_e:
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
-	ldr	r0, _board_init_r_ofs
-	adr	r1, _start
-	add	lr, r0, r1
-	add	lr, lr, r9
-	/* setup parameters for board_init_r */
-	mov	r0, r5		/* gd_t */
-	mov	r1, r6		/* dest_addr */
-	/* jump to it ... */
-	mov	pc, lr
-
-_board_init_r_ofs:
-	.word board_init_r - _start
-
-_rel_dyn_start_ofs:
-	.word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
-	.word __rel_dyn_end - _start
-_dynsym_start_ofs:
-	.word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
-	/*
-	 * flush v4 I/D caches
-	 */
-	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
-
-	/*
-	 * disable MMU stuff and caches
-	 */
-	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
-	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
-	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
-	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
-	orr	r0, r0, #0x40000000	@ set bit 30 (nF) notFastBus
-	mcr	p15, 0, r0, c1, c0, 0
-
-
-	/*
-	 * before relocating, we have to setup RAM timing
-	 * because memory timing is board-dependend, you will
-	 * find a lowlevel_init.S in your board directory.
-	 */
-	mov	ip, lr
-	bl	lowlevel_init
-	mov	lr, ip
-
-	mov	pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE	72
-
-#define S_OLD_R0	68
-#define S_PSR		64
-#define S_PC		60
-#define S_LR		56
-#define S_SP		52
-
-#define S_IP		48
-#define S_FP		44
-#define S_R10		40
-#define S_R9		36
-#define S_R8		32
-#define S_R7		28
-#define S_R6		24
-#define S_R5		20
-#define S_R4		16
-#define S_R3		12
-#define S_R2		8
-#define S_R1		4
-#define S_R0		0
-
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
-	.macro	bad_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	ldr	r2, IRQ_STACK_START_IN
-	ldmia	r2, {r2 - r3}			@ get pc, cpsr
-	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
-
-	add	r5, sp, #S_SP
-	mov	r1, lr
-	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
-	mov	r0, sp
-	.endm
-
-	.macro	irq_save_user_regs
-	sub	sp, sp, #S_FRAME_SIZE
-	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r8, sp, #S_PC
-	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r8, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r8, #4]                    @ Save CPSR
-	str     r0, [r8, #8]                    @ Save OLD_R0
-	mov	r0, sp
-	.endm
-
-	.macro	irq_restore_user_regs
-	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
-	mov	r0, r0
-	ldr	lr, [sp, #S_PC]			@ Get PC
-	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
-	.endm
-
-	.macro get_bad_stack
-	ldr	r13, IRQ_STACK_START_IN		@ setup our mode stack
-
-	str	lr, [r13]			@ save caller lr / spsr
-	mrs	lr, spsr
-	str     lr, [r13, #4]
-
-	mov	r13, #MODE_SVC			@ prepare SVC-Mode
-	@ msr	spsr_c, r13
-	msr	spsr, r13
-	mov	lr, pc
-	movs	pc, lr
-	.endm
-
-	.macro get_irq_stack			@ setup IRQ stack
-	ldr	sp, IRQ_STACK_START
-	.endm
-
-	.macro get_fiq_stack			@ setup FIQ stack
-	ldr	sp, FIQ_STACK_START
-	.endm
-
-/*
- * exception handlers
- */
-	.align  5
-undefined_instruction:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_undefined_instruction
-
-	.align	5
-software_interrupt:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_software_interrupt
-
-	.align	5
-prefetch_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_prefetch_abort
-
-	.align	5
-data_abort:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_data_abort
-
-	.align	5
-not_used:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
-	.align	5
-irq:
-	get_irq_stack
-	irq_save_user_regs
-	bl	do_irq
-	irq_restore_user_regs
-
-	.align	5
-fiq:
-	get_fiq_stack
-	/* someone ought to write a more effiction fiq_save_user_regs */
-	irq_save_user_regs
-	bl	do_fiq
-	irq_restore_user_regs
-
-#else
-
-	.align	5
-irq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_irq
-
-	.align	5
-fiq:
-	get_bad_stack
-	bad_save_user_regs
-	bl	do_fiq
-
-#endif
-
-	.align	5
-.globl reset_cpu
-reset_cpu:
-	bl	disable_interrupts
-
-	/* Disable watchdog */
-	ldr	r1, =pWDTCTL
-	mov	r3, #0
-	str	r3, [r1]
-
-	/* reset counter */
-	ldr	r3, =0x00001984
-	str	r3, [r1, #4]
-
-	/* Enable the watchdog */
-	mov	r3, #1
-	str	r3, [r1]
-
-_loop_forever:
-	b	_loop_forever
diff --git a/arch/arm/cpu/lh7a40x/timer.c b/arch/arm/cpu/lh7a40x/timer.c
deleted file mode 100644
index 58b35b1..0000000
--- a/arch/arm/cpu/lh7a40x/timer.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-static ulong timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	return (timer->value & 0x0000ffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	/* a periodic timer using the 508kHz source */
-	timer->control = (TIMER_PER | TIMER_CLK508K);
-
-	if (timer_load_val == 0) {
-		/*
-		 * 10ms period with 508.469kHz clock = 5084
-		 */
-		timer_load_val = CONFIG_SYS_HZ/100;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timer->load = timer_load_val;
-
-	/* auto load, start timer */
-	timer->control = timer->control | TIMER_EN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-	return (get_timer_masked() - base);
-}
-
-void __udelay (unsigned long usec)
-{
-	ulong tmo,tmp;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	}
-	else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		}
-		else
-			tmo = 1;
-	}
-
-	/* check for rollover during this delay */
-	tmp = get_timer (0);
-	if ((tmp + tmo) < tmp )
-		reset_timer_masked();  /* timer would roll over */
-	else
-		tmo += tmp;
-
-	while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += (lastdec - now);
-	} else {
-		/* we have an overflow ... */
-		timestamp += ((lastdec + timer_load_val) - now);
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		} else {
-			tmo = 1;
-		}
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = timer_load_val * 100;
-
-	return tbclk;
-}
diff --git a/arch/arm/cpu/tegra20-common/emc.c b/arch/arm/cpu/tegra20-common/emc.c
index 97420d7..90edf00 100644
--- a/arch/arm/cpu/tegra20-common/emc.c
+++ b/arch/arm/cpu/tegra20-common/emc.c
@@ -257,7 +257,7 @@ static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp,
 int tegra_set_emc(const void *blob, unsigned rate)
 {
 	struct emc_ctlr *emc;
-	const u32 *table;
+	const u32 *table = NULL;
 	int err, i;
 
 	err = decode_emc(blob, rate, &emc, &table);
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index e49ca0c..e6b202b 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -34,8 +34,8 @@ SECTIONS
 	.text :
 	{
 		__image_copy_start = .;
-		CPUDIR/start.o (.text)
-		*(.text)
+		CPUDIR/start.o (.text*)
+		*(.text*)
 	}
 
 	. = ALIGN(4);
@@ -43,15 +43,17 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : {
-		*(.data)
+		*(.data*)
 	}
 
 	. = ALIGN(4);
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
@@ -81,7 +83,7 @@ SECTIONS
 
 	.bss __rel_dyn_start (OVERLAY) : {
 		__bss_start = .;
-		*(.bss)
+		*(.bss*)
 		 . = ALIGN(4);
 		__bss_end__ = .;
 	}
@@ -92,3 +94,7 @@ SECTIONS
 	/DISCARD/ : { *(.interp*) }
 	/DISCARD/ : { *(.gnu*) }
 }
+
+#if defined(CONFIG_SPL_TEXT_BASE) && defined(CONFIG_SPL_MAX_SIZE)
+ASSERT(__bss_end__ < (CONFIG_SPL_TEXT_BASE + CONFIG_SPL_MAX_SIZE), "SPL image too big");
+#endif
diff --git a/arch/arm/imx-common/cmd_bmode.c b/arch/arm/imx-common/cmd_bmode.c
index 02fe72e..ddc14b0 100644
--- a/arch/arm/imx-common/cmd_bmode.c
+++ b/arch/arm/imx-common/cmd_bmode.c
@@ -24,6 +24,7 @@
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 #include <malloc.h>
+#include <command.h>
 
 static const struct boot_mode *modes[2];
 
@@ -103,9 +104,11 @@ void add_board_boot_modes(const struct boot_mode *p)
 	int size;
 	char *dest;
 
-	if (__u_boot_cmd_bmode.usage) {
-		free(__u_boot_cmd_bmode.usage);
-		__u_boot_cmd_bmode.usage = NULL;
+	cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+	if (entry->usage) {
+		free(entry->usage);
+		entry->usage = NULL;
 	}
 
 	modes[0] = p;
@@ -114,6 +117,6 @@ void add_board_boot_modes(const struct boot_mode *p)
 	dest = malloc(size);
 	if (dest) {
 		create_usage(dest);
-		__u_boot_cmd_bmode.usage = dest;
+		entry->usage = dest;
 	}
 }
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 6cfbef7..819fd2f 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -169,6 +169,12 @@ struct cm_dpll {
 	unsigned int clktimer2clk;	/* offset 0x08 */
 };
 
+/* Control Module RTC registers */
+struct cm_rtc {
+	unsigned int rtcclkctrl;	/* offset 0x0 */
+	unsigned int clkstctrl;		/* offset 0x4 */
+};
+
 /* Watchdog timer registers */
 struct wd_timer {
 	unsigned int resv1[4];
@@ -218,6 +224,15 @@ struct gptimer {
 	unsigned int tcar2;		/* offset 0x58 */
 };
 
+/* RTC Registers */
+struct rtc_regs {
+	unsigned int res[21];
+	unsigned int osc;		/* offset 0x54 */
+	unsigned int res2[5];
+	unsigned int kick0r;		/* offset 0x6c */
+	unsigned int kick1r;		/* offset 0x70 */
+};
+
 /* UART Registers */
 struct uart_sys {
 	unsigned int resv1[21];
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6b22c45..8e69fb6 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,40 +29,41 @@
 #define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
 
-#define DDR2_EMIF_READ_LATENCY	0x100005	/* Enable Dynamic Power Down */
-#define DDR2_EMIF_TIM1		0x0666B3C9
-#define DDR2_EMIF_TIM2		0x243631CA
-#define DDR2_EMIF_TIM3		0x0000033F
-#define DDR2_EMIF_SDCFG		0x41805332
-#define DDR2_EMIF_SDREF		0x0000081a
-#define DDR2_DLL_LOCK_DIFF	0x0
-#define DDR2_RATIO		0x80
-#define DDR2_INVERT_CLKOUT	0x00
-#define DDR2_RD_DQS		0x12
-#define DDR2_WR_DQS		0x00
-#define DDR2_PHY_WRLVL		0x00
-#define DDR2_PHY_GATELVL	0x00
-#define DDR2_PHY_WR_DATA	0x40
-#define DDR2_PHY_FIFO_WE	0x80
-#define DDR2_PHY_RANK0_DELAY	0x1
-#define DDR2_IOCTRL_VALUE	0x18B
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
+#define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
+#define MT47H128M16RT25E_DLL_LOCK_DIFF		0x0
+#define MT47H128M16RT25E_RATIO			0x80
+#define MT47H128M16RT25E_INVERT_CLKOUT		0x00
+#define MT47H128M16RT25E_RD_DQS			0x12
+#define MT47H128M16RT25E_WR_DQS			0x00
+#define MT47H128M16RT25E_PHY_WRLVL		0x00
+#define MT47H128M16RT25E_PHY_GATELVL		0x00
+#define MT47H128M16RT25E_PHY_WR_DATA		0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE		0x80
+#define MT47H128M16RT25E_PHY_RANK0_DELAY		0x1
+#define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY	0x06
-#define DDR3_EMIF_TIM1		0x0888A39B
-#define DDR3_EMIF_TIM2		0x26337FDA
-#define DDR3_EMIF_TIM3		0x501F830F
-#define DDR3_EMIF_SDCFG		0x61C04AB2
-#define DDR3_EMIF_SDREF		0x0000093B
-#define DDR3_ZQ_CFG		0x50074BE4
-#define DDR3_DLL_LOCK_DIFF	0x1
-#define DDR3_RATIO		0x40
-#define DDR3_INVERT_CLKOUT	0x1
-#define DDR3_RD_DQS		0x3B
-#define DDR3_WR_DQS		0x85
-#define DDR3_PHY_WR_DATA	0xC1
-#define DDR3_PHY_FIFO_WE	0x100
-#define DDR3_IOCTRL_VALUE	0x18B
+#define MT41J128MJT125_EMIF_READ_LATENCY	0x06
+#define MT41J128MJT125_EMIF_TIM1		0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2		0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3		0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF		0x0000093B
+#define MT41J128MJT125_ZQ_CFG			0x50074BE4
+#define MT41J128MJT125_DLL_LOCK_DIFF		0x1
+#define MT41J128MJT125_RATIO			0x40
+#define MT41J128MJT125_INVERT_CLKOUT		0x1
+#define MT41J128MJT125_RD_DQS			0x3B
+#define MT41J128MJT125_WR_DQS			0x85
+#define MT41J128MJT125_PHY_WR_DATA		0xC1
+#define MT41J128MJT125_PHY_FIFO_WE		0x100
+#define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
 /**
  * Configure SDRAM
@@ -189,6 +190,8 @@ struct ddr_ctrl {
 	unsigned int ddrckectrl;
 };
 
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+		const struct ddr_data *data, const struct cmd_control *ctrl,
+		const struct emif_regs *regs);
 
 #endif  /* _DDR_DEFS_H */
diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h
index 62332f2..5bd4bc8 100644
--- a/arch/arm/include/asm/arch-am33xx/hardware.h
+++ b/arch/arm/include/asm/arch-am33xx/hardware.h
@@ -61,6 +61,7 @@
 #define CM_WKUP				0x44E00400
 #define CM_DPLL				0x44E00500
 #define CM_DEVICE			0x44E00700
+#define CM_RTC				0x44E00800
 #define CM_CEFUSE			0x44E00A00
 #define PRM_DEVICE			0x44E00F00
 
@@ -83,4 +84,7 @@
 #define AM335X_CPSW_BASE		0x4A100000
 #define AM335X_CPSW_MDIO_BASE		0x4A101000
 
+/* RTC base address */
+#define AM335X_RTC_BASE			0x44E3E000
+
 #endif /* __AM33XX_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h
new file mode 100644
index 0000000..aed6b00
--- /dev/null
+++ b/arch/arm/include/asm/arch-am33xx/mux.h
@@ -0,0 +1,261 @@
+/*
+ * mux.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MUX_H_
+#define _MUX_H_
+
+#include <common.h>
+#include <asm/io.h>
+
+#define MUX_CFG(value, offset)	\
+	__raw_writel(value, (CTRL_BASE + offset));
+
+/* PAD Control Fields */
+#define SLEWCTRL	(0x1 << 6)
+#define RXACTIVE	(0x1 << 5)
+#define PULLUP_EN	(0x1 << 4) /* Pull UP Selection */
+#define PULLUDEN	(0x0 << 3) /* Pull up enabled */
+#define PULLUDDIS	(0x1 << 3) /* Pull up disabled */
+#define MODE(val)	val	/* used for Readability */
+
+/*
+ * PAD CONTROL OFFSETS
+ * Field names corresponds to the pad signal name
+ */
+struct pad_signals {
+	int gpmc_ad0;
+	int gpmc_ad1;
+	int gpmc_ad2;
+	int gpmc_ad3;
+	int gpmc_ad4;
+	int gpmc_ad5;
+	int gpmc_ad6;
+	int gpmc_ad7;
+	int gpmc_ad8;
+	int gpmc_ad9;
+	int gpmc_ad10;
+	int gpmc_ad11;
+	int gpmc_ad12;
+	int gpmc_ad13;
+	int gpmc_ad14;
+	int gpmc_ad15;
+	int gpmc_a0;
+	int gpmc_a1;
+	int gpmc_a2;
+	int gpmc_a3;
+	int gpmc_a4;
+	int gpmc_a5;
+	int gpmc_a6;
+	int gpmc_a7;
+	int gpmc_a8;
+	int gpmc_a9;
+	int gpmc_a10;
+	int gpmc_a11;
+	int gpmc_wait0;
+	int gpmc_wpn;
+	int gpmc_be1n;
+	int gpmc_csn0;
+	int gpmc_csn1;
+	int gpmc_csn2;
+	int gpmc_csn3;
+	int gpmc_clk;
+	int gpmc_advn_ale;
+	int gpmc_oen_ren;
+	int gpmc_wen;
+	int gpmc_be0n_cle;
+	int lcd_data0;
+	int lcd_data1;
+	int lcd_data2;
+	int lcd_data3;
+	int lcd_data4;
+	int lcd_data5;
+	int lcd_data6;
+	int lcd_data7;
+	int lcd_data8;
+	int lcd_data9;
+	int lcd_data10;
+	int lcd_data11;
+	int lcd_data12;
+	int lcd_data13;
+	int lcd_data14;
+	int lcd_data15;
+	int lcd_vsync;
+	int lcd_hsync;
+	int lcd_pclk;
+	int lcd_ac_bias_en;
+	int mmc0_dat3;
+	int mmc0_dat2;
+	int mmc0_dat1;
+	int mmc0_dat0;
+	int mmc0_clk;
+	int mmc0_cmd;
+	int mii1_col;
+	int mii1_crs;
+	int mii1_rxerr;
+	int mii1_txen;
+	int mii1_rxdv;
+	int mii1_txd3;
+	int mii1_txd2;
+	int mii1_txd1;
+	int mii1_txd0;
+	int mii1_txclk;
+	int mii1_rxclk;
+	int mii1_rxd3;
+	int mii1_rxd2;
+	int mii1_rxd1;
+	int mii1_rxd0;
+	int rmii1_refclk;
+	int mdio_data;
+	int mdio_clk;
+	int spi0_sclk;
+	int spi0_d0;
+	int spi0_d1;
+	int spi0_cs0;
+	int spi0_cs1;
+	int ecap0_in_pwm0_out;
+	int uart0_ctsn;
+	int uart0_rtsn;
+	int uart0_rxd;
+	int uart0_txd;
+	int uart1_ctsn;
+	int uart1_rtsn;
+	int uart1_rxd;
+	int uart1_txd;
+	int i2c0_sda;
+	int i2c0_scl;
+	int mcasp0_aclkx;
+	int mcasp0_fsx;
+	int mcasp0_axr0;
+	int mcasp0_ahclkr;
+	int mcasp0_aclkr;
+	int mcasp0_fsr;
+	int mcasp0_axr1;
+	int mcasp0_ahclkx;
+	int xdma_event_intr0;
+	int xdma_event_intr1;
+	int nresetin_out;
+	int porz;
+	int nnmi;
+	int osc0_in;
+	int osc0_out;
+	int rsvd1;
+	int tms;
+	int tdi;
+	int tdo;
+	int tck;
+	int ntrst;
+	int emu0;
+	int emu1;
+	int osc1_in;
+	int osc1_out;
+	int pmic_power_en;
+	int rtc_porz;
+	int rsvd2;
+	int ext_wakeup;
+	int enz_kaldo_1p8v;
+	int usb0_dm;
+	int usb0_dp;
+	int usb0_ce;
+	int usb0_id;
+	int usb0_vbus;
+	int usb0_drvvbus;
+	int usb1_dm;
+	int usb1_dp;
+	int usb1_ce;
+	int usb1_id;
+	int usb1_vbus;
+	int usb1_drvvbus;
+	int ddr_resetn;
+	int ddr_csn0;
+	int ddr_cke;
+	int ddr_ck;
+	int ddr_nck;
+	int ddr_casn;
+	int ddr_rasn;
+	int ddr_wen;
+	int ddr_ba0;
+	int ddr_ba1;
+	int ddr_ba2;
+	int ddr_a0;
+	int ddr_a1;
+	int ddr_a2;
+	int ddr_a3;
+	int ddr_a4;
+	int ddr_a5;
+	int ddr_a6;
+	int ddr_a7;
+	int ddr_a8;
+	int ddr_a9;
+	int ddr_a10;
+	int ddr_a11;
+	int ddr_a12;
+	int ddr_a13;
+	int ddr_a14;
+	int ddr_a15;
+	int ddr_odt;
+	int ddr_d0;
+	int ddr_d1;
+	int ddr_d2;
+	int ddr_d3;
+	int ddr_d4;
+	int ddr_d5;
+	int ddr_d6;
+	int ddr_d7;
+	int ddr_d8;
+	int ddr_d9;
+	int ddr_d10;
+	int ddr_d11;
+	int ddr_d12;
+	int ddr_d13;
+	int ddr_d14;
+	int ddr_d15;
+	int ddr_dqm0;
+	int ddr_dqm1;
+	int ddr_dqs0;
+	int ddr_dqsn0;
+	int ddr_dqs1;
+	int ddr_dqsn1;
+	int ddr_vref;
+	int ddr_vtp;
+	int ddr_strben0;
+	int ddr_strben1;
+	int ain7;
+	int ain6;
+	int ain5;
+	int ain4;
+	int ain3;
+	int ain2;
+	int ain1;
+	int ain0;
+	int vrefp;
+	int vrefn;
+};
+
+struct module_pin_mux {
+	short reg_offset;
+	unsigned char val;
+};
+
+/* Pad control register offset */
+#define PAD_CTRL_BASE	0x800
+#define OFFSET(x)	(unsigned int) (&((struct pad_signals *) \
+				(PAD_CTRL_BASE))->x)
+
+/*
+ * Configure the pin mux for the module
+ */
+void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux);
+
+#endif
diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h
index 63ed10b..644ff35 100644
--- a/arch/arm/include/asm/arch-am33xx/spl.h
+++ b/arch/arm/include/asm/arch-am33xx/spl.h
@@ -27,6 +27,7 @@
 #define BOOT_DEVICE_NAND	5
 #define BOOT_DEVICE_MMC1	8
 #define BOOT_DEVICE_MMC2	9	/* eMMC or daughter card */
+#define BOOT_DEVICE_SPI		11
 #define BOOT_DEVICE_UART	65
 #define BOOT_DEVICE_CPGMAC	70
 #define BOOT_DEVICE_MMC2_2      0xFF
diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h
index 819ea65..9cf35e0 100644
--- a/arch/arm/include/asm/arch-am33xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h
@@ -19,24 +19,6 @@
 #ifndef _SYS_PROTO_H_
 #define _SYS_PROTO_H_
 
-/*
- * AM335x parts define a system EEPROM that defines certain sub-fields.
- * We use these fields to in turn see what board we are on, and what
- * that might require us to set or not set.
- */
-#define HDR_NO_OF_MAC_ADDR	3
-#define HDR_ETH_ALEN		6
-#define HDR_NAME_LEN		8
-
-struct am335x_baseboard_id {
-	unsigned int  magic;
-	char name[HDR_NAME_LEN];
-	char version[4];
-	char serial[12];
-	char config[32];
-	char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
-};
-
 #define BOARD_REV_ID	0x0
 
 u32 get_cpu_rev(void);
@@ -51,13 +33,4 @@ u32 get_device_type(void);
 void setup_clocks_for_console(void);
 void ddr_pll_config(unsigned int ddrpll_M);
 
-/*
- * We have three pin mux functions that must exist.  We must be able to enable
- * uart0, for initial output and i2c0 to read the main EEPROM.  We then have a
- * main pinmux function that can be overridden to enable all other pinmux that
- * is required on the board.
- */
-void enable_uart0_pin_mux(void);
-void enable_i2c0_pin_mux(void);
-void enable_board_pin_mux(struct am335x_baseboard_id *header);
 #endif
diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h
index 0a357b1..0a76610 100644
--- a/arch/arm/include/asm/arch-arm720t/hardware.h
+++ b/arch/arm/include/asm/arch-arm720t/hardware.h
@@ -24,9 +24,7 @@
  * MA 02111-1307 USA
  */
 
-#if defined(CONFIG_NETARM)
-#include <asm/arch-arm720t/netarm_registers.h>
-#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
+#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
 /* include IntegratorCP/CM720T specific hardware file if there was one */
 #else
 #error No hardware file defined for this configuration
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h b/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
deleted file mode 100644
index 328eaf0..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_dma_module.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/* * include/asm-armnommu/arch-netarm/netarm_dma_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             David Smith
- */
-
-#ifndef __NETARM_DMA_MODULE_REGISTERS_H
-#define __NETARM_DMA_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define	NETARM_DMA_MODULE_BASE		(0xFF900000)
-
-#define get_dma_reg_addr(c) ((volatile unsigned int *)(NETARM_DMA_MODULE_BASE + (c)))
-
-#define	NETARM_DMA1A_BFR_DESCRPTOR_PTR	(0x00)
-#define	NETARM_DMA1A_CONTROL		(0x10)
-#define	NETARM_DMA1A_STATUS		(0x14)
-#define	NETARM_DMA1B_BFR_DESCRPTOR_PTR	(0x20)
-#define	NETARM_DMA1B_CONTROL		(0x30)
-#define	NETARM_DMA1B_STATUS		(0x34)
-#define	NETARM_DMA1C_BFR_DESCRPTOR_PTR	(0x40)
-#define	NETARM_DMA1C_CONTROL		(0x50)
-#define	NETARM_DMA1C_STATUS		(0x54)
-#define	NETARM_DMA1D_BFR_DESCRPTOR_PTR	(0x60)
-#define	NETARM_DMA1D_CONTROL		(0x70)
-#define	NETARM_DMA1D_STATUS		(0x74)
-
-#define	NETARM_DMA2_BFR_DESCRPTOR_PTR	(0x80)
-#define	NETARM_DMA2_CONTROL		(0x90)
-#define	NETARM_DMA2_STATUS		(0x94)
-
-#define	NETARM_DMA3_BFR_DESCRPTOR_PTR	(0xA0)
-#define	NETARM_DMA3_CONTROL		(0xB0)
-#define	NETARM_DMA3_STATUS		(0xB4)
-
-#define	NETARM_DMA4_BFR_DESCRPTOR_PTR	(0xC0)
-#define	NETARM_DMA4_CONTROL		(0xD0)
-#define	NETARM_DMA4_STATUS		(0xD4)
-
-#define	NETARM_DMA5_BFR_DESCRPTOR_PTR	(0xE0)
-#define	NETARM_DMA5_CONTROL		(0xF0)
-#define	NETARM_DMA5_STATUS		(0xF4)
-
-#define	NETARM_DMA6_BFR_DESCRPTOR_PTR	(0x100)
-#define	NETARM_DMA6_CONTROL		(0x110)
-#define	NETARM_DMA6_STATUS		(0x114)
-
-#define	NETARM_DMA7_BFR_DESCRPTOR_PTR	(0x120)
-#define	NETARM_DMA7_CONTROL		(0x130)
-#define	NETARM_DMA7_STATUS		(0x134)
-
-#define	NETARM_DMA8_BFR_DESCRPTOR_PTR	(0x140)
-#define	NETARM_DMA8_CONTROL		(0x150)
-#define	NETARM_DMA8_STATUS		(0x154)
-
-#define	NETARM_DMA9_BFR_DESCRPTOR_PTR	(0x160)
-#define	NETARM_DMA9_CONTROL		(0x170)
-#define	NETARM_DMA9_STATUS		(0x174)
-
-#define	NETARM_DMA10_BFR_DESCRPTOR_PTR	(0x180)
-#define	NETARM_DMA10_CONTROL		(0x190)
-#define	NETARM_DMA10_STATUS		(0x194)
-
-/* select bitfield defintions */
-
-/* DMA Control Register ( 0xFF90_0XX0 ) */
-
-#define NETARM_DMA_CTL_ENABLE		(0x80000000)
-
-#define NETARM_DMA_CTL_ABORT		(0x40000000)
-
-#define NETARM_DMA_CTL_BUS_100_PERCENT	(0x00000000)
-#define NETARM_DMA_CTL_BUS_75_PERCENT	(0x10000000)
-#define NETARM_DMA_CTL_BUS_50_PERCENT	(0x20000000)
-#define NETARM_DMA_CTL_BUS_25_PERCENT	(0x30000000)
-
-#define NETARM_DMA_CTL_BUS_MASK		(0x30000000)
-
-#define NETARM_DMA_CTL_MODE_FB_TO_MEM	(0x00000000)
-#define NETARM_DMA_CTL_MODE_FB_FROM_MEM	(0x04000000)
-#define NETARM_DMA_CTL_MODE_MEM_TO_MEM	(0x08000000)
-
-#define NETARM_DMA_CTL_BURST_NONE	(0x00000000)
-#define NETARM_DMA_CTL_BURST_8_BYTE	(0x01000000)
-#define NETARM_DMA_CTL_BURST_16_BYTE	(0x02000000)
-
-#define NETARM_DMA_CTL_BURST_MASK	(0x03000000)
-
-#define NETARM_DMA_CTL_SRC_INCREMENT	(0x00200000)
-
-#define NETARM_DMA_CTL_DST_INCREMENT	(0x00100000)
-
-/* these apply only to ext xfers on DMA 3 or 4 */
-
-#define NETARM_DMA_CTL_CH_3_4_REQ_EXT	(0x00800000)
-
-#define NETARM_DMA_CTL_CH_3_4_DATA_32	(0x00000000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_16	(0x00010000)
-#define NETARM_DMA_CTL_CH_3_4_DATA_8	(0x00020000)
-
-#define NETARM_DMA_CTL_STATE(X)	((X) & 0xFC00)
-#define NETARM_DMA_CTL_INDEX(X)	((X) & 0x03FF)
-
-/* DMA Status Register ( 0xFF90_0XX4 ) */
-
-#define NETARM_DMA_STAT_NC_INTPEN	(0x80000000)
-#define NETARM_DMA_STAT_EC_INTPEN	(0x40000000)
-#define NETARM_DMA_STAT_NR_INTPEN	(0x20000000)
-#define NETARM_DMA_STAT_CA_INTPEN	(0x10000000)
-#define NETARM_DMA_STAT_INTPEN_MASK	(0xF0000000)
-
-#define NETARM_DMA_STAT_NC_INT_EN	(0x00800000)
-#define NETARM_DMA_STAT_EC_INT_EN	(0x00400000)
-#define NETARM_DMA_STAT_NR_INT_EN	(0x00200000)
-#define NETARM_DMA_STAT_CA_INT_EN	(0x00100000)
-#define NETARM_DMA_STAT_INT_EN_MASK	(0x00F00000)
-
-#define NETARM_DMA_STAT_WRAP		(0x00080000)
-#define NETARM_DMA_STAT_IDONE		(0x00040000)
-#define NETARM_DMA_STAT_LAST		(0x00020000)
-#define NETARM_DMA_STAT_FULL		(0x00010000)
-
-#define	NETARM_DMA_STAT_BUFLEN(X)	((X) & 0x7FFF)
-
-/* DMA Buffer Descriptor Word 0 bitfields. */
-
-#define NETARM_DMA_BD0_WRAP		(0x80000000)
-#define NETARM_DMA_BD0_IDONE		(0x40000000)
-#define NETARM_DMA_BD0_LAST		(0x20000000)
-#define NETARM_DMA_BD0_BUFPTR_MASK	(0x1FFFFFFF)
-
-/* DMA Buffer Descriptor Word 1 bitfields. */
-
-#define NETARM_DMA_BD1_STATUS_MASK	(0xFFFF0000)
-#define NETARM_DMA_BD1_FULL		(0x00008000)
-#define NETARM_DMA_BD1_BUFLEN_MASK	(0x00007FFF)
-
-#ifndef	__ASSEMBLER__
-
-typedef	struct __NETARM_DMA_Buff_Desc_FlyBy
-{
-	unsigned int word0;
-	unsigned int word1;
-} NETARM_DMA_Buff_Desc_FlyBy, *pNETARM_DMA_Buff_Desc_FlyBy ;
-
-typedef	struct __NETARM_DMA_Buff_Desc_M_to_M
-{
-	unsigned int word0;
-	unsigned int word1;
-	unsigned int word2;
-	unsigned int word3;
-} NETARM_DMA_Buff_Desc_M_to_M, *pNETARM_DMA_Buff_Desc_M_to_M ;
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
deleted file mode 100644
index 317b354..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_eni_module.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eni_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : David Smith
- */
-
-#ifndef __NETARM_ENI_MODULE_REGISTERS_H
-#define __NETARM_ENI_MODULE_REGISTERS_H
-
-/* ENI unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define	NETARM_ENI_MODULE_BASE		(0xFFA00000)
-/* #endif / * CONFIG_ARCH_NETARM */
-
-#define get_eni_reg_addr(c) ((volatile unsigned int *)(NETARM_ENI_MODULE_BASE + (c)))
-#define get_eni_ctl_reg_addr(minor) \
-	(get_eni_reg_addr(NETARM_ENI_1284_PORT1_CONTROL) + (minor))
-
-#define	NETARM_ENI_GENERAL_CONTROL	(0x00)
-#define	NETARM_ENI_STATUS_CONTROL	(0x04)
-#define	NETARM_ENI_FIFO_MODE_DATA	(0x08)
-
-#define	NETARM_ENI_1284_PORT1_CONTROL	(0x10)
-#define	NETARM_ENI_1284_PORT2_CONTROL	(0x14)
-#define	NETARM_ENI_1284_PORT3_CONTROL	(0x18)
-#define	NETARM_ENI_1284_PORT4_CONTROL	(0x1c)
-
-#define	NETARM_ENI_1284_CHANNEL1_DATA	(0x20)
-#define	NETARM_ENI_1284_CHANNEL2_DATA	(0x24)
-#define	NETARM_ENI_1284_CHANNEL3_DATA	(0x28)
-#define	NETARM_ENI_1284_CHANNEL4_DATA	(0x2c)
-
-#define	NETARM_ENI_ENI_CONTROL		(0x30)
-#define	NETARM_ENI_ENI_PULSED_INTR	(0x34)
-#define	NETARM_ENI_ENI_SHARED_RAM_ADDR	(0x38)
-#define	NETARM_ENI_ENI_SHARED		(0x3c)
-
-/* select bitfield defintions */
-
-/* General Control Register (0xFFA0_0000) */
-
-#define NETARM_ENI_GCR_ENIMODE_IEEE1284	(0x00000001)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM16	(0x00000004)
-#define NETARM_ENI_GCR_ENIMODE_SHRAM8	(0x00000005)
-#define NETARM_ENI_GCR_ENIMODE_FIFO16	(0x00000006)
-#define NETARM_ENI_GCR_ENIMODE_FIFO8	(0x00000007)
-
-#define NETARM_ENI_GCR_ENIMODE_MASK	(0x00000007)
-
-/* IEEE 1284 Port Control Registers 1-4 (0xFFA0_0010, 0xFFA0_0014,
-   0xFFA0_0018, 0xFFA0_001c) */
-
-#define NETARM_ENI_1284PC_PORT_ENABLE	(0x80000000)
-#define NETARM_ENI_1284PC_DMA_ENABLE	(0x40000000)
-#define NETARM_ENI_1284PC_OBE_INT_EN	(0x20000000)
-#define NETARM_ENI_1284PC_ACK_INT_EN	(0x10000000)
-#define NETARM_ENI_1284PC_ECP_MODE	(0x08000000)
-#define NETARM_ENI_1284PC_LOOPBACK_MODE	(0x04000000)
-
-#define NETARM_ENI_1284PC_STROBE_TIME0	(0x00000000) /* 0.5 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME1	(0x01000000) /* 1.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME2	(0x02000000) /* 5.0 uS */
-#define NETARM_ENI_1284PC_STROBE_TIME3	(0x03000000) /* 10.0 uS */
-#define NETARM_ENI_1284PC_STROBE_MASK	(0x03000000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE_EN	(0x00800000)
-#define NETARM_ENI_1284PC_FAST_MODE	(0x00400000)
-#define NETARM_ENI_1284PC_BIDIR_MODE	(0x00200000)
-
-#define NETARM_ENI_1284PC_MAN_STROBE	(0x00080000)
-#define NETARM_ENI_1284PC_AUTO_FEED	(0x00040000)
-#define NETARM_ENI_1284PC_INIT		(0x00020000)
-#define NETARM_ENI_1284PC_HSELECT	(0x00010000)
-#define NETARM_ENI_1284PC_FE_INT_EN	(0x00008000)
-#define NETARM_ENI_1284PC_EPP_MODE	(0x00004000)
-#define NETARM_ENI_1284PC_IBR_INT_EN	(0x00002000)
-#define NETARM_ENI_1284PC_IBR		(0x00001000)
-
-#define NETARM_ENI_1284PC_RXFDB_1BYTE	(0x00000400)
-#define NETARM_ENI_1284PC_RXFDB_2BYTE	(0x00000800)
-#define NETARM_ENI_1284PC_RXFDB_3BYTE	(0x00000c00)
-#define NETARM_ENI_1284PC_RXFDB_4BYTE	(0x00000000)
-
-#define NETARM_ENI_1284PC_RBCC		(0x00000200)
-#define NETARM_ENI_1284PC_RBCT		(0x00000100)
-#define NETARM_ENI_1284PC_ACK		(0x00000080)
-#define NETARM_ENI_1284PC_FIFO_E	(0x00000040)
-#define NETARM_ENI_1284PC_OBE		(0x00000020)
-#define NETARM_ENI_1284PC_ACK_INT	(0x00000010)
-#define NETARM_ENI_1284PC_BUSY		(0x00000008)
-#define NETARM_ENI_1284PC_PE		(0x00000004)
-#define NETARM_ENI_1284PC_PSELECT	(0x00000002)
-#define NETARM_ENI_1284PC_FAULT		(0x00000001)
-
-#endif /* __NETARM_ENI_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h b/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
deleted file mode 100644
index 8f2f369..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_eth_module.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_eth_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Jackie Smith Cashion
- *             David Smith
- */
-
-#ifndef __NETARM_ETH_MODULE_REGISTERS_H
-#define __NETARM_ETH_MODULE_REGISTERS_H
-
-/* ETH unit register offsets */
-
-#define	NETARM_ETH_MODULE_BASE		(0xFF800000)
-
-#define get_eth_reg_addr(c) ((volatile unsigned int *)(NETARM_ETH_MODULE_BASE + (c)))
-
-#define NETARM_ETH_GEN_CTRL		(0x000) /* Ethernet Gen Control Reg */
-#define NETARM_ETH_GEN_STAT		(0x004) /* Ethernet Gen Status Reg */
-#define NETARM_ETH_FIFO_DAT1            (0x008) /* Fifo Data Reg 1 */
-#define NETARM_ETH_FIFO_DAT2            (0x00C) /* Fifo Data Reg 2 */
-#define NETARM_ETH_TX_STAT              (0x010) /* Transmit Status Reg */
-#define NETARM_ETH_RX_STAT              (0x014) /* Receive Status Reg */
-
-#define NETARM_ETH_MAC_CFG		(0x400) /* MAC Configuration Reg */
-#define NETARM_ETH_PCS_CFG		(0x408) /* PCS Configuration Reg */
-#define NETARM_ETH_STL_CFG		(0x410) /* STL Configuration Reg */
-#define NETARM_ETH_B2B_IPG_GAP_TMR	(0x440) /* Back-to-back IPG
-						   Gap Timer Reg */
-#define NETARM_ETH_NB2B_IPG_GAP_TMR	(0x444) /* Non Back-to-back
-						   IPG Gap Timer Reg */
-#define NETARM_ETH_MII_CMD		(0x540) /* MII (PHY) Command Reg */
-#define NETARM_ETH_MII_ADDR		(0x544) /* MII Address Reg */
-#define NETARM_ETH_MII_WRITE		(0x548) /* MII Write Data Reg */
-#define NETARM_ETH_MII_READ		(0x54C) /* MII Read Data Reg */
-#define NETARM_ETH_MII_IND		(0x550) /* MII Indicators Reg */
-#define NETARM_ETH_MIB_CRCEC		(0x580) /* (MIB) CRC Error Counter */
-#define NETARM_ETH_MIB_AEC		(0x584) /* Alignment Error Counter */
-#define NETARM_ETH_MIB_CEC		(0x588) /* Code Error Counter */
-#define NETARM_ETH_MIB_LFC		(0x58C) /* Long Frame Counter */
-#define NETARM_ETH_MIB_SFC		(0x590) /* Short Frame Counter */
-#define NETARM_ETH_MIB_LCC		(0x594) /* Late Collision Counter */
-#define NETARM_ETH_MIB_EDC		(0x598) /* Excessive Deferral
-						   Counter */
-#define NETARM_ETH_MIB_MCC		(0x59C) /* Maximum Collision Counter */
-#define NETARM_ETH_SAL_FILTER		(0x5C0) /* SAL Station Address
-						   Filter Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_1	(0x5C4) /* SAL Station Address
-						   Reg */
-#define NETARM_ETH_SAL_STATION_ADDR_2	(0x5C8)
-#define NETARM_ETH_SAL_STATION_ADDR_3	(0x5CC)
-#define NETARM_ETH_SAL_HASH_TBL_1	(0x5D0) /* SAL Multicast Hash Table*/
-#define NETARM_ETH_SAL_HASH_TBL_2	(0x5D4)
-#define NETARM_ETH_SAL_HASH_TBL_3	(0x5D8)
-#define NETARM_ETH_SAL_HASH_TBL_4	(0x5DC)
-
-/* select bitfield defintions */
-
-/* Ethernet General Control Register (0xFF80_0000) */
-
-#define NETARM_ETH_GCR_ERX		(0x80000000) /* Enable Receive FIFO */
-#define NETARM_ETH_GCR_ERXDMA		(0x40000000) /* Enable Receive DMA */
-#define NETARM_ETH_GCR_ETX		(0x00800000) /* Enable Transmit FIFO */
-#define NETARM_ETH_GCR_ETXDMA		(0x00400000) /* Enable Transmit DMA */
-#define NETARM_ETH_GCR_ETXWM_50		(0x00100000) /* Transmit FIFO Water
-							Mark.  Start transmit
-							when FIFO is 50%
-							full. */
-#define NETARM_ETH_GCR_PNA		(0x00000400) /* pSOS pNA Buffer
-							Descriptor Format */
-
-/* Ethernet General Status Register (0xFF80_0004) */
-
-#define NETARM_ETH_GST_RXFDB            (0x30000000)
-#define NETARM_ETH_GST_RXREGR		(0x08000000) /* Receive Register
-							Ready */
-#define NETARM_ETH_GST_RXFIFOH		(0x04000000)
-#define NETARM_ETH_GST_RXBR		(0x02000000)
-#define NETARM_ETH_GST_RXSKIP		(0x01000000)
-
-#define NETARM_ETH_GST_TXBC             (0x00020000)
-
-
-/* Ethernet Transmit Status Register (0xFF80_0010) */
-
-#define NETARM_ETH_TXSTAT_TXOK          (0x00008000)
-
-
-/* Ethernet Receive Status Register (0xFF80_0014) */
-
-#define NETARM_ETH_RXSTAT_SIZE          (0xFFFF0000)
-#define NETARM_ETH_RXSTAT_RXOK          (0x00002000)
-
-
-/* PCS Configuration Register (0xFF80_0408) */
-
-#define NETARM_ETH_PCSC_NOCFR		(0x1) /* Disable Ciphering */
-#define NETARM_ETH_PCSC_ENJAB		(0x2) /* Enable Jabber Protection */
-#define NETARM_ETH_PCSC_CLKS_25M	(0x0) /* 25 MHz Clock Speed Select */
-#define NETARM_ETH_PCSC_CLKS_33M	(0x4) /* 33 MHz Clock Speed Select */
-
-/* STL Configuration Register (0xFF80_0410) */
-
-#define NETARM_ETH_STLC_RXEN		(0x2) /* Enable Packet Receiver */
-#define NETARM_ETH_STLC_AUTOZ		(0x4) /* Auto Zero Statistics */
-
-/* MAC Configuration Register (0xFF80_0400) */
-
-#define NETARM_ETH_MACC_HUGEN		(0x1) /* Enable Unlimited Transmit
-						 Frame Sizes */
-#define NETARM_ETH_MACC_PADEN		(0x4) /* Automatic Pad Fill Frames
-						 to 64 Bytes */
-#define NETARM_ETH_MACC_CRCEN		(0x8) /* Append CRC to Transmit
-						 Frames */
-
-/* MII (PHY) Command Register (0xFF80_0540) */
-
-#define NETARM_ETH_MIIC_RSTAT		(0x1) /* Single Scan for Read Data */
-
-/* MII Indicators Register (0xFF80_0550) */
-
-#define NETARM_ETH_MIII_BUSY		(0x1) /* MII I/F Busy with
-						 Read/Write */
-
-/* SAL Station Address Filter Register (0xFF80_05C0) */
-
-#define NETARM_ETH_SALF_PRO		(0x8) /* Enable Promiscuous Mode */
-#define NETARM_ETH_SALF_PRM		(0x4) /* Accept All Multicast
-						 Packets */
-#define NETARM_ETH_SALF_PRA		(0x2) /* Accept Mulitcast Packets
-						 using Hash Table */
-#define NETARM_ETH_SALF_BROAD		(0x1) /* Accept All Broadcast
-						 Packets */
-
-
-#endif /* __NETARM_GEN_MODULE_REGISTERS_H */
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h b/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
deleted file mode 100644
index 13656a3..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_gen_module.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_gen_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_GEN_MODULE_REGISTERS_H
-#define __NETARM_GEN_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define NETARM_GEN_MODULE_BASE		(0xFFB00000)
-
-#define get_gen_reg_addr(c) ((volatile unsigned int *)(NETARM_GEN_MODULE_BASE + (c)))
-
-#define NETARM_GEN_SYSTEM_CONTROL	(0x00)
-#define NETARM_GEN_STATUS_CONTROL	(0x04)
-#define NETARM_GEN_PLL_CONTROL		(0x08)
-#define NETARM_GEN_SOFTWARE_SERVICE	(0x0c)
-
-#define NETARM_GEN_TIMER1_CONTROL	(0x10)
-#define NETARM_GEN_TIMER1_STATUS	(0x14)
-#define NETARM_GEN_TIMER2_CONTROL	(0x18)
-#define NETARM_GEN_TIMER2_STATUS	(0x1c)
-
-#define NETARM_GEN_PORTA		(0x20)
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORTB		(0x24)
-#endif
-#define NETARM_GEN_PORTC		(0x28)
-
-#define NETARM_GEN_INTR_ENABLE		(0x30)
-#define NETARM_GEN_INTR_ENABLE_SET	(0x34)
-#define NETARM_GEN_INTR_ENABLE_CLR	(0x38)
-#define NETARM_GEN_INTR_STATUS_EN	(0x34)
-#define NETARM_GEN_INTR_STATUS_RAW	(0x38)
-
-#define NETARM_GEN_CACHE_CONTROL1	(0x40)
-#define NETARM_GEN_CACHE_CONTROL2	(0x44)
-
-/* select bitfield definitions */
-
-/* System Control Register ( 0xFFB0_0000 ) */
-
-#define NETARM_GEN_SYS_CFG_LENDIAN	(0x80000000)
-#define NETARM_GEN_SYS_CFG_BENDIAN	(0x00000000)
-
-#define NETARM_GEN_SYS_CFG_BUSQRTR	(0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSHALF	(0x20000000)
-#define NETARM_GEN_SYS_CFG_BUSFULL	(0x40000000)
-
-#define NETARM_GEN_SYS_CFG_BCLK_DISABLE (0x10000000)
-
-#define NETARM_GEN_SYS_CFG_WDOG_EN	(0x01000000)
-#define NETARM_GEN_SYS_CFG_WDOG_IRQ	(0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_FIQ	(0x00400000)
-#define NETARM_GEN_SYS_CFG_WDOG_RST	(0x00800000)
-#define NETARM_GEN_SYS_CFG_WDOG_24	(0x00000000)
-#define NETARM_GEN_SYS_CFG_WDOG_26	(0x00100000)
-#define NETARM_GEN_SYS_CFG_WDOG_28	(0x00200000)
-#define NETARM_GEN_SYS_CFG_WDOG_29	(0x00300000)
-
-#define NETARM_GEN_SYS_CFG_BUSMON_EN	(0x00040000)
-#define NETARM_GEN_SYS_CFG_BUSMON_128	(0x00000000)
-#define NETARM_GEN_SYS_CFG_BUSMON_64	(0x00010000)
-#define NETARM_GEN_SYS_CFG_BUSMON_32	(0x00020000)
-#define NETARM_GEN_SYS_CFG_BUSMON_16	(0x00030000)
-
-#define NETARM_GEN_SYS_CFG_USER_EN	(0x00008000)
-#define NETARM_GEN_SYS_CFG_BUSER_EN	(0x00004000)
-
-#define NETARM_GEN_SYS_CFG_BUSARB_INT	(0x00002000)
-#define NETARM_GEN_SYS_CFG_BUSARB_EXT	(0x00000000)
-
-#define NETARM_GEN_SYS_CFG_DMATST	(0x00001000)
-
-#define NETARM_GEN_SYS_CFG_TEALAST	(0x00000800)
-
-#define NETARM_GEN_SYS_CFG_ALIGN_ABORT	(0x00000400)
-
-#define NETARM_GEN_SYS_CFG_CACHE_EN	(0x00000200)
-
-#define NETARM_GEN_SYS_CFG_WRI_BUF_EN	(0x00000100)
-
-#define NETARM_GEN_SYS_CFG_CACHE_INIT	(0x00000080)
-
-/* PLL Control Register ( 0xFFB0_0008 ) */
-
-#define NETARM_GEN_PLL_CTL_PLLCNT_MASK	(0x0F000000)
-
-#define NETARM_GEN_PLL_CTL_PLLCNT(x)	(((x)<<24) & \
-					 NETARM_GEN_PLL_CTL_PLLCNT_MASK)
-
-/* Defaults for POLTST and ICP Fields in PLL CTL */
-#define NETARM_GEN_PLL_CTL_OUTDIV(x)	(x)
-#define NETARM_GEN_PLL_CTL_INDIV(x)	((x)<<6)
-#define NETARM_GEN_PLL_CTL_POLTST_DEF	(0x00000E00)
-#define NETARM_GEN_PLL_CTL_ICP_DEF	(0x0000003C)
-
-
-/* Software Service Register ( 0xFFB0_000C ) */
-
-#define NETARM_GEN_SW_SVC_RESETA	(0x123)
-#define NETARM_GEN_SW_SVC_RESETB	(0x321)
-
-/* PORT C Register ( 0xFFB0_0028 ) */
-
-#ifndef CONFIG_NETARM_NS7520
-#define NETARM_GEN_PORT_MODE(x)		(((x)<<24) + (0xFF00))
-#define NETARM_GEN_PORT_DIR(x)		(((x)<<16) + (0xFF00))
-#else
-#define NETARM_GEN_PORT_MODE(x)		((x)<<24)
-#define NETARM_GEN_PORT_DIR(x)		((x)<<16)
-#define NETARM_GEN_PORT_CSF(x)		((x)<<8)
-#endif
-
-/* Timer Registers ( 0xFFB0_0010 0xFFB0_0018 ) */
-
-#define NETARM_GEN_TCTL_ENABLE		(0x80000000)
-#define NETARM_GEN_TCTL_INT_ENABLE	(0x40000000)
-
-#define NETARM_GEN_TCTL_USE_IRQ		(0x00000000)
-#define NETARM_GEN_TCTL_USE_FIQ		(0x20000000)
-
-#define NETARM_GEN_TCTL_USE_PRESCALE	(0x10000000)
-#define NETARM_GEN_TCTL_INIT_COUNT(x)	((x) & 0x1FF)
-
-#define NETARM_GEN_TSTAT_INTPEN		(0x40000000)
-#if ~defined(CONFIG_NETARM_NS7520)
-#define NETARM_GEN_TSTAT_CTC_MASK	(0x000001FF)
-#else
-#define NETARM_GEN_TSTAT_CTC_MASK	(0x0FFFFFFF)
-#endif
-
-/* prescale to msecs conversion */
-
-#if !defined(CONFIG_NETARM_PLL_BYPASS)
-#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 20480 ) * ( 0x1FF - ( (x) &	    \
-					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
-					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(20480*(x)))-1) & \
-					  NETARM_GEN_TSTAT_CTC_MASK ) | \
-					  NETARM_GEN_TCTL_USE_PRESCALE )
-
-#else
-#define NETARM_GEN_TIMER_MSEC_P(x)	( ( ( 4096 ) * ( 0x1FF - ( (x) &    \
-					    NETARM_GEN_TSTAT_CTC_MASK ) +   \
-					    1 ) ) / (NETARM_XTAL_FREQ/1000) )
-
-#define NETARM_GEN_TIMER_SET_HZ(x)	( ( ((NETARM_XTAL_FREQ/(4096*(x)))-1) & \
-					  NETARM_GEN_TSTAT_CTC_MASK ) | \
-					  NETARM_GEN_TCTL_USE_PRESCALE )
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h b/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
deleted file mode 100644
index c650c3b..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_mem_module.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * include/asm-armnommu/arch-netarm/netarm_mem_module.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NETARM_MEM_MODULE_REGISTERS_H
-#define __NETARM_MEM_MODULE_REGISTERS_H
-
-/* GEN unit register offsets */
-
-#define	NETARM_MEM_MODULE_BASE		(0xFFC00000)
-
-#define	NETARM_MEM_MODULE_CONFIG	(0x00)
-#define	NETARM_MEM_CS0_BASE_ADDR	(0x10)
-#define	NETARM_MEM_CS0_OPTIONS		(0x14)
-#define	NETARM_MEM_CS1_BASE_ADDR	(0x20)
-#define	NETARM_MEM_CS1_OPTIONS		(0x24)
-#define	NETARM_MEM_CS2_BASE_ADDR	(0x30)
-#define	NETARM_MEM_CS2_OPTIONS		(0x34)
-#define	NETARM_MEM_CS3_BASE_ADDR	(0x40)
-#define	NETARM_MEM_CS3_OPTIONS		(0x44)
-#define	NETARM_MEM_CS4_BASE_ADDR	(0x50)
-#define	NETARM_MEM_CS4_OPTIONS		(0x54)
-
-/* select bitfield defintions */
-
-/* Module Configuration Register ( 0xFFC0_0000 ) */
-
-#define NETARM_MEM_CFG_REFR_COUNT_MASK	(0xFF000000)
-#define NETARM_MEM_CFG_REFRESH_EN	(0x00800000)
-
-#define NETARM_MEM_CFG_REFR_CYCLE_8CLKS	(0x00000000)
-#define NETARM_MEM_CFG_REFR_CYCLE_6CLKS	(0x00200000)
-#define NETARM_MEM_CFG_REFR_CYCLE_5CLKS	(0x00400000)
-#define NETARM_MEM_CFG_REFR_CYCLE_4CLKS	(0x00600000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX	(0x00100000)
-
-#define NETARM_MEM_CFG_A27_ADDR		(0x00080000)
-#define NETARM_MEM_CFG_A27_CS0OE	(0x00000000)
-
-#define NETARM_MEM_CFG_A26_ADDR		(0x00040000)
-#define NETARM_MEM_CFG_A26_CS0WE	(0x00000000)
-
-#define NETARM_MEM_CFG_A25_ADDR		(0x00020000)
-#define NETARM_MEM_CFG_A25_BLAST	(0x00000000)
-
-#define NETARM_MEM_CFG_PORTC_AMUX2	(0x00010000)
-
-
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock)   */
-/* the expression will round down, so make sure to reverse it to verify */
-/* it is what you want. period = [( count + 1 ) * 20] / Fcrystal        */
-/* (note: Fxtal = Fcrystal/5, see HWRefGuide sections 8.2.5 and 11.3.2) */
-
-#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
-					 (((((NETARM_XTAL_FREQ/(1000))*p)/(20000) \
-					    ) - (1) ) << (24)))
-
-#if 0
-/* range on this period is about 1 to 275 usec (with 18.432MHz clock) */
-/* the expression will round down, so make sure to reverse it toverify */
-/* it is what you want. period = [( count + 1 ) * 4] / Fxtal          */
-
-#define	NETARM_MEM_REFR_PERIOD_USEC(p)	(NETARM_MEM_CFG_REFR_COUNT_MASK & \
-					 (((((NETARM_XTAL_FREQ/(1000))*p)/(4000) \
-					    ) - (1) ) << (24)))
-#endif
-
-/* Base Address Registers (0xFFC0_00X0) */
-
-#define NETARM_MEM_BAR_BASE_MASK	(0xFFFFF000)
-
-/* macro to define base */
-
-#define NETARM_MEM_BAR_BASE(x)		((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_BAR_DRAM_FP		(0x00000000)
-#define NETARM_MEM_BAR_DRAM_EDO		(0x00000100)
-#define NETARM_MEM_BAR_DRAM_SYNC	(0x00000200)
-
-#define NETARM_MEM_BAR_DRAM_MUX_INT	(0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_EXT	(0x00000080)
-
-#define NETARM_MEM_BAR_DRAM_MUX_BAL	(0x00000000)
-#define NETARM_MEM_BAR_DRAM_MUX_UNBAL	(0x00000020)
-
-#define NETARM_MEM_BAR_1BCLK_IDLE	(0x00000010)
-
-#define NETARM_MEM_BAR_DRAM_SEL		(0x00000008)
-
-#define NETARM_MEM_BAR_BURST_EN		(0x00000004)
-
-#define NETARM_MEM_BAR_WRT_PROT		(0x00000002)
-
-#define NETARM_MEM_BAR_VALID		(0x00000001)
-
-/* Option Registers (0xFFC0_00X4) */
-
-/* macro to define which bits of the base are significant */
-
-#define NETARM_MEM_OPT_BASE_USE(x)	((x) & NETARM_MEM_BAR_BASE_MASK)
-
-#define NETARM_MEM_OPT_WAIT_MASK	(0x00000F00)
-
-#define	NETARM_MEM_OPT_WAIT_STATES(x)	(((x) << 8 ) & NETARM_MEM_OPT_WAIT_MASK )
-
-#define NETARM_MEM_OPT_BCYC_1		(0x00000000)
-#define NETARM_MEM_OPT_BCYC_2		(0x00000040)
-#define NETARM_MEM_OPT_BCYC_3		(0x00000080)
-#define NETARM_MEM_OPT_BCYC_4		(0x000000C0)
-
-#define NETARM_MEM_OPT_BSIZE_2		(0x00000000)
-#define NETARM_MEM_OPT_BSIZE_4		(0x00000010)
-#define NETARM_MEM_OPT_BSIZE_8		(0x00000020)
-#define NETARM_MEM_OPT_BSIZE_16		(0x00000030)
-
-#define NETARM_MEM_OPT_32BIT		(0x00000000)
-#define NETARM_MEM_OPT_16BIT		(0x00000004)
-#define NETARM_MEM_OPT_8BIT		(0x00000008)
-#define NETARM_MEM_OPT_32BIT_EXT_ACK	(0x0000000C)
-
-#define NETARM_MEM_OPT_BUS_SIZE_MASK	(0x0000000C)
-
-#define NETARM_MEM_OPT_READ_ASYNC	(0x00000000)
-#define NETARM_MEM_OPT_READ_SYNC	(0x00000002)
-
-#define NETARM_MEM_OPT_WRITE_ASYNC	(0x00000000)
-#define NETARM_MEM_OPT_WRITE_SYNC	(0x00000001)
-
-#ifdef CONFIG_NETARM_NS7520
-/* The NS7520 has a second options register for each chip select */
-#define	NETARM_MEM_CS0_OPTIONS_B  (0x18)
-#define	NETARM_MEM_CS1_OPTIONS_B  (0x28)
-#define	NETARM_MEM_CS2_OPTIONS_B  (0x38)
-#define	NETARM_MEM_CS3_OPTIONS_B  (0x48)
-#define	NETARM_MEM_CS4_OPTIONS_B  (0x58)
-
-/* Option B Registers (0xFFC0_00x8) */
-#define NETARM_MEM_OPTB_SYNC_1_STAGE	(0x00000001)
-#define NETARM_MEM_OPTB_SYNC_2_STAGE	(0x00000002)
-#define NETARM_MEM_OPTB_BCYC_PLUS0	(0x00000000)
-#define NETARM_MEM_OPTB_BCYC_PLUS4	(0x00000004)
-#define NETARM_MEM_OPTB_BCYC_PLUS8	(0x00000008)
-#define NETARM_MEM_OPTB_BCYC_PLUS12	(0x0000000C)
-
-#define NETARM_MEM_OPTB_WAIT_PLUS0	(0x00000000)
-#define NETARM_MEM_OPTB_WAIT_PLUS16	(0x00000010)
-#define NETARM_MEM_OPTB_WAIT_PLUS32	(0x00000020)
-#define NETARM_MEM_OPTB_WAIT_PLUS48	(0x00000030)
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_registers.h b/arch/arm/include/asm/arch-arm720t/netarm_registers.h
deleted file mode 100644
index fa88128..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_registers.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_registers.h
- *
- * Copyright (C) 2005
- * Art Shipkowski, Videon Central, Inc., <art@videon-central.com>
- *
- * Copyright (C) 2000, 2001 NETsilicon, Inc.
- * Copyright (C) 2000, 2001 WireSpeed Communications Corporation
- *
- * This software is copyrighted by WireSpeed. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall WireSpeed
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *
- * Modified to support NS7520 by Art Shipkowski.
- */
-
-#ifndef __NET_ARM_REGISTERS_H
-#define __NET_ARM_REGISTERS_H
-
-#include <config.h>
-
-/* fundamental constants : */
-/* the input crystal/clock frequency ( in Hz ) */
-#define	NETARM_XTAL_FREQ_25MHz		(18432000)
-#define	NETARM_XTAL_FREQ_33MHz		(23698000)
-#define	NETARM_XTAL_FREQ_48MHz		(48000000)
-#define	NETARM_XTAL_FREQ_55MHz		(55000000)
-#define NETARM_XTAL_FREQ_EMLIN1		(20000000)
-
-/* the frequency of SYS_CLK */
-#if defined(CONFIG_NETARM_EMLIN)
-
-/* EMLIN board:  33 MHz (exp.) */
-#define	NETARM_PLL_COUNT_VAL		6
-#define NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV2)
-
-/* NET+40 Rev2 boards:  33 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define	NETARM_PLL_COUNT_VAL		6
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET40_REV4)
-
-/* NET+40 Rev4 boards with EDO must clock slower: 25 MHz (with
-   NETARM_XTAL_FREQ_25MHz) 4 */
-#define	NETARM_PLL_COUNT_VAL		4
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#elif defined(CONFIG_NETARM_NET50)
-
-/* NET+50 boards:  40 MHz (with NETARM_XTAL_FREQ_25MHz) */
-#define NETARM_PLL_COUNT_VAL		8
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_25MHz
-
-#else	/* CONFIG_NETARM_NS7520 */
-
-#define	NETARM_PLL_COUNT_VAL		0
-
-#if defined(CONFIG_BOARD_UNC20)
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_48MHz
-#else
-#define	NETARM_XTAL_FREQ		NETARM_XTAL_FREQ_55MHz
-#endif
-
-#endif
-
-/* #include "arm_registers.h" */
-#include <asm/arch/netarm_gen_module.h>
-#include <asm/arch/netarm_mem_module.h>
-#include <asm/arch/netarm_ser_module.h>
-#include <asm/arch/netarm_eni_module.h>
-#include <asm/arch/netarm_dma_module.h>
-#include <asm/arch/netarm_eth_module.h>
-
-#endif
diff --git a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h b/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
deleted file mode 100644
index 6fbae11..0000000
--- a/arch/arm/include/asm/arch-arm720t/netarm_ser_module.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/*
- * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
- *
- * Copyright (C) 2000 NETsilicon, Inc.
- * Copyright (C) 2000 Red Hat, Inc.
- *
- * This software is copyrighted by Red Hat. LICENSEE agrees that
- * it will not delete this copyright notice, trademarks or protective
- * notices from any copy made by LICENSEE.
- *
- * This software is provided "AS-IS" and any express or implied
- * warranties or conditions, including but not limited to any
- * implied warranties of merchantability and fitness for a particular
- * purpose regarding this software. In no event shall Red Hat
- * be liable for any indirect, consequential, or incidental damages,
- * loss of profits or revenue, loss of use or data, or interruption
- * of business, whether the alleged damages are labeled in contract,
- * tort, or indemnity.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * author(s) : Joe deBlaquiere
- *             Clark Williams
- */
-
-#ifndef __NETARM_SER_MODULE_REGISTERS_H
-#define __NETARM_SER_MODULE_REGISTERS_H
-
-#ifndef	__ASSEMBLER__
-
-/* (--sub)#include "types.h" */
-
-/* serial channel control structure */
-typedef struct {
-  u32	ctrl_a;
-  u32	ctrl_b;
-  u32	status_a;
-  u32	bitrate;
-  u32	fifo;
-  u32	rx_buf_timer;
-  u32	rx_char_timer;
-  u32	rx_match;
-  u32	rx_match_mask;
-  u32	ctrl_c;
-  u32	status_b;
-  u32	status_c;
-  u32	fifo_last;
-  u32	unused[3];
-} netarm_serial_channel_t;
-
-#endif
-
-/* SER unit register offsets */
-
-/* #ifdef CONFIG_ARCH_NETARM */
-#define	NETARM_SER_MODULE_BASE		(0xFFD00000)
-/* #else */
-/* extern serial_channel_t netarm_dummy_registers[]; */
-/* #define NETARM_SER_MODULE_BASE		(netarm_dummy_registers) */
-/* #ifndef NETARM_XTAL_FREQ */
-/* #define NETARM_XTAL_FREQ                18432000 */
-/* #endif */
-/* #endif */
-
-/* calculate the sysclk value from the pll setting */
-#define	NETARM_PLLED_SYSCLK_FREQ	(( NETARM_XTAL_FREQ / 5 ) * \
-					 ( NETARM_PLL_COUNT_VAL + 3 ))
-
-#define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
-
-#define	NETARM_SER_CH1_CTRL_A		(0x00)
-#define	NETARM_SER_CH1_CTRL_B		(0x04)
-#define	NETARM_SER_CH1_STATUS_A		(0x08)
-#define	NETARM_SER_CH1_BITRATE		(0x0C)
-#define	NETARM_SER_CH1_FIFO		(0x10)
-#define	NETARM_SER_CH1_RX_BUF_TMR	(0x14)
-#define	NETARM_SER_CH1_RX_CHAR_TMR	(0x18)
-#define	NETARM_SER_CH1_RX_MATCH		(0x1c)
-#define	NETARM_SER_CH1_RX_MATCH_MASK	(0x20)
-#define	NETARM_SER_CH1_CTRL_C		(0x24)
-#define	NETARM_SER_CH1_STATUS_B		(0x28)
-#define	NETARM_SER_CH1_STATUS_C		(0x2c)
-#define	NETARM_SER_CH1_FIFO_LAST	(0x30)
-
-#define	NETARM_SER_CH2_CTRL_A		(0x40)
-#define	NETARM_SER_CH2_CTRL_B		(0x44)
-#define	NETARM_SER_CH2_STATUS_A		(0x48)
-#define	NETARM_SER_CH2_BITRATE		(0x4C)
-#define	NETARM_SER_CH2_FIFO		(0x50)
-#define	NETARM_SER_CH2_RX_BUF_TMR	(0x54)
-#define	NETARM_SER_CH2_RX_CHAR_TMR	(0x58)
-#define	NETARM_SER_CH2_RX_MATCH		(0x5c)
-#define	NETARM_SER_CH2_RX_MATCH_MASK	(0x60)
-#define	NETARM_SER_CH2_CTRL_C		(0x64)
-#define	NETARM_SER_CH2_STATUS_B		(0x68)
-#define	NETARM_SER_CH2_STATUS_C		(0x6c)
-#define	NETARM_SER_CH2_FIFO_LAST	(0x70)
-
-/* select bitfield defintions */
-
-/* Control Register A */
-
-#define	NETARM_SER_CTLA_ENABLE		(0x80000000)
-#define	NETARM_SER_CTLA_BRK		(0x40000000)
-
-#define	NETARM_SER_CTLA_STICKP		(0x20000000)
-
-#define	NETARM_SER_CTLA_P_EVEN		(0x18000000)
-#define	NETARM_SER_CTLA_P_ODD		(0x08000000)
-#define	NETARM_SER_CTLA_P_NONE		(0x00000000)
-
-/* if you read the errata, you will find that the STOP bits don't work right */
-#define	NETARM_SER_CTLA_2STOP		(0x00000000)
-#define	NETARM_SER_CTLA_3STOP		(0x04000000)
-
-#define	NETARM_SER_CTLA_5BITS		(0x00000000)
-#define	NETARM_SER_CTLA_6BITS		(0x01000000)
-#define	NETARM_SER_CTLA_7BITS		(0x02000000)
-#define	NETARM_SER_CTLA_8BITS		(0x03000000)
-
-#define	NETARM_SER_CTLA_CTSTX		(0x00800000)
-#define	NETARM_SER_CTLA_RTSRX		(0x00400000)
-
-#define	NETARM_SER_CTLA_LOOP_REM	(0x00200000)
-#define	NETARM_SER_CTLA_LOOP_LOC	(0x00100000)
-
-#define	NETARM_SER_CTLA_GPIO2		(0x00080000)
-#define	NETARM_SER_CTLA_GPIO1		(0x00040000)
-
-#define	NETARM_SER_CTLA_DTR_EN		(0x00020000)
-#define	NETARM_SER_CTLA_RTS_EN		(0x00010000)
-
-#define	NETARM_SER_CTLA_IE_RX_BRK	(0x00008000)
-#define	NETARM_SER_CTLA_IE_RX_FRMERR	(0x00004000)
-#define	NETARM_SER_CTLA_IE_RX_PARERR	(0x00002000)
-#define	NETARM_SER_CTLA_IE_RX_OVERRUN	(0x00001000)
-#define	NETARM_SER_CTLA_IE_RX_RDY	(0x00000800)
-#define	NETARM_SER_CTLA_IE_RX_HALF	(0x00000400)
-#define	NETARM_SER_CTLA_IE_RX_FULL	(0x00000200)
-#define	NETARM_SER_CTLA_IE_RX_DMAEN	(0x00000100)
-#define	NETARM_SER_CTLA_IE_RX_DCD	(0x00000080)
-#define	NETARM_SER_CTLA_IE_RX_RI	(0x00000040)
-#define	NETARM_SER_CTLA_IE_RX_DSR	(0x00000020)
-
-#define NETARM_SER_CTLA_IE_RX_ALL	(NETARM_SER_CTLA_IE_RX_BRK \
-					|NETARM_SER_CTLA_IE_RX_FRMERR \
-					|NETARM_SER_CTLA_IE_RX_PARERR \
-					|NETARM_SER_CTLA_IE_RX_OVERRUN \
-					|NETARM_SER_CTLA_IE_RX_RDY \
-					|NETARM_SER_CTLA_IE_RX_HALF \
-					|NETARM_SER_CTLA_IE_RX_FULL \
-					|NETARM_SER_CTLA_IE_RX_DMAEN \
-					|NETARM_SER_CTLA_IE_RX_DCD \
-					|NETARM_SER_CTLA_IE_RX_RI \
-					|NETARM_SER_CTLA_IE_RX_DSR)
-
-#define	NETARM_SER_CTLA_IE_TX_CTS	(0x00000010)
-#define	NETARM_SER_CTLA_IE_TX_EMPTY	(0x00000008)
-#define	NETARM_SER_CTLA_IE_TX_HALF	(0x00000004)
-#define	NETARM_SER_CTLA_IE_TX_FULL	(0x00000002)
-#define	NETARM_SER_CTLA_IE_TX_DMAEN	(0x00000001)
-
-#define NETARM_SER_CTLA_IE_TX_ALL	(NETARM_SER_CTLA_IE_TX_CTS \
-					|NETARM_SER_CTLA_IE_TX_EMPTY \
-					|NETARM_SER_CTLA_IE_TX_HALF \
-					|NETARM_SER_CTLA_IE_TX_FULL \
-					|NETARM_SER_CTLA_IE_TX_DMAEN)
-
-/* Control Register B */
-
-#define	NETARM_SER_CTLB_MATCH1_EN	(0x80000000)
-#define	NETARM_SER_CTLB_MATCH2_EN	(0x40000000)
-#define	NETARM_SER_CTLB_MATCH3_EN	(0x20000000)
-#define	NETARM_SER_CTLB_MATCH4_EN	(0x10000000)
-
-#define	NETARM_SER_CTLB_RBGT_EN		(0x08000000)
-#define	NETARM_SER_CTLB_RCGT_EN		(0x04000000)
-
-#define	NETARM_SER_CTLB_UART_MODE	(0x00000000)
-#define	NETARM_SER_CTLB_HDLC_MODE	(0x00100000)
-#define	NETARM_SER_CTLB_SPI_MAS_MODE	(0x00200000)
-#define	NETARM_SER_CTLB_SPI_SLV_MODE	(0x00300000)
-
-#define	NETARM_SER_CTLB_REV_BIT_ORDER	(0x00080000)
-
-#define	NETARM_SER_CTLB_MAM1		(0x00040000)
-#define	NETARM_SER_CTLB_MAM2		(0x00020000)
-
-/* Status Register A */
-
-#define	NETARM_SER_STATA_MATCH1		(0x80000000)
-#define	NETARM_SER_STATA_MATCH2		(0x40000000)
-#define	NETARM_SER_STATA_MATCH3		(0x20000000)
-#define	NETARM_SER_STATA_MATCH4		(0x10000000)
-
-#define	NETARM_SER_STATA_BGAP		(0x80000000)
-#define	NETARM_SER_STATA_CGAP		(0x40000000)
-
-#define	NETARM_SER_STATA_RX_1B		(0x00100000)
-#define	NETARM_SER_STATA_RX_2B		(0x00200000)
-#define	NETARM_SER_STATA_RX_3B		(0x00300000)
-#define	NETARM_SER_STATA_RX_4B		(0x00000000)
-
-/* downshifted values */
-
-#define	NETARM_SER_STATA_RXFDB_1BYTES	(0x001)
-#define	NETARM_SER_STATA_RXFDB_2BYTES	(0x002)
-#define	NETARM_SER_STATA_RXFDB_3BYTES	(0x003)
-#define	NETARM_SER_STATA_RXFDB_4BYTES	(0x000)
-
-#define	NETARM_SER_STATA_RXFDB_MASK	(0x00300000)
-#define	NETARM_SER_STATA_RXFDB(x)	(((x) & NETARM_SER_STATA_RXFDB_MASK) \
-					 >> 20)
-
-#define	NETARM_SER_STATA_DCD		(0x00080000)
-#define	NETARM_SER_STATA_RI		(0x00040000)
-#define	NETARM_SER_STATA_DSR		(0x00020000)
-#define	NETARM_SER_STATA_CTS		(0x00010000)
-
-#define	NETARM_SER_STATA_RX_BRK		(0x00008000)
-#define	NETARM_SER_STATA_RX_FRMERR	(0x00004000)
-#define	NETARM_SER_STATA_RX_PARERR	(0x00002000)
-#define	NETARM_SER_STATA_RX_OVERRUN	(0x00001000)
-#define	NETARM_SER_STATA_RX_RDY		(0x00000800)
-#define	NETARM_SER_STATA_RX_HALF	(0x00000400)
-#define	NETARM_SER_STATA_RX_CLOSED	(0x00000200)
-#define	NETARM_SER_STATA_RX_FULL	(0x00000100)
-#define	NETARM_SER_STATA_RX_DCD		(0x00000080)
-#define	NETARM_SER_STATA_RX_RI		(0x00000040)
-#define	NETARM_SER_STATA_RX_DSR		(0x00000020)
-
-#define	NETARM_SER_STATA_TX_CTS		(0x00000010)
-#define	NETARM_SER_STATA_TX_RDY		(0x00000008)
-#define	NETARM_SER_STATA_TX_HALF	(0x00000004)
-#define	NETARM_SER_STATA_TX_FULL	(0x00000002)
-#define	NETARM_SER_STATA_TX_DMAEN	(0x00000001)
-
-/* you have to clear all receive signals to get the fifo to move forward */
-#define NETARM_SER_STATA_CLR_ALL	(NETARM_SER_STATA_RX_BRK | \
-					 NETARM_SER_STATA_RX_FRMERR | \
-					 NETARM_SER_STATA_RX_PARERR | \
-					 NETARM_SER_STATA_RX_OVERRUN | \
-					 NETARM_SER_STATA_RX_HALF | \
-					 NETARM_SER_STATA_RX_CLOSED | \
-					 NETARM_SER_STATA_RX_FULL | \
-					 NETARM_SER_STATA_RX_DCD | \
-					 NETARM_SER_STATA_RX_RI | \
-					 NETARM_SER_STATA_RX_DSR | \
-					 NETARM_SER_STATA_TX_CTS )
-
-/* Bit Rate Registers */
-
-#define	NETARM_SER_BR_EN		(0x80000000)
-#define	NETARM_SER_BR_TMODE		(0x40000000)
-
-#define	NETARM_SER_BR_RX_CLK_INT	(0x00000000)
-#define	NETARM_SER_BR_RX_CLK_EXT	(0x20000000)
-#define	NETARM_SER_BR_TX_CLK_INT	(0x00000000)
-#define	NETARM_SER_BR_TX_CLK_EXT	(0x10000000)
-
-#define	NETARM_SER_BR_RX_CLK_DRV	(0x08000000)
-#define	NETARM_SER_BR_TX_CLK_DRV	(0x04000000)
-
-#define	NETARM_SER_BR_CLK_EXT_5		(0x00000000)
-#define	NETARM_SER_BR_CLK_SYSTEM	(0x01000000)
-#define	NETARM_SER_BR_CLK_OUT1A		(0x02000000)
-#define	NETARM_SER_BR_CLK_OUT2A		(0x03000000)
-
-#define	NETARM_SER_BR_TX_CLK_INV	(0x00800000)
-#define	NETARM_SER_BR_RX_CLK_INV	(0x00400000)
-
-/* complete settings assuming system clock input is 18MHz */
-
-#define	NETARM_SER_BR_MASK		(0x000007FF)
-
-/* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
-/* from section 7.5.4 of HW Ref Guide */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
-				  NETARM_SER_BR_RX_CLK_INT |		\
-				  NETARM_SER_BR_TX_CLK_INT |		\
-				  NETARM_SER_BR_CLK_EXT_5 |		\
-				  ( ( ( ( NETARM_XTAL_FREQ /		\
-				          ( x * 10 ) ) - 1 ) /	16 ) &	\
-				    NETARM_SER_BR_MASK ) )
-/*
-#else
-#define	NETARM_SER_BR_X16(x)	( NETARM_SER_BR_EN |			\
-				  NETARM_SER_BR_RX_CLK_INT |		\
-				  NETARM_SER_BR_TX_CLK_INT |		\
-				  NETARM_SER_BR_CLK_SYSTEM |		\
-				  ( ( ( ( NETARM_PLLED_SYSCLK_FREQ /		\
-				          ( x * 2 ) ) - 1 ) /	16 ) &	\
-				    NETARM_SER_BR_MASK ) )
-#endif
-*/
-
-/* Receive Buffer Gap Timer */
-
-#define	NETARM_SER_RX_GAP_TIMER_EN	(0x80000000)
-#define	NETARM_SER_RX_GAP_MASK		(0x00003FFF)
-
-/* rx gap is a function of bit rate x */
-
-/* #ifdef CONFIG_NETARM_PLL_BYPASS */
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-/*
-#else
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |			\
-				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) &			\
-			              NETARM_SER_RX_GAP_MASK ) )
-#endif
-*/
-
-#if 0
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /	\
-				        ( x * 5 * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-#define	NETARM_SER_RXGAP(x)	( NETARM_SER_RX_GAP_TIMER_EN |		\
-				  ( ( ( ( 10 * NETARM_XTAL_FREQ ) /	\
-				        ( x * 512 ) ) - 1 ) &	\
-			              NETARM_SER_RX_GAP_MASK ) )
-#endif
-
-#define MIN_BAUD_RATE        600
-#define MAX_BAUD_RATE     115200
-
-/* the default BAUD rate for the BOOTLOADER, there is a separate */
-/* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
-#define DEFAULT_BAUD_RATE 9600
-#define NETARM_SER_FIFO_SIZE 32
-#define MIN_GAP 0
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h b/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
deleted file mode 100644
index 5715f3e..0000000
--- a/arch/arm/include/asm/arch-lpc2292/lpc2292_registers.h
+++ /dev/null
@@ -1,225 +0,0 @@
-#ifndef __LPC2292_REGISTERS_H
-#define __LPC2292_REGISTERS_H
-
-#include <config.h>
-
-/* Macros for reading/writing registers */
-#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
-#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
-#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
-#define GET8(reg) (*(volatile unsigned char*)(reg))
-#define GET16(reg) (*(volatile unsigned short*)(reg))
-#define GET32(reg) (*(volatile unsigned int*)(reg))
-
-/* External Memory Controller */
-
-#define BCFG0 0xFFE00000	/* 32-bits */
-#define BCFG1 0xFFE00004	/* 32-bits */
-#define BCFG2 0xFFE00008	/* 32-bits */
-#define BCFG3 0xFFE0000c	/* 32-bits */
-
-/* System Control Block */
-
-#define EXTINT   0xE01FC140
-#define EXTWAKE  0xE01FC144
-#define EXTMODE  0xE01FC148
-#define EXTPOLAR 0xE01FC14C
-#define MEMMAP   0xE01FC040
-#define PLLCON   0xE01FC080
-#define PLLCFG   0xE01FC084
-#define PLLSTAT  0xE01FC088
-#define PLLFEED  0xE01FC08C
-#define PCON     0xE01FC0C0
-#define PCONP    0xE01FC0C4
-#define VPBDIV   0xE01FC100
-
-/* Memory Acceleration Module */
-
-#define MAMCR  0xE01FC000
-#define MAMTIM 0xE01FC004
-
-/* Vectored Interrupt Controller */
-
-#define VICIRQStatus    0xFFFFF000
-#define VICFIQStatus    0xFFFFF004
-#define VICRawIntr      0xFFFFF008
-#define VICIntSelect    0xFFFFF00C
-#define VICIntEnable    0xFFFFF010
-#define VICIntEnClr     0xFFFFF014
-#define VICSoftInt      0xFFFFF018
-#define VICSoftIntClear 0xFFFFF01C
-#define VICProtection   0xFFFFF020
-#define VICVectAddr     0xFFFFF030
-#define VICDefVectAddr  0xFFFFF034
-#define VICVectAddr0    0xFFFFF100
-#define VICVectAddr1    0xFFFFF104
-#define VICVectAddr2    0xFFFFF108
-#define VICVectAddr3    0xFFFFF10C
-#define VICVectAddr4    0xFFFFF110
-#define VICVectAddr5    0xFFFFF114
-#define VICVectAddr6    0xFFFFF118
-#define VICVectAddr7    0xFFFFF11C
-#define VICVectAddr8    0xFFFFF120
-#define VICVectAddr9    0xFFFFF124
-#define VICVectAddr10   0xFFFFF128
-#define VICVectAddr11   0xFFFFF12C
-#define VICVectAddr12   0xFFFFF130
-#define VICVectAddr13   0xFFFFF134
-#define VICVectAddr14   0xFFFFF138
-#define VICVectAddr15   0xFFFFF13C
-#define VICVectCntl0    0xFFFFF200
-#define VICVectCntl1	0xFFFFF204
-#define VICVectCntl2	0xFFFFF208
-#define VICVectCntl3	0xFFFFF20C
-#define VICVectCntl4	0xFFFFF210
-#define VICVectCntl5	0xFFFFF214
-#define VICVectCntl6	0xFFFFF218
-#define VICVectCntl7	0xFFFFF21C
-#define VICVectCntl8	0xFFFFF220
-#define VICVectCntl9	0xFFFFF224
-#define VICVectCntl10	0xFFFFF228
-#define VICVectCntl11	0xFFFFF22C
-#define VICVectCntl12	0xFFFFF230
-#define VICVectCntl13	0xFFFFF234
-#define VICVectCntl14	0xFFFFF238
-#define VICVectCntl15	0xFFFFF23C
-
-/* Pin connect block */
-
-#define PINSEL0 0xE002C000	/* 32 bits */
-#define PINSEL1 0xE002C004	/* 32 bits */
-#define PINSEL2 0xE002C014	/* 32 bits */
-
-/* GPIO */
-
-#define IO0PIN 0xE0028000
-#define IO0SET 0xE0028004
-#define IO0DIR 0xE0028008
-#define IO0CLR 0xE002800C
-#define IO1PIN 0xE0028010
-#define IO1SET 0xE0028014
-#define IO1DIR 0xE0028018
-#define IO1CLR 0xE002801C
-#define IO2PIN 0xE0028020
-#define IO2SET 0xE0028024
-#define IO2DIR 0xE0028028
-#define IO2CLR 0xE002802C
-#define IO3PIN 0xE0028030
-#define IO3SET 0xE0028034
-#define IO3DIR 0xE0028038
-#define IO3CLR 0xE002803C
-
-/* Uarts */
-
-#define U0RBR 0xE000C000
-#define U0THR 0xE000C000
-#define U0IER 0xE000C004
-#define U0IIR 0xE000C008
-#define U0FCR 0xE000C008
-#define U0LCR 0xE000C00C
-#define U0LSR 0xE000C014
-#define U0SCR 0xE000C01C
-#define U0DLL 0xE000C000
-#define U0DLM 0xE000C004
-
-#define U1RBR 0xE0010000
-#define U1THR 0xE0010000
-#define U1IER 0xE0010004
-#define U1IIR 0xE0010008
-#define U1FCR 0xE0010008
-#define U1LCR 0xE001000C
-#define U1MCR 0xE0010010
-#define U1LSR 0xE0010014
-#define U1MSR 0xE0010018
-#define U1SCR 0xE001001C
-#define U1DLL 0xE0010000
-#define U1DLM 0xE0010004
-
-/* I2C */
-
-#define I2CONSET 0xE001C000
-#define I2STAT   0xE001C004
-#define I2DAT    0xE001C008
-#define I2ADR    0xE001C00C
-#define I2SCLH   0xE001C010
-#define I2SCLL   0xE001C014
-#define I2CONCLR 0xE001C018
-
-/* SPI */
-
-#define S0SPCR  0xE0020000
-#define S0SPSR  0xE0020004
-#define S0SPDR  0xE0020008
-#define S0SPCCR 0xE002000C
-#define S0SPINT 0xE002001C
-
-#define S1SPCR  0xE0030000
-#define S1SPSR  0xE0030004
-#define S1SPDR  0xE0030008
-#define S1SPCCR 0xE003000C
-#define S1SPINT 0xE003001C
-
-/* CAN controller */
-
-/* skip for now */
-
-/* Timers */
-
-#define T0IR  0xE0004000
-#define T0TCR 0xE0004004
-#define T0TC  0xE0004008
-#define T0PR  0xE000400C
-#define T0PC  0xE0004010
-#define T0MCR 0xE0004014
-#define T0MR0 0xE0004018
-#define T0MR1 0xE000401C
-#define T0MR2 0xE0004020
-#define T0MR3 0xE0004024
-#define T0CCR 0xE0004028
-#define T0CR0 0xE000402C
-#define T0CR1 0xE0004030
-#define T0CR2 0xE0004034
-#define T0CR3 0xE0004038
-#define T0EMR 0xE000403C
-
-#define T1IR  0xE0008000
-#define T1TCR 0xE0008004
-#define T1TC  0xE0008008
-#define T1PR  0xE000800C
-#define T1PC  0xE0008010
-#define T1MCR 0xE0008014
-#define T1MR0 0xE0008018
-#define T1MR1 0xE000801C
-#define T1MR2 0xE0008020
-#define T1MR3 0xE0008024
-#define T1CCR 0xE0008028
-#define T1CR0 0xE000802C
-#define T1CR1 0xE0008030
-#define T1CR2 0xE0008034
-#define T1CR3 0xE0008038
-#define T1EMR 0xE000803C
-
-/* PWM */
-
-/* skip for now */
-
-/* A/D converter */
-
-/* skip for now */
-
-/* Real Time Clock */
-
-/* skip for now */
-
-/* Watchdog */
-
-#define WDMOD  0xE0000000
-#define WDTC   0xE0000004
-#define WDFEED 0xE0000008
-#define WDTV   0xE000000C
-
-/* EmbeddedICE LOGIC */
-
-/* skip for now */
-
-#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/spi.h b/arch/arm/include/asm/arch-lpc2292/spi.h
deleted file mode 100644
index 6ae66e8..0000000
--- a/arch/arm/include/asm/arch-lpc2292/spi.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
-    This file defines the interface to the lpc22xx SPI module.
-    Copyright (C) 2006  Embedded Artists AB (www.embeddedartists.com)
-
-    This file may be included in software not adhering to the GPL.
-
-    This program is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    This program is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef SPI_H
-#define SPI_H
-
-#include <config.h>
-#include <common.h>
-#include <asm/errno.h>
-#include <asm/arch/hardware.h>
-
-#define SPIF 0x80
-
-#define spi_lock() disable_interrupts();
-#define spi_unlock() enable_interrupts();
-
-extern unsigned long spi_flags;
-extern unsigned char spi_idle;
-
-int spi_init(void);
-
-static inline unsigned char spi_read(void)
-{
-	unsigned char b;
-
-	PUT8(S0SPDR, spi_idle);
-	while (!(GET8(S0SPSR) & SPIF));
-	b = GET8(S0SPDR);
-
-	return b;
-}
-
-static inline void spi_write(unsigned char b)
-{
-	PUT8(S0SPDR, b);
-	while (!(GET8(S0SPSR) & SPIF));
-	GET8(S0SPDR);		/* this will clear the SPIF bit */
-}
-
-static inline void spi_set_clock(unsigned char clk_value)
-{
-	PUT8(S0SPCCR, clk_value);
-}
-
-static inline void spi_set_cfg(unsigned char phase,
-			       unsigned char polarity,
-			       unsigned char lsbf)
-{
-	unsigned char v = 0x20;	/* master bit set */
-
-	if (phase)
-		v |= 0x08;			/* set phase bit */
-	if (polarity) {
-		v |= 0x10;			/* set polarity bit */
-		spi_idle = 0xFF;
-	} else {
-		spi_idle = 0x00;
-	}
-	if (lsbf)
-		v |= 0x40;			/* set lsbf bit */
-
-	PUT8(S0SPCR, v);
-}
-#endif /* SPI_H */
diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index 54add4b..ffaffbb 100644
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -190,6 +190,7 @@ struct panel_config {
 
 #define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
 #define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
 
 /* Generic DSS Functions */
 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
diff --git a/arch/arm/include/asm/arch-s3c4510b/hardware.h b/arch/arm/include/asm/arch-s3c4510b/hardware.h
deleted file mode 100644
index 6b8c8ed..0000000
--- a/arch/arm/include/asm/arch-s3c4510b/hardware.h
+++ /dev/null
@@ -1,272 +0,0 @@
-#ifndef __HW_S3C4510_H
-#define __HW_S3C4510_H
-
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- * Description:   Samsung S3C4510B register layout
- */
-
-/*------------------------------------------------------------------------
- *	  ASIC Address Definition
- *----------------------------------------------------------------------*/
-
-/* L1 8KB on chip SRAM base address */
-#define SRAM_BASE       (0x03fe0000)
-
-/* Special Register Start Address After System Reset */
-#define REG_BASE	(0x03ff0000)
-#define SPSTR		(REG_BASE)
-
-/* *********************** */
-/* System Manager Register */
-/* *********************** */
-#define REG_SYSCFG	(REG_BASE+0x0000)
-
-#define REG_CLKCON      (REG_BASE+0x3000)
-#define REG_EXTACON0	(REG_BASE+0x3008)
-#define REG_EXTACON1	(REG_BASE+0x300c)
-#define REG_EXTDBWTH	(REG_BASE+0x3010)
-#define REG_ROMCON0	(REG_BASE+0x3014)
-#define REG_ROMCON1	(REG_BASE+0x3018)
-#define REG_ROMCON2	(REG_BASE+0x301c)
-#define REG_ROMCON3	(REG_BASE+0x3020)
-#define REG_ROMCON4	(REG_BASE+0x3024)
-#define REG_ROMCON5	(REG_BASE+0x3028)
-#define REG_DRAMCON0	(REG_BASE+0x302c)
-#define REG_DRAMCON1	(REG_BASE+0x3030)
-#define REG_DRAMCON2	(REG_BASE+0x3034)
-#define REG_DRAMCON3	(REG_BASE+0x3038)
-#define REG_REFEXTCON	(REG_BASE+0x303c)
-
-/* *********************** */
-/* Ethernet BDMA Register  */
-/* *********************** */
-#define REG_BDMATXCON	(REG_BASE+0x9000)
-#define REG_BDMARXCON	(REG_BASE+0x9004)
-#define REG_BDMATXPTR	(REG_BASE+0x9008)
-#define REG_BDMARXPTR	(REG_BASE+0x900c)
-#define REG_BDMARXLSZ	(REG_BASE+0x9010)
-#define REG_BDMASTAT	(REG_BASE+0x9014)
-
-/* Content Address Memory */
-#define REG_CAM_BASE	(REG_BASE+0x9100)
-
-#define REG_BDMATXBUF	(REG_BASE+0x9200)
-#define REG_BDMARXBUF	(REG_BASE+0x9800)
-
-/* *********************** */
-/* Ethernet MAC Register   */
-/* *********************** */
-#define REG_MACCON	(REG_BASE+0xa000)
-#define REG_CAMCON	(REG_BASE+0xa004)
-#define REG_MACTXCON	(REG_BASE+0xa008)
-#define REG_MACTXSTAT	(REG_BASE+0xa00c)
-#define REG_MACRXCON	(REG_BASE+0xa010)
-#define REG_MACRXSTAT	(REG_BASE+0xa014)
-#define REG_STADATA	(REG_BASE+0xa018)
-#define REG_STACON	(REG_BASE+0xa01c)
-#define REG_CAMEN	(REG_BASE+0xa028)
-#define REG_EMISSCNT	(REG_BASE+0xa03c)
-#define REG_EPZCNT	(REG_BASE+0xa040)
-#define REG_ERMPZCNT	(REG_BASE+0xa044)
-#define REG_ETXSTAT	(REG_BASE+0x9040)
-#define REG_MACRXDESTR	(REG_BASE+0xa064)
-#define REG_MACRXSTATEM	(REG_BASE+0xa090)
-#define REG_MACRXFIFO	(REG_BASE+0xa200)
-
-/********************/
-/* I2C Bus Register */
-/********************/
-#define REG_I2C_CON	(REG_BASE+0xf000)
-#define REG_I2C_BUF	(REG_BASE+0xf004)
-#define REG_I2C_PS	(REG_BASE+0xf008)
-#define REG_I2C_COUNT	(REG_BASE+0xf00c)
-
-/********************/
-/*    GDMA 0        */
-/********************/
-#define REG_GDMACON0	(REG_BASE+0xb000)
-#define REG_GDMA0_RUN_ENABLE (REG_BASE+0xb020)
-#define REG_GDMASRC0	(REG_BASE+0xb004)
-#define REG_GDMADST0	(REG_BASE+0xb008)
-#define REG_GDMACNT0	(REG_BASE+0xb00c)
-
-/********************/
-/*    GDMA 1        */
-/********************/
-#define REG_GDMACON1	(REG_BASE+0xc000)
-#define REG_GDMA1_RUN_ENABLE (REG_BASE+0xc020)
-#define REG_GDMASRC1	(REG_BASE+0xc004)
-#define REG_GDMADST1	(REG_BASE+0xc008)
-#define REG_GDMACNT1	(REG_BASE+0xc00c)
-
-/********************/
-/*      UART 0      */
-/********************/
-#define UART0_BASE       (REG_BASE+0xd000)
-#define REG_UART0_LCON   (REG_BASE+0xd000)
-#define REG_UART0_CTRL   (REG_BASE+0xd004)
-#define REG_UART0_STAT   (REG_BASE+0xd008)
-#define REG_UART0_TXB    (REG_BASE+0xd00c)
-#define REG_UART0_RXB    (REG_BASE+0xd010)
-#define REG_UART0_BAUD_DIV    (REG_BASE+0xd014)
-#define REG_UART0_BAUD_CNT    (REG_BASE+0xd018)
-#define REG_UART0_BAUD_CLK    (REG_BASE+0xd01C)
-
-/********************/
-/*     UART 1       */
-/********************/
-#define UART1_BASE       (REG_BASE+0xe000)
-#define REG_UART1_LCON   (REG_BASE+0xe000)
-#define REG_UART1_CTRL   (REG_BASE+0xe004)
-#define REG_UART1_STAT   (REG_BASE+0xe008)
-#define REG_UART1_TXB    (REG_BASE+0xe00c)
-#define REG_UART1_RXB    (REG_BASE+0xe010)
-#define REG_UART1_BAUD_DIV    (REG_BASE+0xe014)
-#define REG_UART1_BAUD_CNT    (REG_BASE+0xe018)
-#define REG_UART1_BAUD_CLK    (REG_BASE+0xe01C)
-
-/********************/
-/*  Timer Register  */
-/********************/
-#define REG_TMOD	(REG_BASE+0x6000)
-#define REG_TDATA0	(REG_BASE+0x6004)
-#define REG_TDATA1	(REG_BASE+0x6008)
-#define REG_TCNT0	(REG_BASE+0x600c)
-#define REG_TCNT1	(REG_BASE+0x6010)
-
-/**********************/
-/* I/O Port Interface */
-/**********************/
-#define REG_IOPMODE	(REG_BASE+0x5000)
-#define REG_IOPCON	(REG_BASE+0x5004)
-#define REG_IOPDATA	(REG_BASE+0x5008)
-
-/*********************************/
-/* Interrupt Controller Register */
-/*********************************/
-#define REG_INTMODE     (REG_BASE+0x4000)
-#define REG_INTPEND     (REG_BASE+0x4004)
-#define REG_INTMASK     (REG_BASE+0x4008)
-
-#define REG_INTPRI0     (REG_BASE+0x400c)
-#define REG_INTPRI1	(REG_BASE+0x4010)
-#define REG_INTPRI2	(REG_BASE+0x4014)
-#define REG_INTPRI3	(REG_BASE+0x4018)
-#define REG_INTPRI4	(REG_BASE+0x401c)
-#define REG_INTPRI5	(REG_BASE+0x4020)
-#define REG_INTOFFSET	(REG_BASE+0x4024)
-#define REG_INTPNDPRI	(REG_BASE+0x4028)
-#define REG_INTPNDTST	(REG_BASE+0x402C)
-
-/*********************************/
-/* CACHE CONTROL MASKS           */
-/*********************************/
-#define CACHE_STALL      (0x00000001)
-#define CACHE_ENABLE     (0x00000002)
-#define CACHE_WRITE_BUFF (0x00000004)
-#define CACHE_MODE       (0x00000030)
-#define CACHE_MODE_00    (0x00000000)
-#define CACHE_MODE_01    (0x00000010)
-#define CACHE_MODE_10    (0x00000020)
-
-/*********************************/
-/* CACHE RAM BASE ADDRESSES      */
-/*********************************/
-#define CACHE_SET0_RAM   (0x10000000)
-#define CACHE_SET1_RAM   (0x10800000)
-#define CACHE_TAG_RAM    (0x11000000)
-
-/*********************************/
-/* CACHE_DISABLE MASK            */
-/*********************************/
-#define CACHE_DISABLE_MASK (0x04000000)
-
-#define GET_REG(reg)       (*((volatile u32 *)(reg)))
-#define PUT_REG(reg, val)  (*((volatile u32 *)(reg)) = ((u32)(val)))
-#define SET_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) |  mask))
-#define CLR_REG(reg, mask) (PUT_REG((reg), GET_REG((reg)) & ~mask))
-#define PUT_U16(reg, val)  (*((volatile u16 *)(reg)) = ((u16)(val)))
-#define PUT__U8(reg, val)  (*((volatile u8  *)(reg)) = (( u8)((val)&0xFF)))
-#define GET__U8(reg)       (*((volatile u8  *)(reg)))
-
-#define PUT_LED(val)       (PUT_REG(REG_IOPDATA, (~val)&0xFF))
-#define GET_LED()          ((~GET_REG( REG_IOPDATA)) & 0xFF)
-#define SET_LED(val)       { u32 led = GET_LED(); led |= 1 << (val);  PUT_LED( led); }
-#define CLR_LED(val)       { u32 led = GET_LED(); led &= ~(1 << (val));  PUT_LED( led); }
-
-/***********************************/
-/* CLOCK CONSTANTS -- 50 MHz Clock */
-/***********************************/
-
-#define CLK_FREQ_MHZ       (50)
-#define t_data_us(t)       ((t)*CLK_FREQ_MHZ-1)   /* t is time tick,unit[us] */
-#define t_data_ms(t)       (t_data_us((t)*1000))  /* t is time tick,unit[ms] */
-
-/*********************************************************/
-/*	       TIMER MODE REGISTER                       */
-/*********************************************************/
-#define  TM0_RUN      0x01  /* Timer 0 enable */
-#define  TM0_TOGGLE   0x02  /* 0, interval mode */
-#define  TM0_OUT_1    0x04  /* Timer 0 Initial TOUT0 value */
-#define  TM1_RUN      0x08  /* Timer 1 enable */
-#define  TM1_TOGGLE   0x10  /* 0, interval mode */
-#define  TM1_OUT_1    0x20  /* Timer 0 Initial TOUT0 value */
-
-
-/*********************************/
-/* INTERRUPT SOURCES             */
-/*********************************/
-#define INT_EXTINT0	0
-#define INT_EXTINT1	1
-#define INT_EXTINT2	2
-#define INT_EXTINT3	3
-#define INT_UARTTX0	4
-#define INT_UARTRX0	5
-#define INT_UARTTX1	6
-#define INT_UARTRX1	7
-#define INT_GDMA0	8
-#define INT_GDMA1	9
-#define INT_TIMER0	10
-#define INT_TIMER1	11
-#define INT_HDLCTXA	12
-#define INT_HDLCRXA	13
-#define INT_HDLCTXB	14
-#define INT_HDLCRXB	15
-#define INT_BDMATX	16
-#define INT_BDMARX	17
-#define INT_MACTX	18
-#define INT_MACRX	19
-#define INT_IIC		20
-#define INT_GLOBAL	21
-#define N_IRQS         (21)
-
-#ifndef __ASSEMBLER__
-struct _irq_handler {
-	void                *m_data;
-	void (*m_func)( void *data);
-};
-
-#endif
-
-#endif /* __S3C4510_h */
diff --git a/arch/arm/include/asm/arch-tegra20/spl.h b/arch/arm/include/asm/arch-tegra20/spl.h
new file mode 100644
index 0000000..5e453c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra20/spl.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2012
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+#define BOOT_DEVICE_RAM         1
+
+#endif
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index f8088fe..2b9af93 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -34,7 +34,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 89df4dc..78a7fac 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -267,3 +267,8 @@ struct meminfo {
 extern struct meminfo meminfo;
 
 #endif
+
+/*
+ * Board specified tags
+ */
+void setup_board_tags(struct tag **in_params);
diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h
index eac3800..2ba98bc 100644
--- a/arch/arm/include/asm/u-boot.h
+++ b/arch/arm/include/asm/u-boot.h
@@ -37,7 +37,7 @@
 #define _U_BOOT_H_	1
 
 typedef struct bd_info {
-    int			bi_baudrate;	/* serial console baudrate */
+	unsigned int	bi_baudrate;	/* serial console baudrate */
     ulong	        bi_arch_number;	/* unique id for this board */
     ulong	        bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_arm_freq; /* arm frequency */
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index 0b47ab3..92cad9a 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -57,13 +57,6 @@
 #include <miiphy.h>
 #endif
 
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
 DECLARE_GLOBAL_DATA_PTR;
 
 ulong monitor_flash_len;
@@ -274,6 +267,8 @@ void board_init_f(ulong bootflag)
 #ifdef CONFIG_PRAM
 	ulong reg;
 #endif
+	void *new_fdt = NULL;
+	size_t fdt_size = 0;
 
 	bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
 
@@ -409,6 +404,22 @@ void board_init_f(ulong bootflag)
 	debug("Reserving %zu Bytes for Global Data at: %08lx\n",
 			sizeof (gd_t), addr_sp);
 
+#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
+	/*
+	 * If the device tree is sitting immediate above our image then we
+	 * must relocate it. If it is embedded in the data section, then it
+	 * will be relocated with other data.
+	 */
+	if (gd->fdt_blob) {
+		fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+		addr_sp -= fdt_size;
+		new_fdt = (void *)addr_sp;
+		debug("Reserving %zu Bytes for FDT at: %08lx\n",
+		      fdt_size, addr_sp);
+	}
+#endif
+
 	/* setup stackpointer for exeptions */
 	gd->irq_sp = addr_sp;
 #ifdef CONFIG_USE_IRQ
@@ -442,6 +453,10 @@ void board_init_f(ulong bootflag)
 	gd->start_addr_sp = addr_sp;
 	gd->reloc_off = addr - _TEXT_BASE;
 	debug("relocation Offset is: %08lx\n", gd->reloc_off);
+	if (new_fdt) {
+		memcpy(new_fdt, gd->fdt_blob, fdt_size);
+		gd->fdt_blob = new_fdt;
+	}
 	memcpy(id, (void *)gd, sizeof(gd_t));
 
 	relocate_code(addr_sp, id, addr);
@@ -591,16 +606,6 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* enable exceptions */
 	enable_interrupts();
 
-	/* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
-	/* XXX: this needs to be moved to board init */
-	if (getenv("ethaddr")) {
-		uchar enetaddr[6];
-		eth_getenv_enetaddr("ethaddr", enetaddr);
-		smc_set_mac_addr(enetaddr);
-	}
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 37476cc..1bd2730 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -34,6 +34,7 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/bootm.h>
+#include <linux/compiler.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -269,6 +270,8 @@ static int create_fdt(bootm_headers_t *images)
 }
 #endif
 
+__weak void setup_board_tags(struct tag **in_params) {}
+
 /* Subcommand: PREP */
 static void boot_prep_linux(bootm_headers_t *images)
 {
@@ -310,6 +313,7 @@ static void boot_prep_linux(bootm_headers_t *images)
 			setup_initrd_tag(gd->bd, images->rd_start,
 			images->rd_end);
 #endif
+		setup_board_tags(&params);
 		setup_end_tag(gd->bd);
 #else /* all tags */
 		printf("FDT and ATAGS support not compiled in - hanging\n");
diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds
index 0e532f2..0b16d2a 100644
--- a/arch/avr32/cpu/u-boot.lds
+++ b/arch/avr32/cpu/u-boot.lds
@@ -47,11 +47,11 @@ SECTIONS
 	}
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : {
-		KEEP(*(.u_boot_cmd))
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
 	}
-	__u_boot_cmd_end = .;
 
 	. = ALIGN(4);
 	_got = .;
diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h
index 7878bb1..bf661e2 100644
--- a/arch/avr32/include/asm/global_data.h
+++ b/arch/avr32/include/asm/global_data.h
@@ -33,7 +33,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	stack_end;	/* highest stack address */
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h
index 1d2959a..97bbbde 100644
--- a/arch/avr32/include/asm/u-boot.h
+++ b/arch/avr32/include/asm/u-boot.h
@@ -23,7 +23,7 @@
 #define __ASM_U_BOOT_H__ 1
 
 typedef struct bd_info {
-	unsigned long		bi_baudrate;
+	unsigned int		bi_baudrate;
 	unsigned char		bi_phy_id[4];
 	unsigned long		bi_board_number;
 	void			*bi_boot_params;
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 9d3b76e..e3287c4 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -272,8 +272,8 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 	/*
 	 * We have to relocate the command table manually
 	 */
-	fixup_cmdtable(&__u_boot_cmd_start,
-		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+			ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	/* there are some other pointer constants we must deal with */
diff --git a/arch/blackfin/cpu/u-boot.lds b/arch/blackfin/cpu/u-boot.lds
index 2b8d285..58db838 100644
--- a/arch/blackfin/cpu/u-boot.lds
+++ b/arch/blackfin/cpu/u-boot.lds
@@ -112,11 +112,9 @@ SECTIONS
 		CONSTRUCTORS
 	} >ram_data
 
-	.u_boot_cmd :
-	{
-		___u_boot_cmd_start = .;
-		*(.u_boot_cmd)
-		___u_boot_cmd_end = .;
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	} >ram_data
 
 	.text_l1 :
diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h
index 290a9e7..d91e5a4 100644
--- a/arch/blackfin/include/asm/global_data.h
+++ b/arch/blackfin/include/asm/global_data.h
@@ -41,7 +41,7 @@ typedef struct global_data {
 	bd_t *bd;
 	unsigned long flags;
 	unsigned long board_type;
-	unsigned long baudrate;
+	unsigned int baudrate;
 	unsigned long have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h
index df81183..7abd6c2 100644
--- a/arch/blackfin/include/asm/u-boot.h
+++ b/arch/blackfin/include/asm/u-boot.h
@@ -29,7 +29,7 @@
 #define _U_BOOT_H_	1
 
 typedef struct bd_info {
-	int bi_baudrate;		/* serial console baudrate */
+	unsigned int bi_baudrate;	/* serial console baudrate */
 	unsigned long bi_boot_params;	/* where this board expects params */
 	unsigned long bi_memstart;	/* start of DRAM memory */
 	phys_size_t bi_memsize;		/* size  of DRAM memory in bytes */
diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c
index e47b606..9fbbea0 100644
--- a/arch/blackfin/lib/board.c
+++ b/arch/blackfin/lib/board.c
@@ -78,7 +78,7 @@ static void display_global_data(void)
 	printf(" gd: %p\n", gd);
 	printf(" |-flags: %lx\n", gd->flags);
 	printf(" |-board_type: %lx\n", gd->board_type);
-	printf(" |-baudrate: %lu\n", gd->baudrate);
+	printf(" |-baudrate: %u\n", gd->baudrate);
 	printf(" |-have_console: %lx\n", gd->have_console);
 	printf(" |-ram_size: %lx\n", gd->ram_size);
 	printf(" |-env_addr: %lx\n", gd->env_addr);
diff --git a/arch/m68k/cpu/mcf5227x/cpu_init.c b/arch/m68k/cpu/mcf5227x/cpu_init.c
index e23b20d..1928eb3 100644
--- a/arch/m68k/cpu/mcf5227x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5227x/cpu_init.c
@@ -31,6 +31,7 @@
 #include <asm/immap.h>
 #include <asm/io.h>
 #include <asm/rtc.h>
+#include <linux/compiler.h>
 
 /*
  * Breath some life into the CPU...
@@ -41,12 +42,13 @@
  */
 void cpu_init_f(void)
 {
-	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-	pll_t *pll = (pll_t *)MMAP_PLL;
+	fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
 
 #if !defined(CONFIG_CF_SBF)
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+
 	/* Workaround, must place before fbcs */
 	out_be32(&pll->psr, 0x12);
 
diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S
index c5096a8..a683778 100644
--- a/arch/m68k/cpu/mcf5227x/start.S
+++ b/arch/m68k/cpu/mcf5227x/start.S
@@ -485,7 +485,7 @@ clear_bss:
 /* exception code */
 	.globl _fault
 _fault:
-	jmp _fault
+	bra _fault
 	.globl	_exc_handler
 
 _exc_handler:
diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S
index e6a69ab..05f1723 100644
--- a/arch/m68k/cpu/mcf523x/start.S
+++ b/arch/m68k/cpu/mcf523x/start.S
@@ -247,7 +247,7 @@ clear_bss:
 /* exception code */
 	.globl _fault
 _fault:
-	jmp _fault
+	bra _fault
 	.globl	_exc_handler
 
 _exc_handler:
diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S
index ee17792..f5e55dd 100644
--- a/arch/m68k/cpu/mcf52x2/start.S
+++ b/arch/m68k/cpu/mcf52x2/start.S
@@ -307,7 +307,7 @@ clear_bss:
 /* exception code */
 	.globl _fault
 _fault:
-	jmp _fault
+	bra _fault
 
 	.globl	_exc_handler
 _exc_handler:
diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S
index fe98d76..583ed1d 100644
--- a/arch/m68k/cpu/mcf532x/start.S
+++ b/arch/m68k/cpu/mcf532x/start.S
@@ -261,7 +261,7 @@ clear_bss:
 /* exception code */
 	.globl _fault
 _fault:
-	jmp _fault
+	bra _fault
 	.globl	_exc_handler
 
 _exc_handler:
diff --git a/arch/m68k/cpu/mcf5445x/config.mk b/arch/m68k/cpu/mcf5445x/config.mk
index 61a731e..0c48783 100644
--- a/arch/m68k/cpu/mcf5445x/config.mk
+++ b/arch/m68k/cpu/mcf5445x/config.mk
@@ -4,6 +4,8 @@
 # (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# Copyright 2011-2012 Freescale Semiconductor, Inc.
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -24,7 +26,15 @@
 #
 
 PLATFORM_RELFLAGS += -ffixed-d7 -msep-data
+
+cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
+is5441x:=$(shell grep CONFIG_MCF5441x $(TOPDIR)/include/$(cfg))
+
+ifneq (,$(findstring CONFIG_MCF5441x,$(is5441x)))
+PLATFORM_CPPFLAGS += -mcpu=54418 -fPIC
+else
 PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
+endif
 
 ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
 ifneq (,$(findstring GOT,$(shell $(LD) --help)))
diff --git a/arch/m68k/cpu/mcf5445x/cpu.c b/arch/m68k/cpu/mcf5445x/cpu.c
index adfc708..b612cda 100644
--- a/arch/m68k/cpu/mcf5445x/cpu.c
+++ b/arch/m68k/cpu/mcf5445x/cpu.c
@@ -39,6 +39,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	rcm_t *rcm = (rcm_t *) (MMAP_RCM);
 	udelay(1000);
+	out_8(&rcm->rcr, RCM_RCR_FRCRSTOUT);
+	udelay(10000);
 	setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
 
 	/* we don't return! */
@@ -74,6 +76,21 @@ int checkcpu(void)
 	case 0x4f:
 		id = 54450;
 		break;
+	case 0x9F:
+		id = 54410;
+		break;
+	case 0xA0:
+		id = 54415;
+		break;
+	case 0xA1:
+		id = 54416;
+		break;
+	case 0xA2:
+		id = 54417;
+		break;
+	case 0xA3:
+		id = 54418;
+		break;
 	}
 
 	if (id) {
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 3f9209f..6e947d0 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -31,6 +31,7 @@
 #include <asm/processor.h>
 #include <asm/rtc.h>
 #include <asm/io.h>
+#include <linux/compiler.h>
 
 #if defined(CONFIG_CMD_NET)
 #include <config.h>
@@ -38,37 +39,11 @@
 #include <asm/fec.h>
 #endif
 
-/*
- * Breath some life into the CPU...
- *
- * Set up the memory map,
- * initialize a bunch of registers,
- * initialize the UPM's
- */
-void cpu_init_f(void)
+void init_fbcs(void)
 {
-	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
-	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
-
-	out_be32(&scm1->mpr, 0x77777777);
-	out_be32(&scm1->pacra, 0);
-	out_be32(&scm1->pacrb, 0);
-	out_be32(&scm1->pacrc, 0);
-	out_be32(&scm1->pacrd, 0);
-	out_be32(&scm1->pacre, 0);
-	out_be32(&scm1->pacrf, 0);
-	out_be32(&scm1->pacrg, 0);
+	fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
 
-	/* FlexBus */
-	out_8(&gpio->par_be,
-		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
-		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
-	out_8(&gpio->par_fbctl,
-		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
-		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
-
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
 	out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
 	out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
@@ -106,6 +81,145 @@ void cpu_init_f(void)
 	out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
 	out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
 #endif
+}
+
+/*
+ * Breath some life into the CPU...
+ *
+ * Set up the memory map,
+ * initialize a bunch of registers,
+ * initialize the UPM's
+ */
+void cpu_init_f(void)
+{
+	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+#ifdef CONFIG_MCF5441x
+	scm_t *scm = (scm_t *) MMAP_SCM;
+	pm_t *pm = (pm_t *) MMAP_PM;
+
+	/* Disable Switch */
+	*(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
+
+	/* Disable core watchdog */
+	out_be16(&scm->cwcr, 0);
+	out_8(&gpio->par_fbctl,
+		GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
+		GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
+		GPIO_PAR_FBCTL_TA_TA);
+	out_8(&gpio->par_be,
+		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+
+	/* eDMA */
+	out_8(&pm->pmcr0, 17);
+
+	/* INTR0 - INTR2 */
+	out_8(&pm->pmcr0, 18);
+	out_8(&pm->pmcr0, 19);
+	out_8(&pm->pmcr0, 20);
+
+	/* I2C */
+	out_8(&pm->pmcr0, 22);
+	out_8(&pm->pmcr1, 4);
+	out_8(&pm->pmcr1, 7);
+
+	/* DTMR0 - DTMR3*/
+	out_8(&pm->pmcr0, 28);
+	out_8(&pm->pmcr0, 29);
+	out_8(&pm->pmcr0, 30);
+	out_8(&pm->pmcr0, 31);
+
+	/* PIT0 - PIT3 */
+	out_8(&pm->pmcr0, 32);
+	out_8(&pm->pmcr0, 33);
+	out_8(&pm->pmcr0, 34);
+	out_8(&pm->pmcr0, 35);
+
+	/* Edge Port */
+	out_8(&pm->pmcr0, 36);
+	out_8(&pm->pmcr0, 37);
+
+	/* USB OTG */
+	out_8(&pm->pmcr0, 44);
+	/* USB Host */
+	out_8(&pm->pmcr0, 45);
+
+	/* ESDHC */
+	out_8(&pm->pmcr0, 51);
+
+	/* ENET0 - ENET1 */
+	out_8(&pm->pmcr0, 53);
+	out_8(&pm->pmcr0, 54);
+
+	/* NAND */
+	out_8(&pm->pmcr0, 63);
+
+#ifdef CONFIG_SYS_I2C_0
+	out_8(&gpio->par_cani2c, 0xF0);
+	/* I2C0 pull up */
+	out_be16(&gpio->pcr_b, 0x003C);
+	/* I2C0 max speed */
+	out_8(&gpio->srcr_cani2c, 0x03);
+#endif
+#ifdef CONFIG_SYS_I2C_2
+	/* I2C2 */
+	out_8(&gpio->par_ssi0h, 0xA0);
+	/* I2C2, UART7 */
+	out_8(&gpio->par_ssi0h, 0xA8);
+	/* UART7 */
+	out_8(&gpio->par_ssi0l, 0x2);
+	/* UART8, UART9 */
+	out_8(&gpio->par_cani2c, 0xAA);
+	/* UART4, UART0 */
+	out_8(&gpio->par_uart0, 0xAF);
+	/* UART5, UART1 */
+	out_8(&gpio->par_uart1, 0xAF);
+	/* UART6, UART2 */
+	out_8(&gpio->par_uart2, 0xAF);
+	/* I2C2 pull up */
+	out_be16(&gpio->pcr_h, 0xF000);
+#endif
+#ifdef CONFIG_SYS_I2C_5
+	/* I2C5 */
+	out_8(&gpio->par_uart1, 0x0A);
+	/* I2C5 pull up */
+	out_be16(&gpio->pcr_e, 0x0003);
+	out_be16(&gpio->pcr_f, 0xC000);
+#endif
+
+	/* Lowest slew rate for UART0,1,2 */
+	out_8(&gpio->srcr_uart, 0x00);
+#endif		/* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
+	scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
+
+	out_be32(&scm1->mpr, 0x77777777);
+	out_be32(&scm1->pacra, 0);
+	out_be32(&scm1->pacrb, 0);
+	out_be32(&scm1->pacrc, 0);
+	out_be32(&scm1->pacrd, 0);
+	out_be32(&scm1->pacre, 0);
+	out_be32(&scm1->pacrf, 0);
+	out_be32(&scm1->pacrg, 0);
+
+	/* FlexBus */
+	out_8(&gpio->par_be,
+		GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
+		GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
+	out_8(&gpio->par_fbctl,
+		GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
+		GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
+
+#ifdef CONFIG_FSL_I2C
+	out_be16(&gpio->par_feci2c,
+		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
+#endif
+#endif		/* CONFIG_MCF5445x */
+
+	/* FlexBus Chipselect */
+	init_fbcs();
 
 	/*
 	 * now the flash base address is no longer at 0 (Newer ColdFire family
@@ -115,11 +229,6 @@ void cpu_init_f(void)
 	if (CONFIG_SYS_CS0_BASE != 0)
 		setvbr(CONFIG_SYS_CS0_BASE);
 
-#ifdef CONFIG_FSL_I2C
-	out_be16(&gpio->par_feci2c,
-		GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
-#endif
-
 	icache_enable();
 }
 
@@ -142,9 +251,95 @@ int cpu_init_r(void)
 void uart_port_conf(int port)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5441x
+	pm_t *pm = (pm_t *) MMAP_PM;
+#endif
 
 	/* Setup Ports: */
 	switch (port) {
+#ifdef CONFIG_MCF5441x
+	case 0:
+		/* UART0 */
+		out_8(&pm->pmcr0, 24);
+		clrbits_8(&gpio->par_uart0,
+			~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
+		setbits_8(&gpio->par_uart0,
+			GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
+		break;
+	case 1:
+		/* UART1 */
+		out_8(&pm->pmcr0, 25);
+		clrbits_8(&gpio->par_uart1,
+			~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
+		setbits_8(&gpio->par_uart1,
+			GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
+		break;
+	case 2:
+		/* UART2 */
+		out_8(&pm->pmcr0, 26);
+		clrbits_8(&gpio->par_uart2,
+			~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
+		setbits_8(&gpio->par_uart2,
+			GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
+		break;
+	case 3:
+		/* UART3 */
+		out_8(&pm->pmcr0, 27);
+		clrbits_8(&gpio->par_dspi0,
+			~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
+		setbits_8(&gpio->par_dspi0,
+			GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
+		break;
+	case 4:
+		/* UART4 */
+		out_8(&pm->pmcr1, 24);
+		clrbits_8(&gpio->par_uart0,
+			~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
+		setbits_8(&gpio->par_uart0,
+			GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
+		break;
+	case 5:
+		/* UART5 */
+		out_8(&pm->pmcr1, 25);
+		clrbits_8(&gpio->par_uart1,
+			~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
+		setbits_8(&gpio->par_uart1,
+			GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
+		break;
+	case 6:
+		/* UART6 */
+		out_8(&pm->pmcr1, 26);
+		clrbits_8(&gpio->par_uart2,
+			~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
+		setbits_8(&gpio->par_uart2,
+			GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
+		break;
+	case 7:
+		/* UART7 */
+		out_8(&pm->pmcr1, 27);
+		clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
+		clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
+		setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
+		setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
+		break;
+	case 8:
+		/* UART8 */
+		out_8(&pm->pmcr0, 28);
+		clrbits_8(&gpio->par_cani2c,
+			~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
+		setbits_8(&gpio->par_cani2c,
+			GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
+		break;
+	case 9:
+		/* UART9 */
+		out_8(&pm->pmcr1, 29);
+		clrbits_8(&gpio->par_cani2c,
+			~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
+		setbits_8(&gpio->par_cani2c,
+			GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
+		break;
+#endif
+#ifdef CONFIG_MCF5445x
 	case 0:
 		clrbits_8(&gpio->par_uart,
 			GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
@@ -177,6 +372,7 @@ void uart_port_conf(int port)
 			GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
 #endif
 		break;
+#endif	/* CONFIG_MCF5445x */
 	}
 }
 
@@ -186,6 +382,7 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	struct fec_info_s *info = (struct fec_info_s *)dev->priv;
 
+#ifdef CONFIG_MCF5445x
 	if (setclear) {
 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
 		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
@@ -223,6 +420,21 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
 #endif
 		}
 	}
+#endif	/* CONFIG_MCF5445x */
+
+#ifdef CONFIG_MCF5441x
+	if (setclear) {
+		out_8(&gpio->par_fec, 0x03);
+		out_8(&gpio->srcr_fec, 0x0F);
+		clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
+			GPIO_PAR_SIMP0H_DAT_GPIO);
+		clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
+			GPIO_PDDR_G4_OUTPUT);
+		clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
+
+	} else
+		clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
+#endif
 	return 0;
 }
 #endif
@@ -232,10 +444,24 @@ void cfspi_port_conf(void)
 {
 	gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
+#ifdef CONFIG_MCF5445x
 	out_8(&gpio->par_dspi,
 		GPIO_PAR_DSPI_SIN_SIN |
 		GPIO_PAR_DSPI_SOUT_SOUT |
 		GPIO_PAR_DSPI_SCK_SCK);
+#endif
+
+#ifdef CONFIG_MCF5441x
+	pm_t *pm = (pm_t *) MMAP_PM;
+
+	out_8(&gpio->par_dspi0,
+		GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
+		GPIO_PAR_DSPI0_SCK_DSPI0SCK);
+	out_8(&gpio->srcr_dspiow, 3);
+
+	/* DSPI0 */
+	out_8(&pm->pmcr0, 23);
+#endif
 }
 
 int cfspi_claim_bus(uint bus, uint cs)
@@ -249,6 +475,7 @@ int cfspi_claim_bus(uint bus, uint cs)
 	/* Clear FIFO and resume transfer */
 	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
+#ifdef CONFIG_MCF5445x
 	switch (cs) {
 	case 0:
 		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@@ -271,6 +498,20 @@ int cfspi_claim_bus(uint bus, uint cs)
 		setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 		break;
 	}
+#endif
+
+#ifdef CONFIG_MCF5441x
+	switch (cs) {
+	case 0:
+		clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
+		setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
+		break;
+	case 1:
+		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+		setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+		break;
+	}
+#endif
 
 	return 0;
 }
@@ -283,6 +524,7 @@ void cfspi_release_bus(uint bus, uint cs)
 	/* Clear FIFO */
 	clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
 
+#ifdef CONFIG_MCF5445x
 	switch (cs) {
 	case 0:
 		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
@@ -300,5 +542,11 @@ void cfspi_release_bus(uint bus, uint cs)
 		clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
 		break;
 	}
+#endif
+
+#ifdef CONFIG_MCF5441x
+	if (cs == 1)
+		clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
+#endif
 }
 #endif
diff --git a/arch/m68k/cpu/mcf5445x/speed.c b/arch/m68k/cpu/mcf5445x/speed.c
index 073b7ef..55d1c48 100644
--- a/arch/m68k/cpu/mcf5445x/speed.c
+++ b/arch/m68k/cpu/mcf5445x/speed.c
@@ -57,8 +57,10 @@ void clock_enter_limp(int lpdiv)
 	/* Round divider down to nearest power of two */
 	for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
 
+#ifdef CONFIG_MCF5445x
 	/* Apply the divider to the system clock */
 	clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
+#endif
 
 	/* Enable Limp Mode */
 	setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
@@ -81,19 +83,76 @@ void clock_exit_limp(void)
 		;
 }
 
-/*
- * get_clocks() fills in gd->cpu_clock and gd->bus_clk
- */
-int get_clocks(void)
+#ifdef CONFIG_MCF5441x
+void setup_5441x_clocks(void)
 {
+	ccm_t *ccm = (ccm_t *)MMAP_CCM;
+	pll_t *pll = (pll_t *)MMAP_PLL;
+	int temp, vco = 0, bootmod_ccr, pdr;
+
+	bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
+
+	switch (bootmod_ccr) {
+	case 0:
+		out_be32(&pll->pcr, 0x00000013);
+		out_be32(&pll->pdr, 0x00e70c61);
+		clock_exit_limp();
+		break;
+	case 2:
+		break;
+	case 3:
+		break;
+	}
+
+	/*Change frequency for Modelo SER1 USB host*/
+#ifdef CONFIG_LOW_MCFCLK
+	temp = in_be32(&pll->pcr);
+	temp &= ~0x3f;
+	temp |= 5;
+	out_be32(&pll->pcr, temp);
+
+	temp = in_be32(&pll->pdr);
+	temp &= ~0x001f0000;
+	temp |= 0x00040000;
+	out_be32(&pll->pdr, temp);
+	__asm__("tpf");
+#endif
 
+	setbits_be16(&ccm->misccr2, 0x02);
+
+	vco =  ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
+		CONFIG_SYS_INPUT_CLKSRC;
+	gd->vco_clk = vco;
+
+	gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
+
+	pdr = in_be32(&pll->pdr);
+	temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
+	gd->cpu_clk = vco / temp;	/* cpu clock */
+	gd->flb_clk = vco / temp;	/* FlexBus clock */
+	gd->flb_clk >>= 1;
+	if (in_be16(ccm->misccr2) & 2)		/* fsys/4 */
+		gd->flb_clk >>= 1;
+
+	temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
+	gd->bus_clk = vco / temp;	/* bus clock */
+
+}
+#endif
+
+#ifdef CONFIG_MCF5445x
+void setup_5445x_clocks(void)
+{
 	ccm_t *ccm = (ccm_t *)MMAP_CCM;
 	pll_t *pll = (pll_t *)MMAP_PLL;
 	int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
 	int pllmult_pci[] = { 12, 6, 16, 8 };
-	int vco = 0, bPci, temp, fbtemp, pcrvalue;
+	int vco = 0, temp, fbtemp, pcrvalue;
 	int *pPllmult = NULL;
 	u16 fbpll_mask;
+#ifdef CONFIG_PCI
+	int bPci;
+#endif
 
 #ifdef CONFIG_M54455EVB
 	u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
@@ -105,14 +164,16 @@ int get_clocks(void)
 	    ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
 		pPllmult = &pllmult_pci[0];
 		fbpll_mask = 3;		/* 11b */
+#ifdef CONFIG_PCI
 		bPci = 1;
+#endif
 	} else {
 		pPllmult = &pllmult_nopci[0];
 		fbpll_mask = 7;		/* 111b */
 #ifdef CONFIG_PCI
 		gd->pci_clk = 0;
-#endif
 		bPci = 0;
+#endif
 	}
 
 #ifdef CONFIG_M54455EVB
@@ -215,6 +276,22 @@ int get_clocks(void)
 #ifdef CONFIG_FSL_I2C
 	gd->i2c1_clk = gd->bus_clk;
 #endif
+}
+#endif
+
+/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
+int get_clocks(void)
+{
+#ifdef CONFIG_MCF5441x
+	setup_5441x_clocks();
+#endif
+#ifdef CONFIG_MCF5445x
+	setup_5445x_clocks();
+#endif
+
+#ifdef CONFIG_FSL_I2C
+	gd->i2c1_clk = gd->bus_clk;
+#endif
 
 	return (0);
 }
diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S
index 9906014..5fc944d 100644
--- a/arch/m68k/cpu/mcf5445x/start.S
+++ b/arch/m68k/cpu/mcf5445x/start.S
@@ -2,6 +2,9 @@
  * Copyright (C) 2003	Josef Baumgartner <josef.baumgartner@telex.de>
  * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
  *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -21,8 +24,10 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
 #include <asm-offsets.h>
 #include <config.h>
+#include <timestamp.h>
 #include "version.h"
 #include <asm/cache.h>
 
@@ -43,8 +48,9 @@
 	addl	#60,%sp;		/* space for 15 regs */ \
 	rte;
 
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 #define ASM_DRAMINIT	(asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_DRAMINIT_N	(asm_dram_init - TEXT_BASE)
 #define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
 #endif
 
@@ -55,10 +61,15 @@
  *	These vectors are to catch any un-intended traps.
  */
 _vectors:
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 
 INITSP:	.long	0		/* Initial SP	*/
+#ifdef CONFIG_CF_SBF
 INITPC:	.long	ASM_DRAMINIT	/* Initial PC 	*/
+#endif
+#ifdef CONFIG_SYS_NAND_BOOT
+INITPC:	.long	ASM_DRAMINIT_N	/* Initial PC 	*/
+#endif
 
 #else
 
@@ -95,7 +106,7 @@ vector1D:	.long	_FAULT	/* Autovector Level 5	*/
 vector1E:	.long	_FAULT	/* Autovector Level 6	*/
 vector1F:	.long	_FAULT	/* Autovector Level 7	*/
 
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 
 /* TRAP #0 - #15 */
 vector20_2F:
@@ -138,16 +149,26 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 #endif
 
-#if defined(CONFIG_CF_SBF)
+#if defined(CONFIG_SERIAL_BOOT)
 	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
 asm_sbf_img_hdr:
 	.long	0x00000000	/* checksum, not yet implemented */
-	.long	0x00030000	/* image length */
+	.long	0x00040000	/* image length */
 	.long	CONFIG_SYS_TEXT_BASE	/* image to be relocated at */
 
 asm_dram_init:
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
+#ifdef CONFIG_SYS_NAND_BOOT
+	/* for assembly stack */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+#endif
+
+#ifdef CONFIG_CF_SBF
 	move.l	#CONFIG_SYS_INIT_RAM_ADDR, %d0
 	movec	%d0, %VBR
 
@@ -180,7 +201,90 @@ asm_dram_init:
 	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
 	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+#endif			/* CONFIG_CF_SBF */
+
+#ifdef CONFIG_MCF5441x
+	/* TC: enable all peripherals,
+	in the future only enable certain peripherals */
+	move.l	#0xFC04002D, %a1
 
+#if defined(CONFIG_CF_SBF)
+	move.b	#23, (%a1)	/* dspi */
+#endif
+	move.b	#46, (%a1)	/* DDR */
+
+	/* slew settings */
+	move.l	#0xEC094060, %a1
+	move.b	#0, (%a1)
+
+	/* use vco instead of cpu*2 clock for ddr clock */
+	move.l	#0xEC09001A, %a1
+	move.w	#0xE01D, (%a1)
+
+	/* DDR settings */
+	move.l	#0xFC0B8180, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	move.l	#0xFC0B81AC, %a1
+	move.l	#0x01030203, (%a1)
+
+	move.l	#0xFC0B8000, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#0xFC0B8018, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#0xFC0B80A0, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#0xFC0B80B4, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#0xFC0B80E0, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#0xFC0B8024, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	jsr	asm_delay
+#endif		/* CONFIG_MCF5441x */
+
+#ifdef CONFIG_MCF5445x
 	/* Dram Initialization a1, a2, and d0 */
 	/* mscr sdram */
 	move.l	#0xFC0A4074, %a1
@@ -203,7 +307,9 @@ dramsz_loop:
 	add.l	#1, %d1
 	cmp.l	#1, %d2
 	bne	dramsz_loop
-
+#ifdef CONFIG_SYS_NAND_BOOT
+	beq	asm_nand_chk_status
+#endif
 	/* SDRAM Chip 0 and 1 */
 	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
 	or.l	%d1, (%a1)
@@ -275,7 +381,9 @@ dramsz_loop:
 
 	move.l	#2000, %d1
 	jsr	asm_delay
+#endif		/* CONFIG_MCF5445x */
 
+#ifdef CONFIG_CF_SBF
 	/*
 	 * DSPI Initialization
 	 * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h
@@ -286,15 +394,28 @@ dramsz_loop:
 	 */
 	/* Enable pins for DSPI mode - chip-selects are enabled later */
 asm_dspi_init:
+#ifdef CONFIG_MCF5441x
+	move.l	#0xEC09404E, %a1
+	move.l	#0xEC09404F, %a2
+	move.b	#0xFF, (%a1)
+	move.b	#0x80, (%a2)
+#endif
+
+#ifdef CONFIG_MCF5445x
 	move.l	#0xFC0A4063, %a0
 	move.b	#0x7F, (%a0)
-
+#endif
 	/* Configure DSPI module */
 	move.l	#0xFC05C000, %a0
 	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
 
 	move.l	#0xFC05C00C, %a0
+#ifdef CONFIG_MCF5441x
+	move.l	#0x3E000016, (%a0)
+#endif
+#ifdef CONFIG_MCF5445x
 	move.l	#0x3E000011, (%a0)
+#endif
 
 	move.l	#0xFC05C034, %a2	/* dtfr */
 	move.l	#0xFC05C03B, %a3	/* drfr */
@@ -379,19 +500,148 @@ asm_dspi_rd_status:
 
 	move.b	(%a3), %d1
 	rts
+#endif			/* CONFIG_CF_SBF */
+
+#ifdef CONFIG_SYS_NAND_BOOT
+	/* copy 4 boot pages to dram as soon as possible */
+	/* each page is 996 bytes (1056 total with 60 ECC bytes */
+	move.l  #0x00000000, %a1	/* src */
+	move.l	#TEXT_BASE, %a2		/* dst */
+	move.l	#0x3E0, %d0		/* sz in long */
+
+asm_boot_nand_copy:
+	move.l	(%a1)+, (%a2)+
+	subq.l	#1, %d0
+	bne	asm_boot_nand_copy
+
+	/* jump to memory and execute */
+	move.l	#(asm_nand_init), %a0
+	jmp	(%a0)
+
+asm_nand_init:
+	/* exit nand boot-mode */
+	move.l	#0xFC0FFF30, %a1
+	or.l	#0x00000040, %d1
+	move.l	%d1, (%a1)
+
+	/* initialize general use internal ram */
+	move.l #0, %d0
+	move.l #(CACR_STATUS), %a1	/* CACR */
+	move.l #(ICACHE_STATUS), %a2	/* icache */
+	move.l #(DCACHE_STATUS), %a3	/* dcache */
+	move.l %d0, (%a1)
+	move.l %d0, (%a2)
+	move.l %d0, (%a3)
+
+	/* invalidate and disable cache */
+	move.l	#0x01004100, %d0	/* Invalidate cache cmd */
+	movec	%d0, %CACR		/* Invalidate cache */
+	move.l	#0, %d0
+	movec	%d0, %ACR0
+	movec	%d0, %ACR1
+	movec	%d0, %ACR2
+	movec	%d0, %ACR3
+
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+
+	/* NAND port configuration */
+	move.l	#0xEC094048, %a1
+	move.b	#0xFD, (%a1)+
+	move.b	#0x5F, (%a1)+
+	move.b	#0x04, (%a1)+
+
+	/* reset nand */
+	move.l  #0xFC0FFF38, %a1	/* isr */
+	move.l  #0x000e0000, (%a1)
+	move.l	#0xFC0FFF08, %a2
+	move.l	#0x00000000, (%a2)+	/* car */
+	move.l	#0x11000000, (%a2)+	/* rar */
+	move.l	#0x00000000, (%a2)+	/* rpt */
+	move.l	#0x00000000, (%a2)+	/* rai */
+	move.l  #0xFC0FFF2c, %a2	/* cfg */
+	move.l  #0x00000000, (%a2)+	/* secsz */
+	move.l  #0x000e0681, (%a2)+
+	move.l  #0xFC0FFF04, %a2	/* cmd2 */
+	move.l  #0xFF404001, (%a2)
+	move.l  #0x000e0000, (%a1)
+
+	move.l	#0x2000, %d1
+	jsr	asm_delay
+
+	/* setup nand */
+	move.l  #0xFC0FFF00, %a1
+	move.l  #0x30700000, (%a1)+	/* cmd1 */
+	move.l  #0x007EF000, (%a1)+	/* cmd2 */
+
+	move.l  #0xFC0FFF2C, %a1
+	move.l  #0x00000841, (%a1)+	/* secsz */
+	move.l  #0x000e0681, (%a1)+	/* cfg */
+
+	move.l	#100, %d4		/* 100 pages ~200KB */
+	move.l	#4, %d2			/* start at 4 */
+	move.l  #0xFC0FFF04, %a0	/* cmd2 */
+	move.l  #0xFC0FFF0C, %a1	/* rar */
+	move.l	#(TEXT_BASE + 0xF80), %a2	/* dst */
+
+asm_nand_read:
+	move.l	#0x11000000, %d0	/* rar */
+	or.l	%d2, %d0
+	move.l	%d0, (%a1)
+	add.l	#1, %d2
+
+	move.l	(%a0), %d0		/* cmd2 */
+	or.l	#1, %d0
+	move.l	%d0, (%a0)
+
+	move.l	#0x200, %d1
+	jsr	asm_delay
+
+asm_nand_chk_status:
+	move.l  #0xFC0FFF38, %a4	/* isr */
+	move.l	(%a4), %d0
+	and.l	#0x40000000, %d0
+	tst.l	%d0
+	beq	asm_nand_chk_status
+
+	move.l  #0xFC0FFF38, %a4	/* isr */
+	move.l	(%a4), %d0
+	or.l	#0x000E0000, %d0
+	move.l	%d0, (%a4)
+
+	move.l	#0x200, %d3
+	move.l	#0xFC0FC000, %a3	/* buf 1 */
+asm_nand_copy:
+	move.l	(%a3)+, (%a2)+
+	subq.l	#1, %d3
+	bgt	asm_nand_copy
+
+	subq.l	#1, %d4
+	bgt	asm_nand_read
+
+	/* jump to memory and execute */
+	move.l	#(TEXT_BASE + 0x400), %a0
+	jmp	(%a0)
+
+#endif			/* CONFIG_SYS_NAND_BOOT */
 
 asm_delay:
 	nop
 	subq.l	#1, %d1
 	bne	asm_delay
 	rts
-#endif			/* CONFIG_CF_SBF */
+#endif			/* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */
 
 	.text
 	. = 0x400
 	.globl	_start
 _start:
-#if !defined(CONFIG_CF_SBF)
+#if !defined(CONFIG_SERIAL_BOOT)
 	nop
 	nop
 	move.w #0x2700,%sr		/* Mask off Interrupt */
@@ -418,12 +668,15 @@ _start:
 	movec	%d0, %ACR1
 	movec	%d0, %ACR2
 	movec	%d0, %ACR3
+#else
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1
+#endif
 
 	/* set stackpointer to end of internal ram to get some stackspace for
 	   the first c-code */
 	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
-#endif
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S
index ec65cae..d99747b 100644
--- a/arch/m68k/cpu/mcf547x_8x/start.S
+++ b/arch/m68k/cpu/mcf547x_8x/start.S
@@ -164,8 +164,8 @@ _start:
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
 
-	bsr cpu_init_f			/* run low-level CPU init code (from flash) */
-	bsr board_init_f		/* run low-level board init code (from flash) */
+	jbsr cpu_init_f			/* run low-level CPU init code (from flash) */
+	jbsr board_init_f		/* run low-level board init code (from flash) */
 
 	/* board_init_f() does not return */
 
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h
index 5c9bb30..f9e2d15 100644
--- a/arch/m68k/include/asm/cache.h
+++ b/arch/m68k/include/asm/cache.h
@@ -1,7 +1,7 @@
 /*
  * ColdFire cache
  *
- * Copyright (C) 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -37,10 +37,9 @@
 
 #if defined(CONFIG_MCF547x_8x) || defined(CONFIG_MCF5445x)
 #define CONFIG_CF_V4
-#if defined(CONFIG_MCF5441x)
+#elif defined(CONFIG_MCF5441x)
 #define CONFIG_CF_V4E		/* Four Extra ACRn */
 #endif
-#endif
 
 /* ***** CACR ***** */
 /* V2 Core */
@@ -87,7 +86,7 @@
 #endif				/* CONFIG_CF_V3 */
 
 /* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 
 #define CF_CACR_DEC		(1 << 31)
 #define CF_CACR_DW		(1 << 30)
@@ -113,7 +112,7 @@
 #define CF_CACR_IDSP		(1 << 7)
 #define CF_CACR_EUSP		(1 << 5)
 
-#ifdef CONFIG_MCF5445x
+#if defined(CONFIG_MCF5445x) || defined(CONFIG_MCF5441x)
 #define CF_CACR_IVO		(1 << 20)
 #define CF_CACR_SPA		(1 << 14)
 #else
@@ -148,7 +147,7 @@
 #endif				/* CONFIG_CF_V2 */
 
 /* V4 Core */
-#ifdef CONFIG_CF_V4
+#if defined(CONFIG_CF_V4) || defined(CONFIG_CF_V4E)
 #define CF_ACR_AMM		(1 << 10)
 #define CF_ACR_SP		(1 << 3)
 #endif				/* CONFIG_CF_V4 */
diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h
index cd55b83..0cdb11c 100644
--- a/arch/m68k/include/asm/global_data.h
+++ b/arch/m68k/include/asm/global_data.h
@@ -34,7 +34,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
 	unsigned long	bus_clk;
 #ifdef CONFIG_PCI
diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h
index e83ce08..2aab463 100644
--- a/arch/m68k/include/asm/immap.h
+++ b/arch/m68k/include/asm/immap.h
@@ -1,7 +1,7 @@
 /*
  * ColdFire Internal Memory Map and Defines
  *
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright 2004-2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  *
  * See file CREDITS for list of people who contributed to this
@@ -318,6 +318,47 @@
 #define CONFIG_SYS_NUM_IRQS		(128)
 #endif				/* CONFIG_M5329 && CONFIG_M5373 */
 
+#if defined(CONFIG_M54418)
+#include <asm/immap_5441x.h>
+#include <asm/m5441x.h>
+
+#define CONFIG_SYS_FEC0_IOBASE		(MMAP_FEC0)
+#define CONFIG_SYS_FEC1_IOBASE		(MMAP_FEC1)
+
+#if (CONFIG_SYS_UART_PORT < 4)
+#define CONFIG_SYS_UART_BASE		(MMAP_UART0 + \
+					(CONFIG_SYS_UART_PORT * 0x4000))
+#else
+#define CONFIG_SYS_UART_BASE		(MMAP_UART4 + \
+					((CONFIG_SYS_UART_PORT - 4) * 0x4000))
+#endif
+
+#define MMAP_DSPI			MMAP_DSPI0
+#define CONFIG_SYS_MCFRTC_BASE		(MMAP_RTC)
+
+/* Timer */
+#ifdef CONFIG_MCFTMR
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_DTMR0)
+#define CONFIG_SYS_TMR_BASE		(MMAP_DTMR1)
+#define CONFIG_SYS_TMRPND_REG	(((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0)
+#define CONFIG_SYS_TMRINTR_NO		(INT0_HI_DTMR1)
+#define CONFIG_SYS_TMRINTR_MASK		(INTC_IPRH_INT33)
+#define CONFIG_SYS_TMRINTR_PEND		(CONFIG_SYS_TMRINTR_MASK)
+#define CONFIG_SYS_TMRINTR_PRI		(6)
+#define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
+#endif
+
+#ifdef CONFIG_MCFPIT
+#define CONFIG_SYS_UDELAY_BASE		(MMAP_PIT0)
+#define CONFIG_SYS_PIT_BASE		(MMAP_PIT1)
+#define CONFIG_SYS_PIT_PRESCALE	(6)
+#endif
+
+#define CONFIG_SYS_INTR_BASE		(MMAP_INTC0)
+#define CONFIG_SYS_NUM_IRQS		(128)
+
+#endif				/* CONFIG_M54418 */
+
 #if defined(CONFIG_M54451) || defined(CONFIG_M54455)
 #include <asm/immap_5445x.h>
 #include <asm/m5445x.h>
diff --git a/arch/m68k/include/asm/immap_5441x.h b/arch/m68k/include/asm/immap_5441x.h
new file mode 100644
index 0000000..300f4d2
--- /dev/null
+++ b/arch/m68k/include/asm/immap_5441x.h
@@ -0,0 +1,387 @@
+/*
+ * MCF5441x Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __IMMAP_5441X__
+#define __IMMAP_5441X__
+
+/* Module Base Addresses */
+#define MMAP_XBS	0xFC004000
+#define MMAP_FBCS	0xFC008000
+#define MMAP_CAN0	0xFC020000
+#define MMAP_CAN1	0xFC024000
+#define MMAP_I2C1	0xFC038000
+#define MMAP_DSPI1	0xFC03C000
+#define MMAP_SCM	0xFC040000
+#define MMAP_PM		0xFC04002C
+#define MMAP_EDMA	0xFC044000
+#define MMAP_INTC0	0xFC048000
+#define MMAP_INTC1	0xFC04C000
+#define MMAP_INTC2	0xFC050000
+#define MMAP_IACK	0xFC054000
+#define MMAP_I2C0	0xFC058000
+#define MMAP_DSPI0	0xFC05C000
+#define MMAP_UART0	0xFC060000
+#define MMAP_UART1	0xFC064000
+#define MMAP_UART2	0xFC068000
+#define MMAP_UART3	0xFC06C000
+#define MMAP_DTMR0	0xFC070000
+#define MMAP_DTMR1	0xFC074000
+#define MMAP_DTMR2	0xFC078000
+#define MMAP_DTMR3	0xFC07C000
+#define MMAP_PIT0	0xFC080000
+#define MMAP_PIT1	0xFC084000
+#define MMAP_PIT2	0xFC088000
+#define MMAP_PIT3	0xFC08C000
+#define MMAP_EPORT0	0xFC090000
+#define MMAP_ADC	0xFC094000
+#define MMAP_DAC0	0xFC098000
+#define MMAP_DAC1	0xFC09C000
+#define MMAP_RRTC	0xFC0A8000
+#define MMAP_SIM	0xFC0AC000
+#define MMAP_USBOTG	0xFC0B0000
+#define MMAP_USBEHCI	0xFC0B4000
+#define MMAP_SDRAM	0xFC0B8000
+#define MMAP_SSI0	0xFC0BC000
+#define MMAP_PLL	0xFC0C0000
+#define MMAP_RNG	0xFC0C4000
+#define MMAP_SSI1	0xFC0C8000
+#define MMAP_ESDHC	0xFC0CC000
+#define MMAP_FEC0	0xFC0D4000
+#define MMAP_FEC1	0xFC0D8000
+#define MMAP_L2_SW0	0xFC0DC000
+#define MMAP_L2_SW1	0xFC0E0000
+
+#define MMAP_NFC_RAM	0xFC0FC000
+#define MMAP_NFC	0xFC0FF000
+
+#define MMAP_1WIRE	0xEC008000
+#define MMAP_I2C2	0xEC010000
+#define MMAP_I2C3	0xEC014000
+#define MMAP_I2C4	0xEC018000
+#define MMAP_I2C5	0xEC01C000
+#define MMAP_DSPI2	0xEC038000
+#define MMAP_DSPI3	0xEC03C000
+#define MMAP_UART4	0xEC060000
+#define MMAP_UART5	0xEC064000
+#define MMAP_UART6	0xEC068000
+#define MMAP_UART7	0xEC06C000
+#define MMAP_UART8	0xEC070000
+#define MMAP_UART9	0xEC074000
+#define MMAP_RCM	0xEC090000
+#define MMAP_CCM	0xEC090000
+#define MMAP_GPIO	0xEC094000
+
+#include <asm/coldfire/crossbar.h>
+#include <asm/coldfire/dspi.h>
+#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
+#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
+#include <asm/coldfire/ssi.h>
+
+/* Serial Boot Facility (SBF) */
+typedef struct sbf {
+	u8 resv0[0x18];
+	u16 sbfsr;		/* Serial Boot Facility Status */
+	u8 resv1[0x6];
+	u16 sbfcr;		/* Serial Boot Facility Control */
+} sbf_t;
+
+/* Reset Controller Module (RCM) */
+typedef struct rcm {
+	u8 rcr;
+	u8 rsr;
+} rcm_t;
+
+/* Chip Configuration Module (CCM) */
+typedef struct ccm {
+	u8 ccm_resv0[0x4];	/* 0x00 */
+	u16 ccr;		/* 0x04 Chip Configuration */
+	u8 resv1[0x2];		/* 0x06 */
+	u16 rcon;		/* 0x08 Reset Configuration */
+	u16 cir;		/* 0x0A Chip Identification */
+	u8 resv2[0x2];		/* 0x0C */
+	u16 misccr;		/* 0x0E Miscellaneous Control */
+	u16 cdrh;		/* 0x10 Clock Divider */
+	u16 cdrl;		/* 0x12 Clock Divider */
+	u16 uocsr;		/* 0x14 USB On-the-Go Controller Status */
+	u16 uhcsr;		/* 0x16 */
+	u16 misccr3;		/* 0x18 */
+	u16 misccr2;		/* 0x1A */
+	u16 adctsr;		/* 0x1C */
+	u16 dactsr;		/* 0x1E */
+	u16 sbfsr;		/* 0x20 */
+	u16 sbfcr;		/* 0x22 */
+	u32 fnacr;		/* 0x24 */
+} ccm_t;
+
+/* General Purpose I/O Module (GPIO) */
+typedef struct gpio {
+	u8 podr_a;		/* 0x00 */
+	u8 podr_b;		/* 0x01 */
+	u8 podr_c;		/* 0x02 */
+	u8 podr_d;		/* 0x03 */
+	u8 podr_e;		/* 0x04 */
+	u8 podr_f;		/* 0x05 */
+	u8 podr_g;		/* 0x06 */
+	u8 podr_h;		/* 0x07 */
+	u8 podr_i;		/* 0x08 */
+	u8 podr_j;		/* 0x09 */
+	u8 podr_k;		/* 0x0A */
+	u8 rsvd0;		/* 0x0B */
+
+	u8 pddr_a;		/* 0x0C */
+	u8 pddr_b;		/* 0x0D */
+	u8 pddr_c;		/* 0x0E */
+	u8 pddr_d;		/* 0x0F */
+	u8 pddr_e;		/* 0x10 */
+	u8 pddr_f;		/* 0x11 */
+	u8 pddr_g;		/* 0x12 */
+	u8 pddr_h;		/* 0x13 */
+	u8 pddr_i;		/* 0x14 */
+	u8 pddr_j;		/* 0x15 */
+	u8 pddr_k;		/* 0x16 */
+	u8 rsvd1;		/* 0x17 */
+
+	u8 ppdsdr_a;		/* 0x18 */
+	u8 ppdsdr_b;		/* 0x19 */
+	u8 ppdsdr_c;		/* 0x1A */
+	u8 ppdsdr_d;		/* 0x1B */
+	u8 ppdsdr_e;		/* 0x1C */
+	u8 ppdsdr_f;		/* 0x1D */
+	u8 ppdsdr_g;		/* 0x1E */
+	u8 ppdsdr_h;		/* 0x1F */
+	u8 ppdsdr_i;		/* 0x20 */
+	u8 ppdsdr_j;		/* 0x21 */
+	u8 ppdsdr_k;		/* 0x22 */
+	u8 rsvd2;		/* 0x23 */
+
+	u8 pclrr_a;		/* 0x24 */
+	u8 pclrr_b;		/* 0x25 */
+	u8 pclrr_c;		/* 0x26 */
+	u8 pclrr_d;		/* 0x27 */
+	u8 pclrr_e;		/* 0x28 */
+	u8 pclrr_f;		/* 0x29 */
+	u8 pclrr_g;		/* 0x2A */
+	u8 pclrr_h;		/* 0x2B */
+	u8 pclrr_i;		/* 0x2C */
+	u8 pclrr_j;		/* 0x2D */
+	u8 pclrr_k;		/* 0x2E */
+	u8 rsvd3;		/* 0x2F */
+
+	u16 pcr_a;		/* 0x30 */
+	u16 pcr_b;		/* 0x32 */
+	u16 pcr_c;		/* 0x34 */
+	u16 pcr_d;		/* 0x36 */
+	u16 pcr_e;		/* 0x38 */
+	u16 pcr_f;		/* 0x3A */
+	u16 pcr_g;		/* 0x3C */
+	u16 pcr_h;		/* 0x3E */
+	u16 pcr_i;		/* 0x40 */
+	u16 pcr_j;		/* 0x42 */
+	u16 pcr_k;		/* 0x44 */
+	u16 rsvd4;		/* 0x46 */
+
+	u8 par_fbctl;		/* 0x48 */
+	u8 par_be;		/* 0x49 */
+	u8 par_cs;		/* 0x4A */
+	u8 par_cani2c;		/* 0x4B */
+	u8 par_irqh;		/* 0x4C */
+	u8 par_irql;		/* 0x4D */
+	u8 par_dspi0;		/* 0x4E */
+	u8 par_dspiow;		/* 0x4F */
+	u8 par_timer;		/* 0x50 */
+	u8 par_uart2;		/* 0x51 */
+	u8 par_uart1;		/* 0x52 */
+	u8 par_uart0;		/* 0x53 */
+	u8 par_sdhch;		/* 0x54 */
+	u8 par_sdhcl;		/* 0x55 */
+	u8 par_simp0h;		/* 0x56 */
+	u8 par_simp1h;		/* 0x57 */
+	u8 par_ssi0h;		/* 0x58 */
+	u8 par_ssi0l;		/* 0x59 */
+	u8 par_dbg1h;		/* 0x5A */
+	u8 par_dbg0h;		/* 0x5B */
+	u8 par_dbgl;		/* 0x5C */
+	u8 rsvd5;		/* 0x5D */
+	u8 par_fec;		/* 0x5E */
+	u8 rsvd6;		/* 0x5F */
+
+	u8 mscr_sdram;		/* 0x60 */
+	u8 rsvd7[3];		/* 0x61-0x63 */
+
+	u8 srcr_fb1;		/* 0x64 */
+	u8 srcr_fb2;		/* 0x65 */
+	u8 srcr_fb3;		/* 0x66 */
+	u8 srcr_fb4;		/* 0x67 */
+	u8 srcr_dspiow;		/* 0x68 */
+	u8 srcr_cani2c;		/* 0x69 */
+	u8 srcr_irq;		/* 0x6A */
+	u8 srcr_timer;		/* 0x6B */
+	u8 srcr_uart;		/* 0x6C */
+	u8 srcr_fec;		/* 0x6D */
+	u8 srcr_sdhc;		/* 0x6E */
+	u8 srcr_simp0;		/* 0x6F */
+	u8 srcr_ssi0;		/* 0x70 */
+	u8 rsvd8[3];		/* 0x71-0x73 */
+
+	u16 urts_pol;		/* 0x74 */
+	u16 ucts_pol;		/* 0x76 */
+	u16 utxd_wom;		/* 0x78 */
+	u32 urxd_wom;		/* 0x7c */
+
+	u32 hcr1;		/* 0x80 */
+	u32 hcr0;		/* 0x84 */
+} gpio_t;
+
+/* SDRAM Controller (SDRAMC) */
+typedef struct sdramc {
+	u32 cr00;		/* 0x00 */
+	u32 cr01;		/* 0x04 */
+	u32 cr02;		/* 0x08 */
+	u32 cr03;		/* 0x0C */
+	u32 cr04;		/* 0x10 */
+	u32 cr05;		/* 0x14 */
+	u32 cr06;		/* 0x18 */
+	u32 cr07;		/* 0x1C */
+
+	u32 cr08;		/* 0x20 */
+	u32 cr09;		/* 0x24 */
+	u32 cr10;		/* 0x28 */
+	u32 cr11;		/* 0x2C */
+	u32 cr12;		/* 0x30 */
+	u32 cr13;		/* 0x34 */
+	u32 cr14;		/* 0x38 */
+	u32 cr15;		/* 0x3C */
+
+	u32 cr16;		/* 0x40 */
+	u32 cr17;		/* 0x44 */
+	u32 cr18;		/* 0x48 */
+	u32 cr19;		/* 0x4C */
+	u32 cr20;		/* 0x50 */
+	u32 cr21;		/* 0x54 */
+	u32 cr22;		/* 0x58 */
+	u32 cr23;		/* 0x5C */
+
+	u32 cr24;		/* 0x60 */
+	u32 cr25;		/* 0x64 */
+	u32 cr26;		/* 0x68 */
+	u32 cr27;		/* 0x6C */
+	u32 cr28;		/* 0x70 */
+	u32 cr29;		/* 0x74 */
+	u32 cr30;		/* 0x78 */
+	u32 cr31;		/* 0x7C */
+
+	u32 cr32;		/* 0x80 */
+	u32 cr33;		/* 0x84 */
+	u32 cr34;		/* 0x88 */
+	u32 cr35;		/* 0x8C */
+	u32 cr36;		/* 0x90 */
+	u32 cr37;		/* 0x94 */
+	u32 cr38;		/* 0x98 */
+	u32 cr39;		/* 0x9C */
+
+	u32 cr40;		/* 0xA0 */
+	u32 cr41;		/* 0xA4 */
+	u32 cr42;		/* 0xA8 */
+	u32 cr43;		/* 0xAC */
+	u32 cr44;		/* 0xB0 */
+	u32 cr45;		/* 0xB4 */
+	u32 cr46;		/* 0xB8 */
+	u32 cr47;		/* 0xBC */
+	u32 cr48;		/* 0xC0 */
+	u32 cr49;		/* 0xC4 */
+	u32 cr50;		/* 0xC8 */
+	u32 cr51;		/* 0xCC */
+	u32 cr52;		/* 0xD0 */
+	u32 cr53;		/* 0xD4 */
+	u32 cr54;		/* 0xD8 */
+	u32 cr55;		/* 0xDC */
+	u32 cr56;		/* 0xE0 */
+	u32 cr57;		/* 0xE4 */
+	u32 cr58;		/* 0xE8 */
+	u32 cr59;		/* 0xEC */
+	u32 cr60;		/* 0xF0 */
+	u32 cr61;		/* 0xF4 */
+	u32 cr62;		/* 0xF8 */
+	u32 cr63;		/* 0xFC */
+
+	u32 rsvd3[32];		/* 0xF4-0x1A8 */
+
+	u32 rcrcr;		/* 0x180 */
+	u32 swrcr;		/* 0x184 */
+	u32 rcr;		/* 0x188 */
+	u32 msovr;		/* 0x18C */
+	u32 rcrdbg;		/* 0x190 */
+	u32 sl0adj;		/* 0x194 */
+	u32 sl1adj;		/* 0x198 */
+	u32 sl2adj;		/* 0x19C */
+	u32 sl3adj;		/* 0x1A0 */
+	u32 sl4adj;		/* 0x1A4 */
+	u32 flight_tm;		/* 0x1A8 */
+	u32 padcr;		/* 0x1AC */
+} sdramc_t;
+
+/* Phase Locked Loop (PLL) */
+typedef struct pll {
+	u32 pcr;		/* Control */
+	u32 pdr;		/* Divider */
+	u32 psr;		/* Status */
+} pll_t;
+
+typedef struct scm {
+	u8 rsvd1[19];		/* 0x00 - 0x12 */
+	u8 wcr;			/* 0x13 */
+	u16 rsvd2;		/* 0x14 - 0x15 */
+	u16 cwcr;		/* 0x16 */
+	u8 rsvd3[3];		/* 0x18 - 0x1A */
+	u8 cwsr;		/* 0x1B */
+	u8 rsvd4[3];		/* 0x1C - 0x1E */
+	u8 scmisr;		/* 0x1F */
+	u32 rsvd5;		/* 0x20 - 0x23 */
+	u32 bcr;		/* 0x24 */
+	u8 rsvd6[72];		/* 0x28 - 0x6F */
+	u32 cfadr;		/* 0x70 */
+	u8 rsvd7;		/* 0x74 */
+	u8 cfier;		/* 0x75 */
+	u8 cfloc;		/* 0x76 */
+	u8 cfatr;		/* 0x77 */
+	u32 rsvd8;		/* 0x78 - 0x7B */
+	u32 cfdtr;		/* 0x7C */
+} scm_t;
+
+typedef struct pm {
+	u8 pmsr0;		/* */
+	u8 pmcr0;
+	u8 pmsr1;
+	u8 pmcr1;
+	u32 pmhr0;
+	u32 pmlr0;
+	u32 pmhr1;
+	u32 pmlr1;
+} pm_t;
+
+#endif				/* __IMMAP_5441X__ */
diff --git a/arch/m68k/include/asm/m5441x.h b/arch/m68k/include/asm/m5441x.h
new file mode 100644
index 0000000..f5c82d4
--- /dev/null
+++ b/arch/m68k/include/asm/m5441x.h
@@ -0,0 +1,887 @@
+/*
+ * MCF5441X Internal Memory Map
+ *
+ * Copyright 2010-2012 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MCF5441X__
+#define __MCF5441X__
+
+/* Interrupt Controller (INTC) */
+#define INT0_LO_RSVD0			(0)
+#define INT0_LO_EPORT1			(1)
+#define INT0_LO_EPORT2			(2)
+#define INT0_LO_EPORT3			(3)
+#define INT0_LO_EPORT4			(4)
+#define INT0_LO_EPORT5			(5)
+#define INT0_LO_EPORT6			(6)
+#define INT0_LO_EPORT7			(7)
+#define INT0_LO_EDMA_00		(8)
+#define INT0_LO_EDMA_01		(9)
+#define INT0_LO_EDMA_02		(10)
+#define INT0_LO_EDMA_03		(11)
+#define INT0_LO_EDMA_04		(12)
+#define INT0_LO_EDMA_05		(13)
+#define INT0_LO_EDMA_06		(14)
+#define INT0_LO_EDMA_07		(15)
+#define INT0_LO_EDMA_08		(16)
+#define INT0_LO_EDMA_09		(17)
+#define INT0_LO_EDMA_10		(18)
+#define INT0_LO_EDMA_11		(19)
+#define INT0_LO_EDMA_12		(20)
+#define INT0_LO_EDMA_13		(21)
+#define INT0_LO_EDMA_14		(22)
+#define INT0_LO_EDMA_15		(23)
+#define INT0_LO_EDMA_ERR		(24)
+#define INT0_LO_SCM			(25)
+#define INT0_LO_UART0			(26)
+#define INT0_LO_UART1			(27)
+#define INT0_LO_UART2			(28)
+#define INT0_LO_UART3			(29)
+#define INT0_LO_I2C0			(30)
+#define INT0_LO_DSPI0			(31)
+#define INT0_HI_DTMR0			(32)
+#define INT0_HI_DTMR1			(33)
+#define INT0_HI_DTMR2			(34)
+#define INT0_HI_DTMR3			(35)
+#define INT0_HI_MACNET0_TXF		(36)
+#define INT0_HI_MACNET0_TXB		(37)
+#define INT0_HI_MACNET0_UN		(38)
+#define INT0_HI_MACNET0_RL		(39)
+#define INT0_HI_MACNET0_RXF		(40)
+#define INT0_HI_MACNET0_RXB		(41)
+#define INT0_HI_MACNET0_MII		(42)
+#define INT0_HI_MACNET0_LC		(43)
+/* not used 44 */
+#define INT0_HI_MACNET0_GRA		(45)
+#define INT0_HI_MACNET0_EBERR		(46)
+#define INT0_HI_MACNET0_BABT		(47)
+#define INT0_HI_MACNET0_BABR		(48)
+#define INT0_HI_MACNET1_TXF		(49)
+#define INT0_HI_MACNET1_TXB		(50)
+#define INT0_HI_MACNET1_UN		(51)
+#define INT0_HI_MACNET1_RL		(52)
+#define INT0_HI_MACNET1_RXF		(53)
+#define INT0_HI_MACNET1_RXB		(54)
+#define INT0_HI_MACNET1_MII		(55)
+#define INT0_HI_MACNET1_LC		(56)
+/* not used 57 */
+#define INT0_HI_MACNET1_GRA		(58)
+#define INT0_HI_MACNET1_EBERR		(59)
+#define INT0_HI_MACNET1_BABT		(60)
+#define INT0_HI_MACNET1_BABR		(61)
+#define INT0_HI_SCMIR			(62)
+#define INT0_HI_OW			(63)
+
+#define INT1_LO_CAN0_IFG		(0)
+#define INT1_LO_CAN0_BOFF		(1)
+/* not used 2 */
+#define INT1_LO_CAN0_TXRXWRN		(3)
+#define INT1_LO_CAN1_IFG		(4)
+#define INT1_LO_CAN1_BOFF		(5)
+/* not used 6 */
+#define INT1_LO_CAN1_TXRXWRN		(7)
+#define INT1_LO_EDMA_16		(8)
+#define INT1_LO_EDMA_17		(9)
+#define INT1_LO_EDMA_18		(10)
+#define INT1_LO_EDMA_19		(11)
+#define INT1_LO_EDMA_20		(12)
+#define INT1_LO_EDMA_21		(13)
+#define INT1_LO_EDMA_22		(14)
+#define INT1_LO_EDMA_23		(15)
+#define INT1_LO_EDMA_24		(16)
+#define INT1_LO_EDMA_25		(17)
+#define INT1_LO_EDMA_26		(18)
+#define INT1_LO_EDMA_27		(19)
+#define INT1_LO_EDMA_28		(20)
+#define INT1_LO_EDMA_29		(21)
+#define INT1_LO_EDMA_30		(22)
+#define INT1_LO_EDMA_31		(23)
+#define INT1_LO_EDMA_32		(24)
+#define INT1_LO_EDMA_33		(25)
+#define INT1_LO_EDMA_34		(26)
+#define INT1_LO_EDMA_35		(27)
+#define INT1_LO_EDMA_36		(28)
+#define INT1_LO_EDMA_37		(29)
+#define INT1_LO_EDMA_38		(30)
+#define INT1_LO_EDMA_39		(31)
+#define INT1_LO_EDMA_40		(32)
+#define INT1_HI_EDMA_41		(33)
+#define INT1_HI_EDMA_42		(34)
+#define INT1_HI_EDMA_43		(35)
+#define INT1_HI_EDMA_44		(36)
+#define INT1_HI_EDMA_45		(37)
+#define INT1_HI_EDMA_46		(38)
+#define INT1_HI_EDMA_47		(39)
+#define INT1_HI_EDMA_48		(40)
+#define INT1_HI_EDMA_49		(41)
+#define INT1_HI_EDMA_50		(42)
+#define INT1_HI_EDMA_51		(43)
+#define INT1_HI_EDMA_52		(44)
+#define INT1_HI_EDMA_53		(45)
+#define INT1_HI_EDMA_54		(46)
+#define INT1_HI_EDMA_55		(47)
+#define INT1_HI_UART4			(48)
+#define INT1_HI_UART5			(49)
+#define INT1_HI_UART6			(50)
+#define INT1_HI_UART7			(51)
+#define INT1_HI_UART8			(52)
+#define INT1_HI_UART9			(53)
+#define INT1_HI_DSPI1			(54)
+#define INT1_HI_DSPI2			(55)
+#define INT1_HI_DSPI3			(56)
+#define INT1_HI_I2C1			(57)
+#define INT1_HI_I2C2			(58)
+#define INT1_HI_I2C3			(59)
+#define INT1_HI_I2C4			(60)
+#define INT1_HI_I2C5			(61)
+
+#define INT2_LO_EDMA56_63		(0)
+#define INT2_LO_PWM_SM0SR_CF		(1)
+#define INT2_LO_PWM_SM1SR_CF		(2)
+#define INT2_LO_PWM_SM2SR_CF		(3)
+#define INT2_LO_PWM_SM3SR_CF		(4)
+#define INT2_LO_PWM_SM0SR_RF		(5)
+#define INT2_LO_PWM_SM1SR_RF		(6)
+#define INT2_LO_PWM_SM2SR_RF		(7)
+#define INT2_LO_PWM_SM3SR_RF		(8)
+#define INT2_LO_PWM_FSR		(9)
+#define INT2_LO_PWM_SMSR_REF		(10)
+#define INT2_LO_PLL_SR_LOCF		(11)
+#define INT2_LO_PLL_SR_LOLF		(12)
+#define INT2_LO_PIT0_PIF		(13)
+#define INT2_LO_PIT1_PIF		(14)
+#define INT2_LO_PIT2_PIF		(15)
+#define INT2_LO_PIT3_PIF		(16)
+#define INT2_LO_USBOTG_USBSTS		(17)
+#define INT2_LO_USBH_USBSTS		(18)
+/* not used 19-20 */
+#define INT2_LO_SSI0			(21)
+#define INT2_LO_SSI1			(22)
+#define INT2_LO_NFC			(23)
+/* not used 24-25 */
+#define INT2_LO_RTC			(26)
+#define INT2_LO_CCM_UOCSR		(27)
+#define INT2_LO_RNG_EI			(28)
+#define INT2_LO_SIM1_DATA		(29)
+#define INT2_LO_SIM1			(30)
+#define INT2_LO_SDHC			(31)
+/* not used 32-37 */
+#define INT2_HI_L2SW_BERR		(38)
+#define INT2_HI_L2SW_RXB		(39)
+#define INT2_HI_L2SW_RXF		(40)
+#define INT2_HI_L2SW_TXB		(41)
+#define INT2_HI_L2SW_TXF		(42)
+#define INT2_HI_L2SW_QM		(43)
+#define INT2_HI_L2SW_OD0		(44)
+#define INT2_HI_L2SW_OD1		(45)
+#define INT2_HI_L2SW_OD2		(46)
+#define INT2_HI_L2SW_LRN		(47)
+#define INT2_HI_MACNET0_TS		(48)
+#define INT2_HI_MACNET0_WAKE		(49)
+#define INT2_HI_MACNET0_PLR		(50)
+/* not used 51-54 */
+#define INT2_HI_MACNET1_TS		(51)
+#define INT2_HI_MACNET1_WAKE		(52)
+#define INT2_HI_MACNET1_PLR		(53)
+
+/* Serial Boot Facility (SBF) */
+#define SBF_SBFCR_BLDIV(x)		(((x)&0x000F))
+#define SBF_SBFCR_FR			(0x0010)
+
+/* Reset Controller Module (RCM) */
+#define RCM_RCR_SOFTRST		(0x80)
+#define RCM_RCR_FRCRSTOUT		(0x40)
+
+#define RCM_RSR_SOFT			(0x20)
+#define RCM_RSR_LOC			(0x10)
+#define RCM_RSR_POR			(0x08)
+#define RCM_RSR_EXT			(0x04)
+#define RCM_RSR_WDR_CORE		(0x02)
+#define RCM_RSR_LOL			(0x01)
+
+/* Chip Configuration Module (CCM) */
+#define CCM_CCR_BOOTMOD		(0xC000)
+#define CCM_CCR_PLLMULT		(0x0FC0)
+#define CCM_CCR_BOOTPS			(0x0030)
+#define CCM_CCR_BOOTPS_32		(0x0000)
+#define CCM_CCR_BOOTPS_16		(0x0020)
+#define CCM_CCR_BOOTPS_8		(0x0010)
+#define CCM_CCR_BOOTPS_		(0x0000)
+#define CCM_CCR_ALESEL			(0x0008)
+#define CCM_CCR_OSCMOD			(0x0004)
+#define CCM_CCR_PLLMOD			(0x0002)
+#define CCM_CCR_BOOTMEM		(0x0001)
+
+#define CCM_CIR_PIN_MASK		(0xFFC0)
+#define CCM_CIR_PRN_MASK		(0x003F)
+#define CCM_CIR_PIN_MCF54410		(0x9F<<6)
+#define CCM_CIR_PIN_MCF54415		(0xA0<<6)
+#define CCM_CIR_PIN_MCF54416		(0xA1<<6)
+#define CCM_CIR_PIN_MCF54417		(0xA2<<6)
+#define CCM_CIR_PIN_MCF54418		(0xA3<<6)
+
+#define CCM_MISCCR_PWM_EXTCLK(x)	(((x)&(0x0003)<<14)
+#define CCM_MISCCR_PWM_EXTCLK_MASK	(0x3FFF)
+#define CCM_MISCCR_PWM_EXTCLK_TMR0	(0x0000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR1	(0x4000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR2	(0x8000)
+#define CCM_MISCCR_PWM_EXTCLK_TMR3	(0xC000)
+#define CCM_MISCCR_LIMP		(0x1000)
+#define CCM_MISCCR_BME			(0x0800)
+#define CCM_MISCCR_BMT(x)		(((x)&0x0007)<<8)
+#define CCM_MISCCR_BMT_65536		(0)
+#define CCM_MISCCR_BMT_32768		(1)
+#define CCM_MISCCR_BMT_16384		(2)
+#define CCM_MISCCR_BMT_8192		(3)
+#define CCM_MISCCR_BMT_4096		(4)
+#define CCM_MISCCR_BMT_2048		(5)
+#define CCM_MISCCR_BMT_1024		(6)
+#define CCM_MISCCR_BMT_512		(7)
+#define CCM_MISCCR_SDHCSRC		(0x0040)
+#define CCM_MISCCR_SSI1SRC		(0x0020)
+#define CCM_MISCCR_SSI0SRC		(0x0010)
+#define CCM_MISCCR_USBHOC		(0x0008)
+#define CCM_MISCCR_USBOOC		(0x0004)
+#define CCM_MISCCR_USBPUE		(0x0002)
+#define CCM_MISCCR_USBSRC		(0x0001)
+
+#define CCM_CDRH_SSI0DIV(x)		(((x)&0x00FF)<<8)
+#define CCM_CDRH_SSI0DIV_MASK		(0x00FF)
+#define CCM_CDRH_SSI1DIV(x)		(((x)&0x00FF))
+#define CCM_CDRH_SSI1DIV_MASK		(0xFF00)
+#define CCM_CDRL_LPDIV(x)		(((x)&0x000F)<<8)
+#define CCM_CDRL_LPDIV_MASK		(0xFF0F)
+#define CCM_CDR_LPDIV(x)		CCM_CDRL_LPDIV(x)
+
+#define CCM_UOCSR_DPPD			(0x2000)
+#define CCM_UOCSR_DMPD			(0x1000)
+#define CCM_UOCSR_DRV_VBUS		(0x0800)
+#define CCM_UOCSR_CRG_VBUS		(0x0400)
+#define CCM_UOCSR_DCR_VBUS		(0x0200)
+#define CCM_UOCSR_DPPU			(0x0100)
+#define CCM_UOCSR_AVLD			(0x0080)
+#define CCM_UOCSR_BVLD			(0x0040)
+#define CCM_UOCSR_VVLD			(0x0020)
+#define CCM_UOCSR_SEND			(0x0010)
+#define CCM_UOCSR_PWRFLT		(0x0008)
+#define CCM_UOCSR_WKUP			(0x0004)
+#define CCM_UOCSR_UOMIE		(0x0002)
+#define CCM_UOCSR_XPDE			(0x0001)
+
+#define CCM_UHCSR_DRV_VBUS		(0x0010)
+#define CCM_UHCSR_PWRFLT		(0x0008)
+#define CCM_UHCSR_WKUP			(0x0004)
+#define CCM_UHCSR_UOMIE		(0x0002)
+#define CCM_UHCSR_XPDE			(0x0001)
+
+#define CCM_MISCCR3_TMR_ENET		(0x1000)
+#define CCM_MISCCR3_ENETCLK(x)		(((x)&7)<<8)
+#define CCM_MISCCR3_ENETCLK_MASK	(0xF8FF)
+#define CCM_MISCCR3_ENETCLK_MII	(0x0700)
+#define CCM_MISCCR3_ENETCLK_OSC	(0x0600)
+#define CCM_MISCCR3_ENETCLK_USB	(0x0500)
+#define CCM_MISCCR3_ENETCLK_TMR3	(0x0400)
+#define CCM_MISCCR3_ENETCLK_TMR2	(0x0300)
+#define CCM_MISCCR3_ENETCLK_TMR1	(0x0200)
+#define CCM_MISCCR3_ENETCLK_TMR0	(0x0100)
+#define CCM_MISCCR3_ENETCLK_INTBUS	(0x0000)
+
+#define CCM_MISCCR2_EXTCLKBYP		(0x8000)
+#define CCM_MISCCR2_DDR2CLK		(0x4000)
+#define CCM_MISCCR2_RGPIO_HALF		(0x2000)
+#define CCM_MISCCR2_SWTSCR		(0x1000)
+#define CCM_MISCCR2_PLLMODE(x)		(((x)&7)<<8)
+#define CCM_MISCCR2_PLLMODE_MASK	(0xF8FF)
+#define CCM_MISCCR2_DCCBYP		(0x0080)
+#define CCM_MISCCR2_DAC1SEL		(0x0040)
+#define CCM_MISCCR2_DAC0SEL		(0x0020)
+#define CCM_MISCCR2_ADCEN		(0x0010)
+#define CCM_MISCCR2_ADC7SEL		(0x0008)
+#define CCM_MISCCR2_ADC3SEL		(0x0004)
+#define CCM_MISCCR2_FBHALF		(0x0002)
+#define CCM_MISCCR2_ULPI		(0x0001)
+
+#define CCM_FNACR_PCR(x)		(((x)&0x0F)<<24)
+#define CCM_FNACR_PCR_MASK		(0xF0FFFFFF)
+#define CCM_FNACR_MCC(x)		((x)&0xFFFF)
+#define CCM_FNACR_MCC_MASK		(0xFFFF0000)
+
+/* General Purpose I/O Module (GPIO) */
+#define GPIO_PAR_FBCTL_ALE(x)		(((x)&3)<<6)
+#define GPIO_PAR_FBCTL_ALE_MASK	(0x3F)
+#define GPIO_PAR_FBCTL_ALE_FB_ALE	(0xC0)
+#define GPIO_PAR_FBCTL_ALE_FB_TS	(0x80)
+#define GPIO_PAR_FBCTL_ALE_GPIO	(0x00)
+#define GPIO_PAR_FBCTL_OE(x)		(((x)&3)<<4)
+#define GPIO_PAR_FBCTL_OE_MASK		(0xCF)
+#define GPIO_PAR_FBCTL_OE_FB_OE	(0x30)
+#define GPIO_PAR_FBCTL_OE_FB_TBST	(0x20)
+#define GPIO_PAR_FBCTL_OE_NFC_RE	(0x20)
+#define GPIO_PAR_FBCTL_OE_GPIO		(0x00)
+#define GPIO_PAR_FBCTL_FBCLK		(0x08)
+#define GPIO_PAR_FBCTL_RW		(0x04)
+#define GPIO_PAR_FBCTL_TA(x)		((x)&3)
+#define GPIO_PAR_FBCTL_TA_MASK		(0xFC)
+#define GPIO_PAR_FBCTL_TA_TA		(0x03)
+#define GPIO_PAR_FBCTL_TA_NFC_RB	(0x01)
+#define GPIO_PAR_FBCTL_TA_GPIO		(0x00)
+
+#define GPIO_PAR_BE_BS3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_BE_BE3_MASK		(0x3F)
+#define GPIO_PAR_BE_BE3_BE3		(0xC0)
+#define GPIO_PAR_BE_BE3_CS3		(0x80)
+#define GPIO_PAR_BE_BE3_FB_A1		(0x40)
+#define GPIO_PAR_BE_BE3_NFC_ALE	(0x40)
+#define GPIO_PAR_BE_BE3_GPIO		(0x00)
+#define GPIO_PAR_BE_BS2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_BE_BE2_MASK		(0xCF)
+#define GPIO_PAR_BE_BE2_BE2		(0x30)
+#define GPIO_PAR_BE_BE2_CS2		(0x20)
+#define GPIO_PAR_BE_BE2_FB_A0		(0x10)
+#define GPIO_PAR_BE_BE2_NFC_CLE	(0x10)
+#define GPIO_PAR_BE_BE2_GPIO		(0x00)
+#define GPIO_PAR_BE_BS1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_BE_BE1_MASK		(0xF3)
+#define GPIO_PAR_BE_BE1_BE1		(0x0C)
+#define GPIO_PAR_BE_BE1_FB_TSZ1	(0x08)
+#define GPIO_PAR_BE_BE1_GPIO		(0x00)
+#define GPIO_PAR_BE_BS0(x)		((x)&0x03)
+#define GPIO_PAR_BE_BE0_MASK		(0xFC)
+#define GPIO_PAR_BE_BE0_BE0		(0x03)
+#define GPIO_PAR_BE_BE0_FB_TSZ0	(0x02)
+#define GPIO_PAR_BE_BE0_GPIO		(0x00)
+
+#define GPIO_PAR_CS_CS5(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_CS_CS5_MASK		(0x3F)
+#define GPIO_PAR_CS_CS5_CS5		(0xC0)
+#define GPIO_PAR_CS_CS5_DACK1		(0x80)
+#define GPIO_PAR_CS_CS5_GPIO		(0x00)
+#define GPIO_PAR_CS_CS4(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_CS_CS4_MASK		(0xCF)
+#define GPIO_PAR_CS_CS4_CS4		(0x30)
+#define GPIO_PAR_CS_CS4_DREQ1		(0x20)
+#define GPIO_PAR_CS_CS4_GPIO		(0x00)
+#define GPIO_PAR_CS_CS1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_CS_CS1_MASK		(0xF3)
+#define GPIO_PAR_CS_CS1_CS1		(0x0C)
+#define GPIO_PAR_CS_CS1_NFC_CE		(0x04)
+#define GPIO_PAR_CS_CS1_GPIO		(0x00)
+#define GPIO_PAR_CS_CS0_CS0		(0x01)
+
+#define GPIO_PAR_CANI2C_I2C0SCL(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_CANI2C_I2C0SCL_MASK	(0x3F)
+#define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL	(0xC0)
+#define GPIO_PAR_CANI2C_I2C0SCL_U8TXD	(0x80)
+#define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX	(0x40)
+#define GPIO_PAR_CANI2C_I2C0SCL_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_I2C0SDA(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_CANI2C_I2C0SDA_MASK	(0xCF)
+#define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA	(0x30)
+#define GPIO_PAR_CANI2C_I2C0SDA_U8RXD	(0x20)
+#define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX	(0x10)
+#define GPIO_PAR_CANI2C_I2C0SDA_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_CAN1TX(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_CANI2C_CAN1TX_MASK	(0xF3)
+#define GPIO_PAR_CANI2C_CAN1TX_CAN1TX	(0x0C)
+#define GPIO_PAR_CANI2C_CAN1TX_U9TXD	(0x08)
+#define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL	(0x04)
+#define GPIO_PAR_CANI2C_CAN1TX_GPIO	(0x00)
+#define GPIO_PAR_CANI2C_CAN1RX(x)	((x)&0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_MASK	(0xFC)
+#define GPIO_PAR_CANI2C_CAN1RX_CAN1RX	(0x03)
+#define GPIO_PAR_CANI2C_CAN1RX_U9RXD	(0x02)
+#define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA	(0x01)
+#define GPIO_PAR_CANI2C_CAN1RX_GPIO	(0x00)
+
+#define GPIO_PAR_IRQH_IRQ7		(0x10)
+#define GPIO_PAR_IRQH_IRQ4(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_IRQH_IRQ4_MASK	(0xF3)
+#define GPIO_PAR_IRQH_IRQ4_IRQ4	(0x0C)
+#define GPIO_PAR_IRQH_IRQ4_DREQ0	(0x08)
+#define GPIO_PAR_IRQH_IRQ4_GPIO	(0x00)
+#define GPIO_PAR_IRQH_IRQ1		(0x03)
+
+#define GPIO_PAR_IRQL_IRQ6(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_IRQL_IRQ6_MASK	(0x3F)
+#define GPIO_PAR_IRQL_IRQ6_IRQ6	(0xC0)
+#define GPIO_PAR_IRQL_IRQ6_USBCLKIN	(0x40)
+#define GPIO_PAR_IRQL_IRQ6_GPIO	(0x00)
+#define GPIO_PAR_IRQL_IRQ3(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_IRQL_IRQ3_MASK	(0xCF)
+#define GPIO_PAR_IRQL_IRQ3_IRQ3	(0x30)
+#define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3	(0x20)
+#define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN	(0x10)
+#define GPIO_PAR_IRQL_IRQ3_GPIO	(0x00)
+#define GPIO_PAR_IRQL_IRQ2(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_IRQL_IRQ2_MASK	(0xF3)
+#define GPIO_PAR_IRQL_IRQ2_IRQ2	(0x0C)
+#define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2	(0x08)
+#define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC	(0x04)
+#define GPIO_PAR_IRQL_IRQ2_GPIO	(0x00)
+
+#define GPIO_PAR_DSPI0_SIN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_DSPI0_SIN_MASK	(0x3F)
+#define GPIO_PAR_DSPI0_SIN_DSPI0SIN	(0xC0)
+#define GPIO_PAR_DSPI0_SIN_SBF_DI	(0xC0)
+#define GPIO_PAR_DSPI0_SIN_U3RXD	(0x80)
+#define GPIO_PAR_DSPI0_SIN_SDHC_CMD	(0x40)
+#define GPIO_PAR_DSPI0_SIN_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_SOUT(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_DSPI0_SOUT_MASK	(0xCF)
+#define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT	(0x30)
+#define GPIO_PAR_DSPI0_SOUT_SBF_DO	(0x30)
+#define GPIO_PAR_DSPI0_SOUT_U3TXD	(0x20)
+#define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0	(0x10)
+#define GPIO_PAR_DSPI0_SOUT_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_SCK(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_DSPI0_SCK_MASK	(0xF3)
+#define GPIO_PAR_DSPI0_SCK_DSPI0SCK	(0x0C)
+#define GPIO_PAR_DSPI0_SCK_SBF_CK	(0x0C)
+#define GPIO_PAR_DSPI0_SCK_I2C3SCL	(0x08)
+#define GPIO_PAR_DSPI0_SCK_SDHC_CLK	(0x04)
+#define GPIO_PAR_DSPI0_SCK_GPIO	(0x00)
+#define GPIO_PAR_DSPI0_PCS0(x)		((x)&0x03)
+#define GPIO_PAR_DSPI0_PCS0_MASK	(0xFC)
+#define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0	(0x03)
+#define GPIO_PAR_DSPI0_PCS0_SS		(0x03)
+#define GPIO_PAR_DSPI0_PCS0_I2C3SDA	(0x02)
+#define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3	(0x01)
+#define GPIO_PAR_DSPI0_PCS0_GPIO	(0x00)
+
+#define GPIO_PAR_DSPIOW_DSPI0PSC1	(0x80)
+#define GPIO_PAR_DSPIOW_SBF_CS		(0x80)
+#define GPIO_PAR_DSPIOW_OWDAT		(((x)&0x03)<<4)
+#define GPIO_PAR_DSPIOW_OWDAT_MASK	(0xCF)
+#define GPIO_PAR_DSPIOW_OWDAT_OWDAT	(0x30)
+#define GPIO_PAR_DSPIOW_OWDAT_DACK0	(0x20)
+#define GPIO_PAR_DSPIOW_OWDAT_GPIO	(0x00)
+
+#define GPIO_PAR_TIMER_T3IN(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_TIMER_T3IN_MASK	(0x3F)
+#define GPIO_PAR_TIMER_T3IN_T3IN	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_EXTA3	(0xC0)
+#define GPIO_PAR_TIMER_T3IN_T3OUT	(0x80)
+#define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN	(0x40)
+#define GPIO_PAR_TIMER_T3IN_ULIPI_DIR	(0x40)
+#define GPIO_PAR_TIMER_T3IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T2IN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_TIMER_T2IN_MASK	(0xCF)
+#define GPIO_PAR_TIMER_T2IN_T2IN	(0x30)
+#define GPIO_PAR_TIMER_T2IN_EXTA2	(0x30)
+#define GPIO_PAR_TIMER_T2IN_T2OUT	(0x20)
+#define GPIO_PAR_TIMER_T2IN_SDHC_DAT2	(0x10)
+#define GPIO_PAR_TIMER_T2IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T1IN(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_TIMER_T1IN_MASK	(0xF3)
+#define GPIO_PAR_TIMER_T1IN_T1IN	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_EXTA1	(0x0C)
+#define GPIO_PAR_TIMER_T1IN_T1OUT	(0x08)
+#define GPIO_PAR_TIMER_T1IN_SDHC_DAT1	(0x04)
+#define GPIO_PAR_TIMER_T1IN_GPIO	(0x00)
+#define GPIO_PAR_TIMER_T0IN(x)		((x)&0x03)
+#define GPIO_PAR_TIMER_T0IN_MASK	(0xFC)
+#define GPIO_PAR_TIMER_T0IN_T0IN	(0x03)
+#define GPIO_PAR_TIMER_T0IN_EXTA0	(0x03)
+#define GPIO_PAR_TIMER_T0IN_T0OUT	(0x02)
+#define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC	(0x01)
+#define GPIO_PAR_TIMER_T0IN_ULPI_NXT	(0x01)
+#define GPIO_PAR_TIMER_T0IN_GPIO	(0x00)
+
+#define GPIO_PAR_UART2_U2CTS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_UART2_U2CTS_MASK	(0x3F)
+#define GPIO_PAR_UART2_U2CTS_U2CTS	(0xC0)
+#define GPIO_PAR_UART2_U2CTS_U6TXD	(0x80)
+#define GPIO_PAR_UART2_U2CTS_SSI1_BCLK	(0x40)
+#define GPIO_PAR_UART2_U2CTS_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2RTS(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_UART2_U2RTS_MASK	(0xCF)
+#define GPIO_PAR_UART2_U2RTS_U2RTS	(0x30)
+#define GPIO_PAR_UART2_U2RTS_U6RXD	(0x20)
+#define GPIO_PAR_UART2_U2RTS_SSI1_FS	(0x10)
+#define GPIO_PAR_UART2_U2RTS_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2RXD(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_UART2_U2RXD_MASK	(0xF3)
+#define GPIO_PAR_UART2_U2RXD_U2RXD	(0x0C)
+#define GPIO_PAR_UART2_U2RXD_PWM_A3	(0x08)
+#define GPIO_PAR_UART2_U2RXD_SSI1_RXD	(0x04)
+#define GPIO_PAR_UART2_U2RXD_GPIO	(0x00)
+#define GPIO_PAR_UART2_U2TXD(x)	((x)&0x03)
+#define GPIO_PAR_UART2_U2TXD_MASK	(0xFC)
+#define GPIO_PAR_UART2_U2TXD_U2TXD	(0x03)
+#define GPIO_PAR_UART2_U2TXD_PWM_B3	(0x02)
+#define GPIO_PAR_UART2_U2TXD_SSI1_TXD	(0x01)
+#define GPIO_PAR_UART2_U2TXD_GPIO	(0x00)
+
+#define GPIO_PAR_UART1_U1CTS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_UART1_U1CTS_MASK	(0x3F)
+#define GPIO_PAR_UART1_U1CTS_U1CTS	(0xC0)
+#define GPIO_PAR_UART1_U1CTS_U5TXD	(0x80)
+#define GPIO_PAR_UART1_U1CTS_DSPI3_SCK	(0x40)
+#define GPIO_PAR_UART1_U1CTS_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1RTS(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_UART1_U1RTS_MASK	(0xCF)
+#define GPIO_PAR_UART1_U1RTS_U1RTS	(0x30)
+#define GPIO_PAR_UART1_U1RTS_U5RXD	(0x20)
+#define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0	(0x10)
+#define GPIO_PAR_UART1_U1RTS_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1RXD(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_UART1_U1RXD_MASK	(0xF3)
+#define GPIO_PAR_UART1_U1RXD_U1RXD	(0x0C)
+#define GPIO_PAR_UART1_U1RXD_I2C5SDA	(0x08)
+#define GPIO_PAR_UART1_U1RXD_DSPI3_SIN	(0x04)
+#define GPIO_PAR_UART1_U1RXD_GPIO	(0x00)
+#define GPIO_PAR_UART1_U1TXD(x)	((x)&0x03)
+#define GPIO_PAR_UART1_U1TXD_MASK	(0xFC)
+#define GPIO_PAR_UART1_U1TXD_U1TXD	(0x03)
+#define GPIO_PAR_UART1_U1TXD_I2C5SCL	(0x02)
+#define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT	(0x01)
+#define GPIO_PAR_UART1_U1TXD_GPIO	(0x00)
+
+#define GPIO_PAR_UART0_U0CTS(x)	(((x)&0x03)<<6)
+#define GPIO_PAR_UART0_U0CTS_MASK	(0x3F)
+#define GPIO_PAR_UART0_U0CTS_U0CTS	(0xC0)
+#define GPIO_PAR_UART0_U0CTS_U4TXD	(0x80)
+#define GPIO_PAR_UART0_U0CTS_DSPI2_SCK	(0x40)
+#define GPIO_PAR_UART0_U0CTS_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0RTS(x)	(((x)&0x03)<<4)
+#define GPIO_PAR_UART0_U0RTS_MASK	(0xCF)
+#define GPIO_PAR_UART0_U0RTS_U0RTS	(0x30)
+#define GPIO_PAR_UART0_U0RTS_U4RXD	(0x20)
+#define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0	(0x10)
+#define GPIO_PAR_UART0_U0RTS_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0RXD(x)	(((x)&0x03)<<2)
+#define GPIO_PAR_UART0_U0RXD_MASK	(0xF3)
+#define GPIO_PAR_UART0_U0RXD_U0RXD	(0x0C)
+#define GPIO_PAR_UART0_U0RXD_I2C4SDA	(0x08)
+#define GPIO_PAR_UART0_U0RXD_DSPI2_SIN	(0x04)
+#define GPIO_PAR_UART0_U0RXD_GPIO	(0x00)
+#define GPIO_PAR_UART0_U0TXD(x)	((x)&0x03)
+#define GPIO_PAR_UART0_U0TXD_MASK	(0xFC)
+#define GPIO_PAR_UART0_U0TXD_U0TXD	(0x03)
+#define GPIO_PAR_UART0_U0TXD_I2C4SCL	(0x02)
+#define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT	(0x01)
+#define GPIO_PAR_UART0_U0TXD_GPIO	(0x00)
+
+#define GPIO_PAR_SDHCH_DAT3(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SDHCH_DAT3_MASK	(0x3F)
+#define GPIO_PAR_SDHCH_DAT3_DAT3	(0xC0)
+#define GPIO_PAR_SDHCH_DAT3_PWM_A1	(0x80)
+#define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0	(0x40)
+#define GPIO_PAR_SDHCH_DAT3_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT2(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SDHCH_DAT2_MASK	(0xCF)
+#define GPIO_PAR_SDHCH_DAT2_DAT2	(0x30)
+#define GPIO_PAR_SDHCH_DAT2_PWM_B1	(0x20)
+#define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2	(0x10)
+#define GPIO_PAR_SDHCH_DAT2_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT1(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SDHCH_DAT1_MASK	(0xF3)
+#define GPIO_PAR_SDHCH_DAT1_DAT1	(0x0C)
+#define GPIO_PAR_SDHCH_DAT1_PWM_A2	(0x08)
+#define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1	(0x04)
+#define GPIO_PAR_SDHCH_DAT1_GPIO	(0x00)
+#define GPIO_PAR_SDHCH_DAT0(x)		((x)&0x03)
+#define GPIO_PAR_SDHCH_DAT0_MASK	(0xFC)
+#define GPIO_PAR_SDHCH_DAT0_DAT0	(0x03)
+#define GPIO_PAR_SDHCH_DAT0_PWM_B2	(0x02)
+#define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT	(0x01)
+#define GPIO_PAR_SDHCH_DAT0_GPIO	(0x00)
+
+#define GPIO_PAR_SDHCL_CMD(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SDHCL_CMD_MASK	(0xF3)
+#define GPIO_PAR_SDHCL_CMD_CMD		(0x0C)
+#define GPIO_PAR_SDHCL_CMD_PWM_A0	(0x08)
+#define GPIO_PAR_SDHCL_CMD_DSPI1_SIN	(0x04)
+#define GPIO_PAR_SDHCL_CMD_GPIO	(0x00)
+#define GPIO_PAR_SDHCL_CLK(x)		((x)&0x03)
+#define GPIO_PAR_SDHCL_CLK_MASK	(0xFC)
+#define GPIO_PAR_SDHCL_CLK_CLK		(0x03)
+#define GPIO_PAR_SDHCL_CLK_PWM_B0	(0x02)
+#define GPIO_PAR_SDHCL_CLK_DSPI1_SCK	(0x01)
+#define GPIO_PAR_SDHCL_CLK_GPIO	(0x00)
+
+#define GPIO_PAR_SIMP0H_DAT(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SIMP0H_DAT_MASK	(0x3F)
+#define GPIO_PAR_SIMP0H_DAT_DAT	(0xC0)
+#define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2	(0x80)
+#define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7	(0x40)
+#define GPIO_PAR_SIMP0H_DAT_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_VEN(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SIMP0H_VEN_MASK	(0xCF)
+#define GPIO_PAR_SIMP0H_VEN_VEN	(0x30)
+#define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0	(0x20)
+#define GPIO_PAR_SIMP0H_VEN_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_RST(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SIMP0H_RST_MASK	(0xF3)
+#define GPIO_PAR_SIMP0H_RST_RST	(0x0C)
+#define GPIO_PAR_SIMP0H_RST_PWM_FORCE	(0x08)
+#define GPIO_PAR_SIMP0H_RST_SDHC_DAT6	(0x04)
+#define GPIO_PAR_SIMP0H_RST_GPIO	(0x00)
+#define GPIO_PAR_SIMP0H_PD(x)		((x)&0x03)
+#define GPIO_PAR_SIMP0H_PD_MASK	(0xFC)
+#define GPIO_PAR_SIMP0H_PD_PD		(0x03)
+#define GPIO_PAR_SIMP0H_PD_PWM_SYNC	(0x02)
+#define GPIO_PAR_SIMP0H_PD_SDHC_DAT5	(0x01)
+#define GPIO_PAR_SIMP0H_PD_GPIO	(0x00)
+
+#define GPIO_PAR_SIMP0L_CLK(x)		((x)&0x03)
+#define GPIO_PAR_SIMP0L_CLK_MASK	(0xFC)
+#define GPIO_PAR_SIMP0L_CLK_CLK	(0x03)
+#define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1	(0x02)
+#define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4	(0x01)
+#define GPIO_PAR_SIMP0L_CLK_GPIO	(0x00)
+
+#define GPIO_PAR_SSI0H_RXD(x)		(((x)&0x03)<<6)
+#define GPIO_PAR_SSI0H_RXD_MASK	(0x3F)
+#define GPIO_PAR_SSI0H_RXD_RXD		(0xC0)
+#define GPIO_PAR_SSI0H_RXD_I2C2SDA	(0x80)
+#define GPIO_PAR_SSI0H_RXD_SIM1_VEN	(0x40)
+#define GPIO_PAR_SSI0H_RXD_GPIO	(0x00)
+#define GPIO_PAR_SSI0H_TXD(x)		(((x)&0x03)<<4)
+#define GPIO_PAR_SSI0H_TXD_MASK	(0xCF)
+#define GPIO_PAR_SSI0H_TXD_TXD		(0x30)
+#define GPIO_PAR_SSI0H_TXD_I2C2SCL	(0x20)
+#define GPIO_PAR_SSI0H_TXD_SIM1_DAT	(0x10)
+#define GPIO_PAR_SSI0H_TXD_GPIO	(0x00)
+#define GPIO_PAR_SSI0H_FS(x)		(((x)&0x03)<<2)
+#define GPIO_PAR_SSI0H_FS_MASK		(0xF3)
+#define GPIO_PAR_SSI0H_FS_FS		(0x0C)
+#define GPIO_PAR_SSI0H_FS_U7TXD	(0x08)
+#define GPIO_PAR_SSI0H_FS_SIM1_RST	(0x04)
+#define GPIO_PAR_SSI0H_FS_GPIO		(0x00)
+#define GPIO_PAR_SSI0H_MCLK(x)		((x)&0x03)
+#define GPIO_PAR_SSI0H_MCLK_MASK	(0xFC)
+#define GPIO_PAR_SSI0H_MCLK_MCLK	(0x03)
+#define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN	(0x02)
+#define GPIO_PAR_SSI0H_MCLK_SIM1_CLK	(0x01)
+#define GPIO_PAR_SSI0H_MCLK_GPIO	(0x00)
+
+#define GPIO_PAR_SSI0L_BCLK(x)		((x)&0x03)
+#define GPIO_PAR_SSI0L_BCLK_MASK	(0xFC)
+#define GPIO_PAR_SSI0L_BCLK_BCLK	(0x03)
+#define GPIO_PAR_SSI0L_BCLK_U7RXD	(0x02)
+#define GPIO_PAR_SSI0L_BCLK_SIM1_PD	(0x01)
+#define GPIO_PAR_SSI0L_BCLK_GPIO	(0x00)
+
+#define GPIO_PAR_DEBUGH1_DAT3		(0x40)
+#define GPIO_PAR_DEBUGH1_DAT2		(0x10)
+#define GPIO_PAR_DEBUGH1_DAT1		(0x04)
+#define GPIO_PAR_DEBUGH1_DAT0		(0x01)
+
+#define GPIO_PAR_DEBUGH0_PST3		(0x40)
+#define GPIO_PAR_DEBUGH0_PST2		(0x10)
+#define GPIO_PAR_DEBUGH0_PST1		(0x04)
+#define GPIO_PAR_DEBUGH0_PST0		(0x01)
+
+#define GPIO_PODR_G4_VAL		(0x01 << 4)
+#define GPIO_PODR_G4_MASK		(0xff & ~GPIO_PODR_G4_VAL)
+#define GPIO_PDDR_G4_OUTPUT		(0x01 << 4)
+#define GPIO_PDDR_G4_MASK		(0xff & ~GPIO_PDDR_G4_OUTPUT)
+
+#define GPIO_PAR_DEBUGL_ALLPST		(0x01)
+
+#define GPIO_PAR_FEC_FEC(x)		((x)&0x0F)
+#define GPIO_PAR_FEC_FEC_MASK		(0xF0)
+#define GPIO_PAR_FEC_FEC_GPIO		(0x0D)
+#define GPIO_PAR_FEC_FEC_RMII1		(0x0C)
+#define GPIO_PAR_FEC_FEC_RMII1FUL	(0x0B)
+#define GPIO_PAR_FEC_FEC_RMII_ULPI	(0x0A)
+#define GPIO_PAR_FEC_FEC_RMII0		(0x09)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI	(0x08)
+#define GPIO_PAR_FEC_FEC_RMII0FUL	(0x07)
+#define GPIO_PAR_FEC_FEC_RMII0_1FUL	(0x06)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1	(0x05)	/* 0:Full 1: */
+/* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
+#define GPIO_PAR_FEC_FEC_RMII0_1	(0x04)
+#define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL	(0x03)
+#define GPIO_PAR_FEC_FEC_MII		(0x01)	/* MDC & MDIO - GPIO */
+#define GPIO_PAR_FEC_FEC_MIIFUL	(0x00)
+
+
+/* TC: Need to edit here.... */
+
+/* Mode Select Control */
+#define GPIO_MSCR_SDRAM_MSC(x)		((x)&0x03)
+#define GPIO_MSCR_SDRAM_MSC_MASK	(0xFC)
+
+/* Slew Rate Control */
+
+#define GPIO_SRCR_FB3_FB3(x)		((x)&0x03)
+#define GPIO_SRCR_FB3_FB3_MASK		(0xFC)
+
+#define GPIO_SRCR_FB2_FB2(x)		((x)&0x03)
+#define GPIO_SRCR_FB2_FB2_MASK		(0xFC)
+
+#define GPIO_SRCR_FB1_FB1(x)		((x)&0x03)
+#define GPIO_SRCR_FB1_FB1_MASK		(0xFC)
+
+#define GPIO_SRCR_FB4_FB5(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_FB4_FB5_MASK		(0xF3)
+#define GPIO_SRCR_FB4_FB4(x)		((x)&0x03)
+#define GPIO_SRCR_FB4_FB4_MASK		(0xFC)
+
+#define GPIO_SRCR_DSPIOW_OWDAT(x)	(((x)&0x03)<<4)
+#define GPIO_SRCR_DSPIOW_OWDAT_MASK	(0xCF)
+#define GPIO_SRCR_DSPIOW_DSPI0(x)	((x)&0x03)
+#define GPIO_SRCR_DSPIOW_DSPI0_MASK	(0xFC)
+
+#define GPIO_SRCR_CANI2C_CAN1(x)	(((x)&0x03)<<2)
+#define GPIO_SRCR_CANI2C_CAN1_MASK	(0xF3)
+#define GPIO_SRCR_CANI2C_I2C0(x)	((x)&0x03)
+#define GPIO_SRCR_CANI2C_I2C0_MASK	(0xFC)
+
+#define GPIO_SRCR_IRQ0_IRQ0(x)		((x)&0x03)
+#define GPIO_SRCR_IRQ0_IRQ0_MASK	(0xFC)
+
+#define GPIO_SRCR_TIMER_TMR3(x)	(((x)&0x03)<<6)
+#define GPIO_SRCR_TIMER_TMR3_MASK	(0x3F)
+#define GPIO_SRCR_TIMER_TMR2(x)	(((x)&0x03)<<4)
+#define GPIO_SRCR_TIMER_TMR2_MASK	(0xCF)
+#define GPIO_SRCR_TIMER_TMR1(x)	(((x)&0x03)<<2)
+#define GPIO_SRCR_TIMER_TMR1_MASK	(0xF3)
+#define GPIO_SRCR_TIMER_TMR0(x)	((x)&0x03)
+#define GPIO_SRCR_TIMER_TMR0_MASK	(0xFC)
+
+#define GPIO_SRCR_UART_U2(x)		(((x)&0x03)<<4)
+#define GPIO_SRCR_UART_U2_MASK		(0xCF)
+#define GPIO_SRCR_UART_U1(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_UART_U1_MASK		(0xF3)
+#define GPIO_SRCR_UART_U0(x)		((x)&0x03)
+#define GPIO_SRCR_UART_U0_MASK		(0xFC)
+
+#define GPIO_SRCR_FEC_RMII0(x)		(((x)&0x03)<<2)
+#define GPIO_SRCR_FEC_RMII0_MASK	(0xF3)
+#define GPIO_SRCR_FEC_RMII1(x)		((x)&0x03)
+#define GPIO_SRCR_FEC_RMII1_MASK	(0xFC)
+
+#define GPIO_SRCR_SDHC_SDHC(x)		((x)&0x03)
+#define GPIO_SRCR_SDHC_SDHC_MASK	(0xFC)
+
+#define GPIO_SRCR_SIM0_SIMP0(x)	((x)&0x03)
+#define GPIO_SRCR_SIM0_SIMP0_MASK	(0xFC)
+
+#define GPIO_SRCR_SSI0_SSI0(x)		((x)&0x03)
+#define GPIO_SRCR_SSI0_SSI0_MASK	(0xFC)
+
+#define GPIO_PCR_URTS_U2		(0x0004)
+#define GPIO_PCR_URTS_U1		(0x0002)
+#define GPIO_PCR_URTS_U0		(0x0001)
+
+#define GPIO_PCR_UCTS_U2		(0x0004)
+#define GPIO_PCR_UCTS_U1		(0x0002)
+#define GPIO_PCR_UCTS_U0		(0x0001)
+
+#define GPIO_UTXD_WOM_U9		(0x0200)
+#define GPIO_UTXD_WOM_U8		(0x0100)
+#define GPIO_UTXD_WOM_U7		(0x0080)
+#define GPIO_UTXD_WOM_U6		(0x0040)
+#define GPIO_UTXD_WOM_U5		(0x0020)
+#define GPIO_UTXD_WOM_U4		(0x0010)
+#define GPIO_UTXD_WOM_U3		(0x0008)
+#define GPIO_UTXD_WOM_U2		(0x0004)
+#define GPIO_UTXD_WOM_U1		(0x0002)
+#define GPIO_UTXD_WOM_U0		(0x0001)
+
+#define GPIO_URXD_WOM_U9(x)		(((x)&3)<<18)
+#define GPIO_URXD_WOM_U9_MASK		(0xFFF3FFFF)
+#define GPIO_URXD_WOM_U8(x)		(((x)&3)<<16)
+#define GPIO_URXD_WOM_U8_MASK		(0xFFFCFFFF)
+#define GPIO_URXD_WOM_U7(x)		(((x)&3)<<14)
+#define GPIO_URXD_WOM_U7_MASK		(0xFFFF3FFF)
+#define GPIO_URXD_WOM_U6(x)		(((x)&3)<<12)
+#define GPIO_URXD_WOM_U6_MASK		(0xFFFFCFFF)
+#define GPIO_URXD_WOM_U5(x)		(((x)&3)<<10)
+#define GPIO_URXD_WOM_U5_MASK		(0xFFFFF3FF)
+#define GPIO_URXD_WOM_U4(x)		(((x)&3)<<8)
+#define GPIO_URXD_WOM_U4_MASK		(0xFFFFFCFF)
+#define GPIO_URXD_WOM_U3(x)		(((x)&3)<<6)
+#define GPIO_URXD_WOM_U3_MASK		(0xFFFFFF3F)
+#define GPIO_URXD_WOM_U2(x)		(((x)&3)<<4)
+#define GPIO_URXD_WOM_U2_MASK		(0xFFFFFFCF)
+#define GPIO_URXD_WOM_U1(x)		(((x)&3)<<2)
+#define GPIO_URXD_WOM_U1_MASK		(0xFFFFFFF3)
+#define GPIO_URXD_WOM_U0(x)		((x)&3)
+#define GPIO_URXD_WOM_U0_MASK		(0xFFFFFFFC)
+
+#define GPIO_HCR1_PG4_0(x)		(((x)&0x1F)<<27)
+#define GPIO_HCR1_PG4_0_MASK		(0x07FFFFFF)
+#define GPIO_HCR1_PF7_3(x)		(((x)&0x1F)<<22)
+#define GPIO_HCR1_PF7_3_MASK		(0xF83FFFFF)
+#define GPIO_HCR1_PE6_0(x)		(((x)&0x7F)<<15)
+#define GPIO_HCR1_PE6_0_MASK		(0xFFC07FFF)
+#define GPIO_HCR1_PD7_3(x)		(((x)&0x1F)<<10)
+#define GPIO_HCR1_PD7_3_MASK		(0xFFFF83FF)
+#define GPIO_HCR1_PC7_1(x)		(((x)&0x7F)<<3)
+#define GPIO_HCR1_PC7_1_MASK		(0xFFFFFC07)
+#define GPIO_HCR1_PB2_0(x)		((x)&7)
+#define GPIO_HCR1_PB2_0_MASK		(0xFFFFFFF8)
+
+#define GPIO_HCR0_PK3			(0x00000400)
+#define GPIO_HCR0_PK0			(0x00000200)
+#define GPIO_HCR0_PD2_0(x)		(((x)&7)<<6)
+#define GPIO_HCR0_PD2_0_MASK		(0xFFFFFE3F)
+#define GPIO_HCR0_PE7			(0x00000020)
+#define GPIO_HCR0_PH7_3(x)		((x)&0x1F)
+#define GPIO_HCR0_PH7_3_MASK(x)	(0xFFFFFFE0)
+
+/* SDRAM Controller (SDRAMC) */
+
+/* Phase Locked Loop (PLL) */
+#define PLL_CR_LOCIRQ			(0x00040000)
+#define PLL_CR_LOCRE			(0x00020000)
+#define PLL_CR_LOCEN			(0x00010000)
+#define PLL_CR_LOLIRQ			(0x00004000)
+#define PLL_CR_LOLRE			(0x00002000)
+#define PLL_CR_LOLEN			(0x00001000)
+#define PLL_CR_REFDIV(x)		(((x)&7)<<8)
+#define PLL_CR_REFDIV_MASK		(0xFFFFF8FF)
+#define PLL_CR_FBKDIV(x)		((x)&0x3F)
+#define PLL_CR_FBKDIV_MASK		(0xFFFFFFC0)
+#define PLL_CR_FBKDIV_BITS		(0x3F)
+
+#define PLL_DR_OUTDIV5(x)		(((x)&0x1F)<<21)
+#define PLL_DR_OUTDIV5_MASK		(0xFC1FFFFF)
+#define PLL_DR_OUTDIV5_BITS		(0x03E00000)
+#define PLL_DR_OUTDIV4(x)		(((x)&0x1F)<<16)
+#define PLL_DR_OUTDIV4_MASK		(0xFFE0FFFF)
+#define PLL_DR_OUTDIV4_BITS		(0x001F0000)
+#define PLL_DR_OUTDIV3(x)		(((x)&0x1F)<<10)
+#define PLL_DR_OUTDIV3_MASK		(0xFFFF83FF)
+#define PLL_DR_OUTDIV3_BITS		(0x00007C00)
+#define PLL_DR_OUTDIV2(x)		(((x)&0x1F)<<5)
+#define PLL_DR_OUTDIV2_MASK		(0xFFFFFC1F)
+#define PLL_DR_OUTDIV2_BITS		(0x000003E0)
+#define PLL_DR_OUTDIV1(x)		((x)&0x1F)
+#define PLL_DR_OUTDIV1_MASK		(0xFFFFFFE0)
+#define PLL_DR_OUTDIV1_BITS		(0x0000001F)
+
+#define PLL_SR_LOCF			(0x00000200)
+#define PLL_SR_LOC			(0x00000100)
+#define PLL_SR_LOLF			(0x00000040)
+#define PLL_SR_LOCKS			(0x00000020)
+#define PLL_SR_LOCK			(0x00000010)
+#define PLL_PSR_LOCK			PLL_SR_LOCK	/* compatible with 5x */
+#define PLL_SR_MODE(x)			((x)&7)
+#define PLL_SR_MODE_MASK		(0xFFFFFFF8)
+
+#endif				/* __MCF5441X__ */
diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h
index 973c9ee..8c7c554 100644
--- a/arch/m68k/include/asm/u-boot.h
+++ b/arch/m68k/include/asm/u-boot.h
@@ -58,7 +58,7 @@ typedef struct bd_info {
 	unsigned long bi_vcofreq;	/* vco Freq in MHz */
 	unsigned long bi_flbfreq;	/* Flexbus Freq in MHz */
 #endif
-	unsigned long bi_baudrate;	/* Console Baudrate */
+	unsigned int bi_baudrate;	/* Console Baudrate */
 } bd_t;
 
 #endif				/* __ASSEMBLY__ */
diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c
index 67c9a13..02d73fd 100644
--- a/arch/m68k/lib/board.c
+++ b/arch/m68k/lib/board.c
@@ -29,6 +29,7 @@
 #include <command.h>
 #include <malloc.h>
 #include <stdio_dev.h>
+#include <linux/compiler.h>
 
 #include <asm/immap.h>
 
@@ -387,7 +388,7 @@ board_init_f (ulong bootflag)
  */
 void board_init_r (gd_t *id, ulong dest_addr)
 {
-	char *s;
+	char *s __maybe_unused;
 	bd_t *bd;
 
 #ifndef CONFIG_ENV_IS_NOWHERE
@@ -415,8 +416,8 @@ void board_init_r (gd_t *id, ulong dest_addr)
 	/*
 	 * We have to relocate the command table manually
 	 */
-	fixup_cmdtable(&__u_boot_cmd_start,
-		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+			ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	/* there are some other pointer constants we must deal with */
diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c
index d258a69..ce066b9 100644
--- a/arch/microblaze/cpu/cache.c
+++ b/arch/microblaze/cpu/cache.c
@@ -61,12 +61,7 @@ void	dcache_enable (void) {
 
 void	dcache_disable(void) {
 #ifdef XILINX_USE_DCACHE
-#ifdef XILINX_DCACHE_BYTE_SIZE
 	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#else
-#warning please rebuild BSPs and update configuration
-	flush_cache(0, 32768);
-#endif
 #endif
 	MSRCLR(0x80);
 }
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 8564c4e..3da711d 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -132,6 +132,12 @@ _start:
 	rsubi	r8, r10, 0x26
 	sh	r6, r0, r8
 
+	/* Flush cache before enable cache */
+	addik	r5, r0, 0
+	addik	r6, r0, XILINX_DCACHE_BYTE_SIZE
+flush:	bralid r15, flush_cache
+	nop
+
 	/* enable instruction and data cache */
 	mfs	r12, rmsr
 	ori	r12, r12, 0xa0
diff --git a/arch/microblaze/cpu/u-boot.lds b/arch/microblaze/cpu/u-boot.lds
index d033a28..fe3d97d 100644
--- a/arch/microblaze/cpu/u-boot.lds
+++ b/arch/microblaze/cpu/u-boot.lds
@@ -45,17 +45,16 @@ SECTIONS
 	.data ALIGN(0x4):
 	{
 		__data_start = .;
+#ifdef CONFIG_OF_EMBED
 		dts/libdts.o (.data)
+#endif
 		*(.data)
 		__data_end = .;
 	}
 
-	.u_boot_cmd ALIGN(0x4):
-	{
-		. = .;
-		__u_boot_cmd_start = .;
-		*(.u_boot_cmd)
-		__u_boot_cmd_end = .;
+	. = ALIGN(4);
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
 
 	.bss ALIGN(0x4):
diff --git a/arch/microblaze/include/asm/bitops.h b/arch/microblaze/include/asm/bitops.h
index e8c835f..eafa2b5 100644
--- a/arch/microblaze/include/asm/bitops.h
+++ b/arch/microblaze/include/asm/bitops.h
@@ -319,7 +319,8 @@ extern __inline__ int ext2_test_bit(int nr, const volatile void * addr)
 #define ext2_find_first_zero_bit(addr, size) \
 	ext2_find_next_zero_bit((addr), (size), 0)
 
-extern __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
+static inline unsigned long ext2_find_next_zero_bit(void *addr,
+				unsigned long size, unsigned long offset)
 {
 	unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
 	unsigned long result = offset & ~31UL;
diff --git a/arch/microblaze/include/asm/byteorder.h b/arch/microblaze/include/asm/byteorder.h
index b2757a4..f3a471d 100644
--- a/arch/microblaze/include/asm/byteorder.h
+++ b/arch/microblaze/include/asm/byteorder.h
@@ -20,29 +20,6 @@
 
 #ifdef __GNUC__
 
-/* This is effectively a dupe of the arch-independent byteswap
-   code in include/linux/byteorder/swab.h, however we force a cast
-   of the result up to 32 bits.  This in turn forces the compiler
-   to explicitly clear the high 16 bits, which it wasn't doing otherwise.
-
-   I think this is a symptom of a bug in mb-gcc.  JW 20040303
-*/
-
-
-static __inline__ __u16 ___arch__swab16 (__u16 half_word)
-{
-	/* 32 bit temp to cast result, forcing clearing of high word */
-	__u32 temp;
-
-	temp = ((half_word & 0x00FFU) << 8) | ((half_word & 0xFF00U) >> 8);
-
-	return (__u16) temp;
-}
-
-#define __arch__swab16(x) ___arch__swab16(x)
-
-/* Microblaze has no arch-specific endian conversion insns */
-
 #if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
 #  define __BYTEORDER_HAS_U64__
 #  define __SWAB_64_THRU_32__
diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h
index de3b8db..2111c7c 100644
--- a/arch/microblaze/include/asm/global_data.h
+++ b/arch/microblaze/include/asm/global_data.h
@@ -35,7 +35,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
diff --git a/arch/microblaze/include/asm/posix_types.h b/arch/microblaze/include/asm/posix_types.h
index 9a2cc66..38dc5aa 100644
--- a/arch/microblaze/include/asm/posix_types.h
+++ b/arch/microblaze/include/asm/posix_types.h
@@ -16,9 +16,6 @@
 #ifndef __MICROBLAZE_POSIX_TYPES_H__
 #define __MICROBLAZE_POSIX_TYPES_H__
 
-#include <asm/bitops.h>
-
-
 typedef unsigned int	__kernel_dev_t;
 typedef unsigned long	__kernel_ino_t;
 typedef unsigned long long __kernel_ino64_t;
diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h
index a0b1dbf..8d00658 100644
--- a/arch/microblaze/include/asm/u-boot.h
+++ b/arch/microblaze/include/asm/u-boot.h
@@ -40,7 +40,7 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-	unsigned long	bi_baudrate;	/* Console Baudrate */
+	unsigned int	bi_baudrate;	/* Console Baudrate */
 } bd_t;
 
 /* For image.h:image_check_target_arch() */
diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c
index 95cee50..66d21f4 100644
--- a/arch/microblaze/lib/bootm.c
+++ b/arch/microblaze/lib/bootm.c
@@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima
 #endif
 
 #ifdef XILINX_USE_DCACHE
-#ifdef XILINX_DCACHE_BYTE_SIZE
 	flush_cache(0, XILINX_DCACHE_BYTE_SIZE);
-#else
-#warning please rebuild BSPs and update configuration
-	flush_cache(0, 32768);
-#endif
 #endif
 	/*
 	 * Linux Kernel Parameters (passing device tree):
diff --git a/arch/mips/cpu/mips32/au1x00/Makefile b/arch/mips/cpu/mips32/au1x00/Makefile
index dc58475..b9f895d 100644
--- a/arch/mips/cpu/mips32/au1x00/Makefile
+++ b/arch/mips/cpu/mips32/au1x00/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	= au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+COBJS	= au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_ide.c b/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
new file mode 100644
index 0000000..932cdfb
--- /dev/null
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_ide.c
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <ide.h>
+
+/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+	ide_input_data(dev, sect_buf, words);
+}
diff --git a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
index 0beac98..3e85b90 100644
--- a/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
+++ b/arch/mips/cpu/mips32/au1x00/au1x00_serial.c
@@ -103,12 +103,6 @@ static void au1x00_serial_putc(const char c)
 	*uart_tx = (u32)c;
 }
 
-static void au1x00_serial_puts(const char *s)
-{
-	while (*s)
-		serial_putc(*s++);
-}
-
 static int au1x00_serial_getc(void)
 {
 	volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
@@ -137,7 +131,7 @@ static struct serial_device au1x00_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= au1x00_serial_setbrg,
 	.putc	= au1x00_serial_putc,
-	.puts	= au1x00_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= au1x00_serial_getc,
 	.tstc	= au1x00_serial_tstc,
 };
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index e683e8b..64dfad0 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -85,17 +85,17 @@ LEAF(mips_init_icache)
 	/* clear tag to invalidate */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1
-1:	cache_op	Index_Store_Tag_I t0
+1:	cache_op	INDEX_STORE_TAG_I t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 	/* fill once, so data field parity is correct */
 	PTR_LI		t0, INDEX_BASE
-2:	cache_op	Fill t0
+2:	cache_op	FILL t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 2b
 	/* invalidate again - prudent but not strictly neccessary */
 	PTR_LI		t0, INDEX_BASE
-1:	cache_op	Index_Store_Tag_I t0
+1:	cache_op	INDEX_STORE_TAG_I t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 9:	jr		ra
@@ -110,7 +110,7 @@ LEAF(mips_init_dcache)
 	/* clear all tags */
 	PTR_LI		t0, INDEX_BASE
 	PTR_ADDU	t1, t0, a1
-1:	cache_op	Index_Store_Tag_D t0
+1:	cache_op	INDEX_STORE_TAG_D t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 	/* load from each line (in cached space) */
@@ -120,7 +120,7 @@ LEAF(mips_init_dcache)
 	bne		t0, t1, 2b
 	/* clear all tags */
 	PTR_LI		t0, INDEX_BASE
-1:	cache_op	Index_Store_Tag_D t0
+1:	cache_op	INDEX_STORE_TAG_D t0
 	PTR_ADDU	t0, a2
 	bne		t0, t1, 1b
 9:	jr		ra
diff --git a/arch/mips/cpu/mips32/cpu.c b/arch/mips/cpu/mips32/cpu.c
index 7b49e1b..50bb248 100644
--- a/arch/mips/cpu/mips32/cpu.c
+++ b/arch/mips/cpu/mips32/cpu.c
@@ -61,8 +61,8 @@ void flush_cache(ulong start_addr, ulong size)
 		return;
 
 	while (1) {
-		cache_op(Hit_Writeback_Inv_D, addr);
-		cache_op(Hit_Invalidate_I, addr);
+		cache_op(HIT_WRITEBACK_INV_D, addr);
+		cache_op(HIT_INVALIDATE_I, addr);
 		if (addr == aend)
 			break;
 		addr += lsize;
@@ -76,7 +76,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
 	while (1) {
-		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(HIT_WRITEBACK_INV_D, addr);
 		if (addr == aend)
 			break;
 		addr += lsize;
@@ -90,7 +90,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
 	while (1) {
-		cache_op(Hit_Invalidate_D, addr);
+		cache_op(HIT_INVALIDATE_D, addr);
 		if (addr == aend)
 			break;
 		addr += lsize;
diff --git a/arch/mips/cpu/mips32/incaip/asc_serial.c b/arch/mips/cpu/mips32/incaip/asc_serial.c
index 08949f4..6f0e4f2 100644
--- a/arch/mips/cpu/mips32/incaip/asc_serial.c
+++ b/arch/mips/cpu/mips32/incaip/asc_serial.c
@@ -236,14 +236,6 @@ static void asc_serial_putc(const char c)
     }
 }
 
-static void asc_serial_puts(const char *s)
-{
-    while (*s)
-    {
-	serial_putc (*s++);
-    }
-}
-
 static int asc_serial_getc(void)
 {
     ulong symbol_mask;
@@ -292,7 +284,7 @@ static struct serial_device asc_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= asc_serial_setbrg,
 	.putc	= asc_serial_putc,
-	.puts	= asc_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= asc_serial_getc,
 	.tstc	= asc_serial_tstc,
 };
diff --git a/arch/arm/cpu/lh7a40x/Makefile b/arch/mips/cpu/mips64/Makefile
index 01cf7f5..be38664 100644
--- a/arch/arm/cpu/lh7a40x/Makefile
+++ b/arch/mips/cpu/mips64/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000-2006
+# (C) Copyright 2003-2006
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -26,10 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
-COBJS	= cpu.o speed.o timer.o
+COBJS-y	= cpu.o interrupts.o time.o cache.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(START) $(LIB)
@@ -43,5 +43,3 @@ $(LIB):	$(OBJS)
 include $(SRCTREE)/rules.mk
 
 sinclude $(obj).depend
-
-#########################################################################
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S
new file mode 100644
index 0000000..036f035
--- /dev/null
+++ b/arch/mips/cpu/mips64/cache.S
@@ -0,0 +1,229 @@
+/*
+ *  Cache-handling routined for MIPS CPUs
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA		t9
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE	0x10000
+
+#define INDEX_BASE	CKSEG0
+
+	.macro	cache_op op addr
+	.set	push
+	.set	noreorder
+	.set	mips3
+	cache	\op, 0(\addr)
+	.set	pop
+	.endm
+
+	.macro	f_fill64 dst, offset, val
+	LONG_S	\val, (\offset +  0 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  1 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  2 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  3 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  4 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  5 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  6 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+	LONG_S	\val, (\offset +  8 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset +  9 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset + 10 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset + 11 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset + 12 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset + 13 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset + 14 * LONGSIZE)(\dst)
+	LONG_S	\val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+	.endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+	blez		a1, 9f
+	mtc0		zero, CP0_TAGLO
+	/* clear tag to invalidate */
+	PTR_LI		t0, INDEX_BASE
+	PTR_ADDU	t1, t0, a1
+1:	cache_op	INDEX_STORE_TAG_I t0
+	PTR_ADDU	t0, a2
+	bne		t0, t1, 1b
+	/* fill once, so data field parity is correct */
+	PTR_LI		t0, INDEX_BASE
+2:	cache_op	FILL t0
+	PTR_ADDU	t0, a2
+	bne		t0, t1, 2b
+	/* invalidate again - prudent but not strictly neccessary */
+	PTR_LI		t0, INDEX_BASE
+1:	cache_op	INDEX_STORE_TAG_I t0
+	PTR_ADDU	t0, a2
+	bne		t0, t1, 1b
+9:	jr		ra
+	END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+	blez		a1, 9f
+	mtc0		zero, CP0_TAGLO
+	/* clear all tags */
+	PTR_LI		t0, INDEX_BASE
+	PTR_ADDU	t1, t0, a1
+1:	cache_op	INDEX_STORE_TAG_D t0
+	PTR_ADDU	t0, a2
+	bne		t0, t1, 1b
+	/* load from each line (in cached space) */
+	PTR_LI		t0, INDEX_BASE
+2:	LONG_L		zero, 0(t0)
+	PTR_ADDU	t0, a2
+	bne		t0, t1, 2b
+	/* clear all tags */
+	PTR_LI		t0, INDEX_BASE
+1:	cache_op	INDEX_STORE_TAG_D t0
+	PTR_ADDU	t0, a2
+	bne		t0, t1, 1b
+9:	jr		ra
+	END(mips_init_dcache)
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity.  It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
+NESTED(mips_cache_reset, 0, ra)
+	move	RA, ra
+	li	t2, CONFIG_SYS_ICACHE_SIZE
+	li	t3, CONFIG_SYS_DCACHE_SIZE
+	li	t8, CONFIG_SYS_CACHELINE_SIZE
+
+	li	v0, MIPS_MAX_CACHE_SIZE
+
+	/*
+	 * Now clear that much memory starting from zero.
+	 */
+	PTR_LI		a0, CKSEG1
+	PTR_ADDU	a1, a0, v0
+2:	PTR_ADDIU	a0, 64
+	f_fill64	a0, -64, zero
+	bne		a0, a1, 2b
+
+	/*
+	 * The caches are probably in an indeterminate state,
+	 * so we force good parity into them by doing an
+	 * invalidate, load/fill, invalidate for each line.
+	 */
+
+	/*
+	 * Assume bottom of RAM will generate good parity for the cache.
+	 */
+
+	/*
+	 * Initialize the I-cache first,
+	 */
+	move	a1, t2
+	move	a2, t8
+	PTR_LA	v1, mips_init_icache
+	jalr	v1
+
+	/*
+	 * then initialize D-cache.
+	 */
+	move	a1, t3
+	move	a2, t8
+	PTR_LA	v1, mips_init_dcache
+	jalr	v1
+
+	jr	RA
+	END(mips_cache_reset)
+
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
+LEAF(dcache_status)
+	mfc0	t0, CP0_CONFIG
+	li	t1, CONF_CM_UNCACHED
+	andi	t0, t0, CONF_CM_CMASK
+	move	v0, zero
+	beq	t0, t1, 2f
+	li	v0, 1
+2:	jr	ra
+	END(dcache_status)
+
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_disable)
+	mfc0	t0, CP0_CONFIG
+	li	t1, -8
+	and	t0, t0, t1
+	ori	t0, t0, CONF_CM_UNCACHED
+	mtc0	t0, CP0_CONFIG
+	jr	ra
+	END(dcache_disable)
+
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_enable)
+	mfc0	t0, CP0_CONFIG
+	ori	t0, CONF_CM_CMASK
+	xori	t0, CONF_CM_CMASK
+	ori	t0, CONF_CM_CACHABLE_NONCOHERENT
+	mtc0	t0, CP0_CONFIG
+	jr	ra
+	END(dcache_enable)
diff --git a/arch/arm/cpu/lh7a40x/config.mk b/arch/mips/cpu/mips64/config.mk
index 1c4aa97..ebc1ceb 100644
--- a/arch/arm/cpu/lh7a40x/config.mk
+++ b/arch/mips/cpu/mips64/config.mk
@@ -1,6 +1,6 @@
 #
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
 #
 # See file CREDITS for list of people who contributed to this
 # project.
@@ -21,13 +21,20 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
 #
-# Supply options according to compiler version
+# Default optimization level for MIPS64
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
 #
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+MIPSFLAGS = -march=mips64
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS  += -m elf64btsmip
+else
+PLATFORM_LDFLAGS  += -m elf64ltsmip
+endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 0000000..2a38d0c
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op, addr)						\
+	__asm__ __volatile__(						\
+	"	.set	push\n"						\
+	"	.set	noreorder\n"					\
+	"	.set	mips64\n"					\
+	"	cache	%0, %1\n"					\
+	"	.set	pop\n"						\
+	:								\
+	: "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+	fprintf(stderr, "*** reset failed ***\n");
+
+	while (1)
+		/* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	_machine_restart();
+
+	return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+	/* aend will be miscalculated when size is zero, so we return here */
+	if (size == 0)
+		return;
+
+	while (1) {
+		cache_op(HIT_WRITEBACK_INV_D, addr);
+		cache_op(HIT_INVALIDATE_I, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(HIT_WRITEBACK_INV_D, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+	unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+	unsigned long addr = start_addr & ~(lsize - 1);
+	unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+	while (1) {
+		cache_op(HIT_INVALIDATE_D, addr);
+		if (addr == aend)
+			break;
+		addr += lsize;
+	}
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+	write_c0_entrylo0(low0);
+	write_c0_pagemask(pagemask);
+	write_c0_entrylo1(low1);
+	write_c0_entryhi(hi);
+	write_c0_index(index);
+	tlb_write_indexed();
+}
diff --git a/arch/arm/cpu/lh7a40x/cpu.c b/arch/mips/cpu/mips64/interrupts.c
index b193189..e4e9aae 100644
--- a/arch/arm/cpu/lh7a40x/cpu.c
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -1,10 +1,6 @@
 /*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,41 +21,14 @@
  * MA 02111-1307 USA
  */
 
-/*
- * CPU specific code
- */
-
 #include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
+#include <asm/mipsregs.h>
 
-int cleanup_before_linux (void)
+void enable_interrupts(void)
 {
-	/*
-	 * this function is called just before we call linux
-	 * it prepares the processor for linux
-	 *
-	 * we turn off caches etc ...
-	 */
-
-	disable_interrupts ();
-
-	/* turn off I/D-cache */
-	icache_disable();
-	dcache_disable();
-
-	/* flush I/D-cache */
-	cache_flush();
-
-	return 0;
 }
 
-/* flush I/D-cache */
-static void cache_flush (void)
+int disable_interrupts(void)
 {
-	unsigned long i = 0;
-
-	asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+	return 0;
 }
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S
new file mode 100644
index 0000000..4112de7
--- /dev/null
+++ b/arch/mips/cpu/mips64/start.S
@@ -0,0 +1,256 @@
+/*
+ *  Startup Code for MIPS64 CPU-core
+ *
+ *  Copyright (c) 2003	Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+	/*
+	 * For the moment disable interrupts, mark the kernel mode and
+	 * set ST0_KX so that the CPU does not spit fire when using
+	 * 64-bit addresses.
+	 */
+	.macro	setup_c0_status set clr
+	.set	push
+	mfc0	t0, CP0_STATUS
+	or	t0, ST0_CU0 | \set | 0x1f | \clr
+	xor	t0, 0x1f | \clr
+	mtc0	t0, CP0_STATUS
+	.set	noreorder
+	sll	zero, 3				# ehb
+	.set	pop
+	.endm
+
+	.set noreorder
+
+	.globl _start
+	.text
+_start:
+	.org 0x000
+	b	reset
+	 nop
+	.org 0x080
+	b	romReserved
+	 nop
+	.org 0x100
+	b	romReserved
+	 nop
+	.org 0x180
+	b	romReserved
+	 nop
+	.org 0x200
+	b	romReserved
+	 nop
+	.org 0x280
+	b	romReserved
+	 nop
+	.org 0x300
+	b	romReserved
+	 nop
+	.org 0x380
+	b	romReserved
+	 nop
+	.org 0x480
+	b	romReserved
+	 nop
+
+	/*
+	 * We hope there are no more reserved vectors!
+	 * 128 * 8 == 1024 == 0x400
+	 * so this is address R_VEC+0x400 == 0xbfc00400
+	 */
+	.org 0x500
+	.align 4
+reset:
+
+	/* Clear watch registers */
+	dmtc0	zero, CP0_WATCHLO
+	dmtc0	zero, CP0_WATCHHI
+
+	/* WP(Watch Pending), SW0/1 should be cleared */
+	mtc0	zero, CP0_CAUSE
+
+	setup_c0_status ST0_KX 0
+
+	/* Init Timer */
+	mtc0	zero, CP0_COUNT
+	mtc0	zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	/* CONFIG0 register */
+	dli	t0, CONF_CM_UNCACHED
+	mtc0	t0, CP0_CONFIG
+#endif
+
+	/* Initialize $gp */
+	bal	1f
+	 nop
+	.dword	_gp
+1:
+	ld	gp, 0(ra)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+	/* Initialize any external memory */
+	dla	t9, lowlevel_init
+	jalr	t9
+	 nop
+
+	/* Initialize caches... */
+	dla	t9, mips_cache_reset
+	jalr	t9
+	 nop
+
+	/* ... and enable them */
+	dli	t0, CONFIG_SYS_MIPS_CACHE_MODE
+	mtc0	t0, CP0_CONFIG
+#endif
+
+	/* Set up temporary stack */
+	dli	t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+	dla	sp, 0(t0)
+
+	dla	t9, board_init_f
+	jr	t9
+	 nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+	.globl	relocate_code
+	.ent	relocate_code
+relocate_code:
+	move	sp, a0			# set new stack pointer
+
+	dli	t0, CONFIG_SYS_MONITOR_BASE
+	dla	t3, in_ram
+	ld	t2, -24(t3)		# t2 <-- uboot_end_data
+	move	t1, a2
+	move	s2, a2			# s2 <-- destination address
+
+	/*
+	 * Fix $gp:
+	 *
+	 * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+	 */
+	move	t8, gp
+	dsub	gp, CONFIG_SYS_MONITOR_BASE
+	dadd	gp, a2			# gp now adjusted
+	dsub	s1, gp, t8		# s1 <-- relocation offset
+
+	/*
+	 * t0 = source address
+	 * t1 = target address
+	 * t2 = source end address
+	 */
+
+	/*
+	 * Save destination address and size for dlater usage in flush_cache()
+	 */
+	move	s0, a1			# save gd in s0
+	move	a0, t1			# a0 <-- destination addr
+	dsub	a1, t2, t0		# a1 <-- size
+
+1:
+	lw	t3, 0(t0)
+	sw	t3, 0(t1)
+	daddu	t0, 4
+	ble	t0, t2, 1b
+	 daddu	t1, 4
+
+	/* If caches were enabled, we would have to flush them here. */
+
+	/* a0 & a1 are already set up for flush_cache(start, size) */
+	dla	t9, flush_cache
+	jalr	t9
+	 nop
+
+	/* Jump to where we've relocated ourselves */
+	daddi	t0, s2, in_ram - _start
+	jr	t0
+	 nop
+
+	.dword	_gp
+	.dword	_GLOBAL_OFFSET_TABLE_
+	.dword	uboot_end_data
+	.dword	uboot_end
+	.dword	num_got_entries
+
+in_ram:
+	/*
+	 * Now we want to update GOT.
+	 *
+	 * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+	 * generated by GNU ld. Skip these reserved entries from relocation.
+	 */
+	ld	t3, -8(t0)		# t3 <-- num_got_entries
+	ld	t8, -32(t0)		# t8 <-- _GLOBAL_OFFSET_TABLE_
+	ld	t9, -40(t0)		# t9 <-- _gp
+	dsub	t8, t9			# compute offset
+	dadd	t8, t8, gp		# t8 now holds relocated _G_O_T_
+	daddi	t8, t8, 16		# skipping first two entries
+	dli	t2, 2
+1:
+	ld	t1, 0(t8)
+	beqz	t1, 2f
+	 dadd	t1, s1
+	sd	t1, 0(t8)
+2:
+	daddi	t2, 1
+	blt	t2, t3, 1b
+	 daddi	t8, 8
+
+	/* Clear BSS */
+	ld	t1, -24(t0)		# t1 <-- uboot_end_data
+	ld	t2, -16(t0)		# t2 <-- uboot_end
+	dadd	t1, s1			# adjust pointers
+	dadd	t2, s1
+
+	dsub	t1, 8
+1:
+	daddi	t1, 8
+	bltl	t1, t2, 1b
+	 sd	zero, 0(t1)
+
+	move	a0, s0			# a0 <-- gd
+	dla	t9, board_init_r
+	jr	t9
+	 move	a1, s2
+
+	.end	relocate_code
+
+	/* Exception handlers */
+romReserved:
+	b	romReserved
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 0000000..5154280
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY	 \
+	(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+	/* Set up the timer for the first expiration. */
+	timestamp = 0;
+	write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+	return 0;
+}
+
+ulong get_timer(ulong base)
+{
+	unsigned int count;
+	unsigned int expirelo = read_c0_compare();
+
+	/* Check to see if we have missed any timestamps. */
+	count = read_c0_count();
+	while ((count - expirelo) < 0x7fffffff) {
+		expirelo += CYCLES_PER_JIFFY;
+		timestamp++;
+	}
+	write_c0_compare(expirelo);
+
+	return timestamp - base;
+}
+
+void __udelay(unsigned long usec)
+{
+	unsigned int tmo;
+
+	tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+	while ((tmo - read_c0_count()) < 0x7fffffff)
+		/*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/mips/cpu/xburst/cpu.c b/arch/mips/cpu/xburst/cpu.c
index ddcbfaa..cc190df 100644
--- a/arch/mips/cpu/xburst/cpu.c
+++ b/arch/mips/cpu/xburst/cpu.c
@@ -84,8 +84,8 @@ void flush_cache(ulong start_addr, ulong size)
 	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
 	for (; addr <= aend; addr += lsize) {
-		cache_op(Hit_Writeback_Inv_D, addr);
-		cache_op(Hit_Invalidate_I, addr);
+		cache_op(HIT_WRITEBACK_INV_D, addr);
+		cache_op(HIT_INVALIDATE_I, addr);
 	}
 }
 
@@ -96,7 +96,7 @@ void flush_dcache_range(ulong start_addr, ulong stop)
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
 	for (; addr <= aend; addr += lsize)
-		cache_op(Hit_Writeback_Inv_D, addr);
+		cache_op(HIT_WRITEBACK_INV_D, addr);
 }
 
 void invalidate_dcache_range(ulong start_addr, ulong stop)
@@ -106,7 +106,7 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 	unsigned long aend = (stop - 1) & ~(lsize - 1);
 
 	for (; addr <= aend; addr += lsize)
-		cache_op(Hit_Invalidate_D, addr);
+		cache_op(HIT_INVALIDATE_D, addr);
 }
 
 void flush_icache_all(void)
@@ -118,7 +118,7 @@ void flush_icache_all(void)
 
 	for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
 	     addr += CONFIG_SYS_CACHELINE_SIZE) {
-		cache_op(Index_Store_Tag_I, addr);
+		cache_op(INDEX_STORE_TAG_I, addr);
 	}
 
 	/* invalidate btb */
@@ -139,7 +139,7 @@ void flush_dcache_all(void)
 
 	for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
 	     addr += CONFIG_SYS_CACHELINE_SIZE) {
-		cache_op(Index_Writeback_Inv_D, addr);
+		cache_op(INDEX_WRITEBACK_INV_D, addr);
 	}
 
 	__asm__ __volatile__("sync");
diff --git a/arch/mips/cpu/xburst/jz_serial.c b/arch/mips/cpu/xburst/jz_serial.c
index 3199007..a147657 100644
--- a/arch/mips/cpu/xburst/jz_serial.c
+++ b/arch/mips/cpu/xburst/jz_serial.c
@@ -109,19 +109,13 @@ static int jz_serial_getc(void)
 	return readb(&uart->rbr_thr_dllr);
 }
 
-static void jz_serial_puts(const char *s)
-{
-	while (*s)
-		serial_putc(*s++);
-}
-
 static struct serial_device jz_serial_drv = {
 	.name	= "jz_serial",
 	.start	= jz_serial_init,
 	.stop	= NULL,
 	.setbrg	= jz_serial_setbrg,
 	.putc	= jz_serial_putc,
-	.puts	= jz_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= jz_serial_getc,
 	.tstc	= jz_serial_tstc,
 };
diff --git a/arch/mips/cpu/xburst/start.S b/arch/mips/cpu/xburst/start.S
index d846104..3a8280c 100644
--- a/arch/mips/cpu/xburst/start.S
+++ b/arch/mips/cpu/xburst/start.S
@@ -96,7 +96,7 @@ relocate_code:
 	li	t0, KSEG0
 	addi	t1, t0, CONFIG_SYS_DCACHE_SIZE
 2:
-	cache	Index_Writeback_Inv_D, 0(t0)
+	cache	INDEX_WRITEBACK_INV_D, 0(t0)
 	bne	t0, t1, 2b
 	 addi	t0, CONFIG_SYS_CACHELINE_SIZE
 
@@ -106,7 +106,7 @@ relocate_code:
 	li	t0, KSEG0
 	addi	t1, t0, CONFIG_SYS_ICACHE_SIZE
 3:
-	cache	Index_Invalidate_I, 0(t0)
+	cache	INDEX_INVALIDATE_I, 0(t0)
 	bne	t0, t1, 3b
 	 addi	t0, CONFIG_SYS_CACHELINE_SIZE
 
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
 #else	/* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
 #endif	/* CONFIG_SOC_AU1X00 */
 #endif	/* __ASSEMBLY__ */
 
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcf..933ccb1 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -401,7 +401,7 @@ symbol		=	value
 #ifdef CONFIG_SGI_IP28
 /* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
 #include <asm/cacheops.h>
-#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
+#define R10KCBARRIER(addr)  cache   CACHE_BARRIER, addr;
 #else
 #define R10KCBARRIER(addr)
 #endif
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 70bcad7..6464250 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -14,54 +14,54 @@
 /*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Load_Tag_I	0x04
-#define Index_Load_Tag_D	0x05
-#define Index_Store_Tag_I	0x08
-#define Index_Store_Tag_D	0x09
+#define INDEX_INVALIDATE_I      0x00
+#define INDEX_WRITEBACK_INV_D   0x01
+#define INDEX_LOAD_TAG_I	0x04
+#define INDEX_LOAD_TAG_D	0x05
+#define INDEX_STORE_TAG_I	0x08
+#define INDEX_STORE_TAG_D	0x09
 #if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I	0x00
+#define HIT_INVALIDATE_I	0x00
 #else
-#define Hit_Invalidate_I	0x10
+#define HIT_INVALIDATE_I	0x10
 #endif
-#define Hit_Invalidate_D	0x11
-#define Hit_Writeback_Inv_D	0x15
+#define HIT_INVALIDATE_D	0x11
+#define HIT_WRITEBACK_INV_D	0x15
 
 /*
  * R4000-specific cacheops
  */
-#define Create_Dirty_Excl_D	0x0d
-#define Fill			0x14
-#define Hit_Writeback_I		0x18
-#define Hit_Writeback_D		0x19
+#define CREATE_DIRTY_EXCL_D	0x0d
+#define FILL			0x14
+#define HIT_WRITEBACK_I		0x18
+#define HIT_WRITEBACK_D		0x19
 
 /*
  * R4000SC and R4400SC-specific cacheops
  */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_SI	0x06
-#define Index_Load_Tag_SD	0x07
-#define Index_Store_Tag_SI	0x0A
-#define Index_Store_Tag_SD	0x0B
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_SI	0x12
-#define Hit_Invalidate_SD	0x13
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_SD	0x1b
-#define Hit_Set_Virtual_SI	0x1e
-#define Hit_Set_Virtual_SD	0x1f
+#define INDEX_INVALIDATE_SI     0x02
+#define INDEX_WRITEBACK_INV_SD  0x03
+#define INDEX_LOAD_TAG_SI	0x06
+#define INDEX_LOAD_TAG_SD	0x07
+#define INDEX_STORE_TAG_SI	0x0A
+#define INDEX_STORE_TAG_SD	0x0B
+#define CREATE_DIRTY_EXCL_SD	0x0f
+#define HIT_INVALIDATE_SI	0x12
+#define HIT_INVALIDATE_SD	0x13
+#define HIT_WRITEBACK_INV_SD	0x17
+#define HIT_WRITEBACK_SD	0x1b
+#define HIT_SET_VIRTUAL_SI	0x1e
+#define HIT_SET_VIRTUAL_SD	0x1f
 
 /*
  * R5000-specific cacheops
  */
-#define R5K_Page_Invalidate_S	0x17
+#define R5K_PAGE_INVALIDATE_S	0x17
 
 /*
  * RM7000-specific cacheops
  */
-#define Page_Invalidate_T	0x16
+#define PAGE_INVALIDATE_T	0x16
 
 /*
  * R10000-specific cacheops
@@ -69,17 +69,17 @@
  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
  */
-#define Index_Writeback_Inv_S	0x03
-#define Index_Load_Tag_S	0x07
-#define Index_Store_Tag_S	0x0B
-#define Hit_Invalidate_S	0x13
-#define Cache_Barrier		0x14
-#define Hit_Writeback_Inv_S	0x17
-#define Index_Load_Data_I	0x18
-#define Index_Load_Data_D	0x19
-#define Index_Load_Data_S	0x1b
-#define Index_Store_Data_I	0x1c
-#define Index_Store_Data_D	0x1d
-#define Index_Store_Data_S	0x1f
+#define INDEX_WRITEBACK_INV_S	0x03
+#define INDEX_LOAD_TAG_S	0x07
+#define INDEX_STORE_TAG_S	0x0B
+#define HIT_INVALIDATE_S	0x13
+#define CACHE_BARRIER		0x14
+#define HIT_WRITEBACK_INV_S	0x17
+#define INDEX_LOAD_DATA_I	0x18
+#define INDEX_LOAD_DATA_D	0x19
+#define INDEX_LOAD_DATA_S	0x1b
+#define INDEX_STORE_DATA_I	0x1c
+#define INDEX_STORE_DATA_D	0x1d
+#define INDEX_STORE_DATA_S	0x1f
 
 #endif	/* __ASM_CACHEOPS_H */
diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h
index 6e2cdc7..a735a8a 100644
--- a/arch/mips/include/asm/global_data.h
+++ b/arch/mips/include/asm/global_data.h
@@ -48,7 +48,7 @@ typedef	struct	global_data {
 	unsigned long	tbl;
 	unsigned long	lastinc;
 #endif
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long base)
  */
 extern inline phys_addr_t virt_to_phys(volatile void * address)
 {
+#ifndef CONFIG_64BIT
 	return CPHYSADDR(address);
+#else
+	return XPHYSADDR(address);
+#endif
 }
 
 extern inline void * phys_to_virt(unsigned long address)
 {
+#ifndef CONFIG_64BIT
 	return (void *)KSEG0ADDR(address);
+#else
+	return (void *)CKSEG0ADDR(address);
+#endif
 }
 
 /*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long address)
  */
 extern inline unsigned long virt_to_bus(volatile void * address)
 {
+#ifndef CONFIG_64BIT
 	return CPHYSADDR(address);
+#else
+	return XPHYSADDR(address);
+#endif
 }
 
 extern inline void * bus_to_virt(unsigned long address)
 {
+#ifndef CONFIG_64BIT
 	return (void *)KSEG0ADDR(address);
+#else
+	return (void *)CKSEG0ADDR(address);
+#endif
 }
 
 /*
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
index 879aae2..4deac52 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int		__kernel_pid_t;
 typedef int		__kernel_ipc_pid_t;
 typedef int		__kernel_uid_t;
 typedef int		__kernel_gid_t;
+#if _MIPS_SZLONG != 64
 typedef unsigned int	__kernel_size_t;
 typedef int		__kernel_ssize_t;
 typedef int		__kernel_ptrdiff_t;
+#else
+typedef unsigned long	__kernel_size_t;
+typedef long		__kernel_ssize_t;
+typedef long		__kernel_ptrdiff_t;
+#endif
 typedef long		__kernel_time_t;
 typedef long		__kernel_suseconds_t;
 typedef long		__kernel_clock_t;
diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h
index 590649a..5fa4a6a 100644
--- a/arch/mips/include/asm/u-boot.h
+++ b/arch/mips/include/asm/u-boot.h
@@ -32,7 +32,7 @@
 #define _U_BOOT_H_	1
 
 typedef struct bd_info {
-	int		bi_baudrate;	/* serial console baudrate */
+	unsigned int	bi_baudrate;	/* serial console baudrate */
 	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_memstart;	/* start of DRAM memory */
diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c
index b14b33e..7ddd778 100644
--- a/arch/mips/lib/board.c
+++ b/arch/mips/lib/board.c
@@ -266,8 +266,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/*
 	 * We have to relocate the command table manually
 	 */
-	fixup_cmdtable(&__u_boot_cmd_start,
-		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+			ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	/* there are some other pointer constants we must deal with */
diff --git a/arch/nds32/cpu/n1213/u-boot.lds b/arch/nds32/cpu/n1213/u-boot.lds
index 1903420..cef19c5 100644
--- a/arch/nds32/cpu/n1213/u-boot.lds
+++ b/arch/nds32/cpu/n1213/u-boot.lds
@@ -52,9 +52,11 @@ SECTIONS
 	}
 
 	. = .;
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 
diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h
index 94bd4c2..b1feb2c 100644
--- a/arch/nds32/include/asm/global_data.h
+++ b/arch/nds32/include/asm/global_data.h
@@ -44,7 +44,7 @@
 typedef	struct global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 
 	unsigned long	reloc_off;	/* Relocation Offset */
diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h
index b533fea..7b8d8e4 100644
--- a/arch/nds32/include/asm/u-boot.h
+++ b/arch/nds32/include/asm/u-boot.h
@@ -39,7 +39,7 @@
 #include <environment.h>
 
 typedef struct bd_info {
-	int		bi_baudrate;	/* serial console baudrate */
+	unsigned int	bi_baudrate;	/* serial console baudrate */
 	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_memstart;	/* start of DRAM memory */
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 89900fe..91395ca 100644
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
@@ -320,8 +320,8 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/*
 	 * We have to relocate the command table manually
 	 */
-	fixup_cmdtable(&__u_boot_cmd_start,
-		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+			ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 	serial_initialize();
@@ -396,7 +396,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 	/* Initialize from environment */
 	load_addr = getenv_ulong("loadaddr", 16, load_addr);
 
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
 	board_late_init();
 #endif
 
diff --git a/arch/nios2/cpu/u-boot.lds b/arch/nios2/cpu/u-boot.lds
index 4856bd3..d0eb80d 100644
--- a/arch/nios2/cpu/u-boot.lds
+++ b/arch/nios2/cpu/u-boot.lds
@@ -45,13 +45,11 @@ SECTIONS
 	 * the initialization code relocates the command table as
 	 * well -- admittedly, this is just pure laziness ;-)
 	 */
-	__u_boot_cmd_start = .;
-	.u_boot_cmd :
-	{
-	  *(.u_boot_cmd)
-	}
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	/* INIT DATA sections - "Small" data (see the gcc -G option)
 	 * is always gp-relative. Here we make all init data sections
diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h
index 3b0d9e6..413b485 100644
--- a/arch/nios2/include/asm/global_data.h
+++ b/arch/nios2/include/asm/global_data.h
@@ -26,7 +26,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz!		*/
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h
index 315ef8b..e591237 100644
--- a/arch/nios2/include/asm/u-boot.h
+++ b/arch/nios2/include/asm/u-boot.h
@@ -39,7 +39,7 @@ typedef struct bd_info {
 	unsigned long	bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
-	unsigned long	bi_baudrate;	/* Console Baudrate */
+	unsigned int	bi_baudrate;	/* Console Baudrate */
 } bd_t;
 
 /* For image.h:image_check_target_arch() */
diff --git a/arch/openrisc/include/asm/global_data.h b/arch/openrisc/include/asm/global_data.h
index 6a0c0cc..96f3f1c 100644
--- a/arch/openrisc/include/asm/global_data.h
+++ b/arch/openrisc/include/asm/global_data.h
@@ -35,7 +35,7 @@
 typedef struct global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	have_console;	/* serial_init() was called */
 	phys_size_t	ram_size;	/* RAM size */
diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h
index 76b8132..f2f31d3 100644
--- a/arch/openrisc/include/asm/u-boot.h
+++ b/arch/openrisc/include/asm/u-boot.h
@@ -32,7 +32,7 @@
 #define _U_BOOT_H_
 
 typedef struct bd_info {
-	unsigned long	bi_baudrate;	/* serial console baudrate */
+	unsigned int	bi_baudrate;	/* serial console baudrate */
 	unsigned long	bi_arch_number;	/* unique id for this board */
 	unsigned long	bi_boot_params;	/* where this board expects params */
 	unsigned long	bi_memstart;	/* start of DRAM memory */
diff --git a/arch/powerpc/cpu/74xx_7xx/traps.c b/arch/powerpc/cpu/74xx_7xx/traps.c
index 7ae81eb..a33e283 100644
--- a/arch/powerpc/cpu/74xx_7xx/traps.c
+++ b/arch/powerpc/cpu/74xx_7xx/traps.c
@@ -48,8 +48,7 @@ extern unsigned long search_exception_table(unsigned long);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -69,8 +68,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void
-show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -100,16 +98,14 @@ show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
 }
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -152,8 +148,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -164,8 +159,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 	unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
 	int i, j;
@@ -190,8 +184,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -202,9 +195,7 @@ SoftEmuException(struct pt_regs *regs)
 	panic("Software Emulation Exception");
 }
 
-
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -218,8 +209,7 @@ UnknownException(struct pt_regs *regs)
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int	retval;
diff --git a/arch/powerpc/cpu/74xx_7xx/u-boot.lds b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
index 24823cd..ecee439 100644
--- a/arch/powerpc/cpu/74xx_7xx/u-boot.lds
+++ b/arch/powerpc/cpu/74xx_7xx/u-boot.lds
@@ -62,9 +62,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc512x/traps.c b/arch/powerpc/cpu/mpc512x/traps.c
index 786f4a5..15468e5 100644
--- a/arch/powerpc/cpu/mpc512x/traps.c
+++ b/arch/powerpc/cpu/mpc512x/traps.c
@@ -47,68 +47,65 @@ extern ulong get_effective_memsize(void);
  * Trap & Exception support
  */
 
-void
-print_backtrace (unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
 
-	puts ("Call backtrace: ");
+	puts("Call backtrace: ");
 	while (sp) {
 		if ((uint)sp > END_OF_MEM)
 			break;
 
 		i = sp[1];
 		if (cnt++ % 7 == 0)
-			putc ('\n');
-		printf ("%08lX ", i);
+			putc('\n');
+		printf("%08lX ", i);
 		if (cnt > 32) break;
 		sp = (unsigned long *) *sp;
 	}
-	putc ('\n');
+	putc('\n');
 }
 
-void show_regs (struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
-	printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
 	       regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
-	printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
 	       regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
 	       regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0,
 	       regs->msr & MSR_IR ? 1 : 0,
 	       regs->msr & MSR_DR ? 1 : 0);
 
-	putc ('\n');
+	putc('\n');
 	for (i = 0;  i < 32;  i++) {
 		if ((i % 8) == 0) {
-			printf ("GPR%02d: ", i);
+			printf("GPR%02d: ", i);
 		}
 
-		printf ("%08lX ", regs->gpr[i]);
+		printf("%08lX ", regs->gpr[i]);
 		if ((i % 8) == 7) {
-			putc ('\n');
+			putc('\n');
 		}
 	}
 }
 
 
-void
-_exception (int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
-	show_regs (regs);
-	print_backtrace ((unsigned long *)regs->gpr[1]);
-	panic ("Exception at pc %lx signal %d", regs->nip,signr);
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Exception at pc %lx signal %d", regs->nip, signr);
 }
 
 
-void
-MachineCheckException (struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
-	unsigned long fixup;
+	unsigned long fixup = search_exception_table(regs->nip);
 
-	if ((fixup = search_exception_table (regs->nip)) != 0) {
+	if (fixup) {
 		regs->nip = fixup;
 		return;
 	}
@@ -118,95 +115,90 @@ MachineCheckException (struct pt_regs *regs)
 		return;
 #endif
 
-	puts ("Machine check.\nCaused by (from msr): ");
-	printf ("regs %p ",regs);
+	puts("Machine check.\nCaused by (from msr): ");
+	printf("regs %p ", regs);
 	switch (regs->msr & 0x00FF0000) {
 	case (0x80000000 >> 10):
-		puts ("Instruction cache parity signal\n");
+		puts("Instruction cache parity signal\n");
 		break;
 	case (0x80000000 >> 11):
-		puts ("Data cache parity signal\n");
+		puts("Data cache parity signal\n");
 		break;
 	case (0x80000000 >> 12):
-		puts ("Machine check signal\n");
+		puts("Machine check signal\n");
 		break;
 	case (0x80000000 >> 13):
-		puts ("Transfer error ack signal\n");
+		puts("Transfer error ack signal\n");
 		break;
 	case (0x80000000 >> 14):
-		puts ("Data parity signal\n");
+		puts("Data parity signal\n");
 		break;
 	case (0x80000000 >> 15):
-		puts ("Address parity signal\n");
+		puts("Address parity signal\n");
 		break;
 	default:
-		puts ("Unknown values in msr\n");
+		puts("Unknown values in msr\n");
 	}
-	show_regs (regs);
-	print_backtrace ((unsigned long *)regs->gpr[1]);
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
 
-	panic ("machine check");
+	panic("machine check");
 }
 
-void
-AlignmentException (struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #ifdef CONFIG_CMD_KGDB
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	show_regs (regs);
-	print_backtrace ((unsigned long *)regs->gpr[1]);
-	panic ("Alignment Exception");
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException (struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 #ifdef CONFIG_CMD_KGDB
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	show_regs (regs);
-	print_backtrace ((unsigned long *)regs->gpr[1]);
-	panic ("Program Check Exception");
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Program Check Exception");
 }
 
-void
-SoftEmuException (struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #ifdef CONFIG_CMD_KGDB
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	show_regs (regs);
-	print_backtrace ((unsigned long *)regs->gpr[1]);
-	panic ("Software Emulation Exception");
+	show_regs(regs);
+	print_backtrace((unsigned long *)regs->gpr[1]);
+	panic("Software Emulation Exception");
 }
 
 
-void
-UnknownException (struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #ifdef CONFIG_CMD_KGDB
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
 	       regs->nip, regs->msr, regs->trap);
-	_exception (0, regs);
+	_exception(0, regs);
 }
 
 #ifdef CONFIG_CMD_BEDBUG
-extern void do_bedbug_breakpoint (struct pt_regs *);
+extern void do_bedbug_breakpoint(struct pt_regs *);
 #endif
 
-void
-DebugException (struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
-	printf ("Debugger trap at @ %lx\n", regs->nip );
-	show_regs (regs);
+	printf("Debugger trap at @ %lx\n", regs->nip);
+	show_regs(regs);
 #ifdef CONFIG_CMD_BEDBUG
-	do_bedbug_breakpoint (regs);
+	do_bedbug_breakpoint(regs);
 #endif
 }
diff --git a/arch/powerpc/cpu/mpc512x/u-boot.lds b/arch/powerpc/cpu/mpc512x/u-boot.lds
index 7a4d927..7faefba 100644
--- a/arch/powerpc/cpu/mpc512x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc512x/u-boot.lds
@@ -57,9 +57,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc5xx/serial.c b/arch/powerpc/cpu/mpc5xx/serial.c
index 6ef8be8..732856a 100644
--- a/arch/powerpc/cpu/mpc5xx/serial.c
+++ b/arch/powerpc/cpu/mpc5xx/serial.c
@@ -161,21 +161,13 @@ static void mpc5xx_serial_setbrg(void)
 #endif
 }
 
-static void mpc5xx_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc(*s);
-		++s;
-	}
-}
-
 static struct serial_device mpc5xx_serial_drv = {
 	.name	= "mpc5xx_serial",
 	.start	= mpc5xx_serial_init,
 	.stop	= NULL,
 	.setbrg	= mpc5xx_serial_setbrg,
 	.putc	= mpc5xx_serial_putc,
-	.puts	= mpc5xx_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= mpc5xx_serial_getc,
 	.tstc	= mpc5xx_serial_tstc,
 };
diff --git a/arch/powerpc/cpu/mpc5xx/traps.c b/arch/powerpc/cpu/mpc5xx/traps.c
index e3ce11b..90da73b 100644
--- a/arch/powerpc/cpu/mpc5xx/traps.c
+++ b/arch/powerpc/cpu/mpc5xx/traps.c
@@ -52,7 +52,7 @@ extern unsigned long search_exception_table(unsigned long);
 /*
  * Print stack backtrace
  */
-void print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -75,7 +75,7 @@ void print_backtrace(unsigned long *sp)
 /*
  * Print current registers
  */
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
@@ -105,7 +105,7 @@ void show_regs(struct pt_regs * regs)
 /*
  * General exception handler routine
  */
-void _exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
diff --git a/arch/powerpc/cpu/mpc5xx/u-boot.lds b/arch/powerpc/cpu/mpc5xx/u-boot.lds
index e02b213..c91e146 100644
--- a/arch/powerpc/cpu/mpc5xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xx/u-boot.lds
@@ -65,9 +65,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc5xxx/traps.c b/arch/powerpc/cpu/mpc5xxx/traps.c
index 5972f34..438f8d3 100644
--- a/arch/powerpc/cpu/mpc5xxx/traps.c
+++ b/arch/powerpc/cpu/mpc5xxx/traps.c
@@ -49,8 +49,7 @@ extern unsigned long search_exception_table(unsigned long);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -70,7 +69,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -98,16 +97,14 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
 }
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -152,8 +149,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -164,8 +160,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -176,8 +171,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -189,8 +183,7 @@ SoftEmuException(struct pt_regs *regs)
 }
 
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -205,8 +198,7 @@ UnknownException(struct pt_regs *regs)
 extern void do_bedbug_breakpoint(struct pt_regs *);
 #endif
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 
   printf("Debugger trap at @ %lx\n", regs->nip );
@@ -219,8 +211,7 @@ DebugException(struct pt_regs *regs)
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int	retval;
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
index 0c6c54e..ac7844d 100644
--- a/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds
@@ -66,10 +66,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
 
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc5xxx/u-boot.lds b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
index 5dcaec1..1f46ead 100644
--- a/arch/powerpc/cpu/mpc5xxx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc5xxx/u-boot.lds
@@ -60,9 +60,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc8220/traps.c b/arch/powerpc/cpu/mpc8220/traps.c
index 13894c9..19d6cb5 100644
--- a/arch/powerpc/cpu/mpc8220/traps.c
+++ b/arch/powerpc/cpu/mpc8220/traps.c
@@ -39,7 +39,7 @@
 #include <asm/processor.h>
 
 /* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table (unsigned long);
+extern unsigned long search_exception_table(unsigned long);
 
 /* THIS NEEDS CHANGING to use the board info structure.
 */
@@ -49,171 +49,166 @@ extern unsigned long search_exception_table (unsigned long);
  * Trap & Exception support
  */
 
-void print_backtrace (unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
 
-	printf ("Call backtrace: ");
+	printf("Call backtrace: ");
 	while (sp) {
 		if ((uint) sp > END_OF_MEM)
 			break;
 
 		i = sp[1];
 		if (cnt++ % 7 == 0)
-			printf ("\n");
-		printf ("%08lX ", i);
+			printf("\n");
+		printf("%08lX ", i);
 		if (cnt > 32)
 			break;
 		sp = (unsigned long *) *sp;
 	}
-	printf ("\n");
+	printf("\n");
 }
 
-void show_regs (struct pt_regs *regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
-	printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
+	printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n",
 		regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
-	printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
+	printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
 		regs->msr,
 		regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0,
 		regs->msr & MSR_FP ? 1 : 0, regs->msr & MSR_ME ? 1 : 0,
 		regs->msr & MSR_IR ? 1 : 0, regs->msr & MSR_DR ? 1 : 0);
 
-	printf ("\n");
+	printf("\n");
 	for (i = 0; i < 32; i++) {
 		if ((i % 8) == 0) {
-			printf ("GPR%02d: ", i);
+			printf("GPR%02d: ", i);
 		}
 
-		printf ("%08lX ", regs->gpr[i]);
+		printf("%08lX ", regs->gpr[i]);
 		if ((i % 8) == 7) {
-			printf ("\n");
+			printf("\n");
 		}
 	}
 }
 
 
-void _exception (int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
-	show_regs (regs);
-	print_backtrace ((unsigned long *) regs->gpr[1]);
-	panic ("Exception in kernel pc %lx signal %d", regs->nip, signr);
+	show_regs(regs);
+	print_backtrace((unsigned long *) regs->gpr[1]);
+	panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
 }
 
-void MachineCheckException (struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
-	unsigned long fixup;
+	unsigned long fixup = search_exception_table(regs->nip);
 
 	/* Probing PCI using config cycles cause this exception
 	 * when a device is not present.  Catch it and return to
 	 * the PCI exception handler.
 	 */
-	if ((fixup = search_exception_table (regs->nip)) != 0) {
+	if (fixup) {
 		regs->nip = fixup;
 		return;
 	}
 #if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler
-	    && (*debugger_exception_handler) (regs))
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
 
-	printf ("Machine check in kernel mode.\n");
-	printf ("Caused by (from msr): ");
-	printf ("regs %p ", regs);
+	printf("Machine check in kernel mode.\n");
+	printf("Caused by (from msr): ");
+	printf("regs %p ", regs);
 	/* refer to 603e Manual (MPC603EUM/AD), chapter 4.5.2.1 */
 	switch (regs->msr & 0x000F0000) {
 	case (0x80000000 >> 12):
-		printf ("Machine check signal - probably due to mm fault\n"
+		printf("Machine check signal - probably due to mm fault\n"
 			"with mmu off\n");
 		break;
 	case (0x80000000 >> 13):
-		printf ("Transfer error ack signal\n");
+		printf("Transfer error ack signal\n");
 		break;
 	case (0x80000000 >> 14):
-		printf ("Data parity signal\n");
+		printf("Data parity signal\n");
 		break;
 	case (0x80000000 >> 15):
-		printf ("Address parity signal\n");
+		printf("Address parity signal\n");
 		break;
 	default:
-		printf ("Unknown values in msr\n");
+		printf("Unknown values in msr\n");
 	}
-	show_regs (regs);
-	print_backtrace ((unsigned long *) regs->gpr[1]);
-	panic ("machine check");
+	show_regs(regs);
+	print_backtrace((unsigned long *) regs->gpr[1]);
+	panic("machine check");
 }
 
-void AlignmentException (struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler
-	    && (*debugger_exception_handler) (regs))
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	show_regs (regs);
-	print_backtrace ((unsigned long *) regs->gpr[1]);
-	panic ("Alignment Exception");
+	show_regs(regs);
+	print_backtrace((unsigned long *) regs->gpr[1]);
+	panic("Alignment Exception");
 }
 
-void ProgramCheckException (struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler
-	    && (*debugger_exception_handler) (regs))
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	show_regs (regs);
-	print_backtrace ((unsigned long *) regs->gpr[1]);
-	panic ("Program Check Exception");
+	show_regs(regs);
+	print_backtrace((unsigned long *) regs->gpr[1]);
+	panic("Program Check Exception");
 }
 
-void SoftEmuException (struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler
-	    && (*debugger_exception_handler) (regs))
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	show_regs (regs);
-	print_backtrace ((unsigned long *) regs->gpr[1]);
-	panic ("Software Emulation Exception");
+	show_regs(regs);
+	print_backtrace((unsigned long *) regs->gpr[1]);
+	panic("Software Emulation Exception");
 }
 
 
-void UnknownException (struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
-	if (debugger_exception_handler
-	    && (*debugger_exception_handler) (regs))
+	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
 		return;
 #endif
-	printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
+	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
 		regs->nip, regs->msr, regs->trap);
-	_exception (0, regs);
+	_exception(0, regs);
 }
 
 #if defined(CONFIG_CMD_BEDBUG)
-extern void do_bedbug_breakpoint (struct pt_regs *);
+extern void do_bedbug_breakpoint(struct pt_regs *);
 #endif
 
-void DebugException (struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 
-	printf ("Debugger trap at @ %lx\n", regs->nip);
-	show_regs (regs);
+	printf("Debugger trap at @ %lx\n", regs->nip);
+	show_regs(regs);
 #if defined(CONFIG_CMD_BEDBUG)
-	do_bedbug_breakpoint (regs);
+	do_bedbug_breakpoint(regs);
 #endif
 }
 
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int addr_probe (uint * addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int retval;
diff --git a/arch/powerpc/cpu/mpc8220/u-boot.lds b/arch/powerpc/cpu/mpc8220/u-boot.lds
index 39bb42e..c147954 100644
--- a/arch/powerpc/cpu/mpc8220/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8220/u-boot.lds
@@ -59,9 +59,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc8220/uart.c b/arch/powerpc/cpu/mpc8220/uart.c
index 25d4472..772528f 100644
--- a/arch/powerpc/cpu/mpc8220/uart.c
+++ b/arch/powerpc/cpu/mpc8220/uart.c
@@ -84,13 +84,6 @@ static void mpc8220_serial_putc(const char c)
 	psc->xmitbuf[0] = c;
 }
 
-static void mpc8220_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static int mpc8220_serial_getc(void)
 {
 	volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
@@ -132,7 +125,7 @@ static struct serial_device mpc8220_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= mpc8220_serial_setbrg,
 	.putc	= mpc8220_serial_putc,
-	.puts	= mpc8220_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= mpc8220_serial_getc,
 	.tstc	= mpc8220_serial_tstc,
 };
diff --git a/arch/powerpc/cpu/mpc824x/cpu_init.c b/arch/powerpc/cpu/mpc824x/cpu_init.c
index 395f776..cfc665d 100644
--- a/arch/powerpc/cpu/mpc824x/cpu_init.c
+++ b/arch/powerpc/cpu/mpc824x/cpu_init.c
@@ -63,7 +63,7 @@ void
 cpu_init_f (void)
 {
 /* MOUSSE board is initialized in asm */
-#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
+#if !defined(CONFIG_MOUSSE)
     register unsigned long val;
     CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
 /*    CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
@@ -321,7 +321,7 @@ cpu_init_f (void)
 	CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
 	__asm__ __volatile__("eieio");
 
-#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
+#endif /* !CONFIG_MOUSSE */
 }
 
 
diff --git a/arch/powerpc/cpu/mpc824x/start.S b/arch/powerpc/cpu/mpc824x/start.S
index 70db73e..076df70 100644
--- a/arch/powerpc/cpu/mpc824x/start.S
+++ b/arch/powerpc/cpu/mpc824x/start.S
@@ -113,9 +113,6 @@ _start:
 
 
 in_flash:
-#if defined(CONFIG_BMW)
-	bl early_init_f /* Must be ASM: no stack yet! */
-#endif
 	/*
 	 * Setup BATs - cannot be done in C since we don't have a stack yet
 	 */
@@ -126,7 +123,7 @@ in_flash:
 	mfmsr	r3
 	ori	r3, r3, (MSR_IR | MSR_DR)
 	mtmsr	r3
-#if !defined(CONFIG_BMW)
+
 	/* Enable and invalidate data cache.
 	 */
 	mfspr	r3, HID0
@@ -158,7 +155,7 @@ in_flash:
 	ori	r3, r3, 0x0080
 	sync
 	mtspr	1011, r3
-#endif /* !CONFIG_BMW */
+
 	/*
 	 * Thisk the stack pointer *somewhere* sensible. Doesnt
 	 * matter much where as we'll move it when we relocate
@@ -498,7 +495,6 @@ relocate_code:
 	bdnz	3b
 
 4:
-#if !defined(CONFIG_BMW)
 /* Unlock the data cache and invalidate locked area */
 	xor	r0, r0, r0
 	mtspr	1011, r0
@@ -510,7 +506,6 @@ relocate_code:
 	dcbi	r0, r4
 	addi	r4, r4, 32
 	bdnz	41b
-#endif
 
 /*
  * Now flush the cache: note that we must start from a cache aligned
diff --git a/arch/powerpc/cpu/mpc824x/traps.c b/arch/powerpc/cpu/mpc824x/traps.c
index 163b983..9bcdd8f 100644
--- a/arch/powerpc/cpu/mpc824x/traps.c
+++ b/arch/powerpc/cpu/mpc824x/traps.c
@@ -46,8 +46,7 @@ extern unsigned long search_exception_table(unsigned long);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -67,7 +66,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -95,16 +94,14 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
 }
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -142,24 +139,21 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
@@ -167,8 +161,7 @@ SoftEmuException(struct pt_regs *regs)
 }
 
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 	printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
 	       regs->nip, regs->msr, regs->trap);
@@ -179,8 +172,7 @@ UnknownException(struct pt_regs *regs)
 extern void do_bedbug_breakpoint(struct pt_regs *);
 #endif
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 
   printf("Debugger trap at @ %lx\n", regs->nip );
@@ -193,8 +185,7 @@ DebugException(struct pt_regs *regs)
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int	retval;
diff --git a/arch/powerpc/cpu/mpc824x/u-boot.lds b/arch/powerpc/cpu/mpc824x/u-boot.lds
index b30ce76..a713012 100644
--- a/arch/powerpc/cpu/mpc824x/u-boot.lds
+++ b/arch/powerpc/cpu/mpc824x/u-boot.lds
@@ -60,9 +60,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc8260/serial_scc.c b/arch/powerpc/cpu/mpc8260/serial_scc.c
index ab77558..ab2a2b2 100644
--- a/arch/powerpc/cpu/mpc8260/serial_scc.c
+++ b/arch/powerpc/cpu/mpc8260/serial_scc.c
@@ -217,13 +217,6 @@ static void mpc8260_scc_serial_putc(const char c)
 	tbdf->cbd_sc |= BD_SC_READY;
 }
 
-static void mpc8260_scc_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static int mpc8260_scc_serial_getc(void)
 {
 	volatile cbd_t		*rbdf;
@@ -267,7 +260,7 @@ static struct serial_device mpc8260_scc_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= mpc8260_scc_serial_setbrg,
 	.putc	= mpc8260_scc_serial_putc,
-	.puts	= mpc8260_scc_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= mpc8260_scc_serial_getc,
 	.tstc	= mpc8260_scc_serial_tstc,
 };
diff --git a/arch/powerpc/cpu/mpc8260/serial_smc.c b/arch/powerpc/cpu/mpc8260/serial_smc.c
index 7edde9a..feba1f6 100644
--- a/arch/powerpc/cpu/mpc8260/serial_smc.c
+++ b/arch/powerpc/cpu/mpc8260/serial_smc.c
@@ -216,13 +216,6 @@ static void mpc8260_smc_serial_putc(const char c)
 	rtx->txbd.cbd_sc |= BD_SC_READY;
 }
 
-static void mpc8260_smc_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static int mpc8260_smc_serial_getc(void)
 {
 	volatile smc_uart_t	*up;
@@ -270,7 +263,7 @@ static struct serial_device mpc8260_smc_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= mpc8260_smc_serial_setbrg,
 	.putc	= mpc8260_smc_serial_putc,
-	.puts	= mpc8260_smc_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= mpc8260_smc_serial_getc,
 	.tstc	= mpc8260_smc_serial_tstc,
 };
diff --git a/arch/powerpc/cpu/mpc8260/traps.c b/arch/powerpc/cpu/mpc8260/traps.c
index c116cdf..e1e6845 100644
--- a/arch/powerpc/cpu/mpc8260/traps.c
+++ b/arch/powerpc/cpu/mpc8260/traps.c
@@ -49,8 +49,7 @@ extern unsigned long search_exception_table(unsigned long);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -70,7 +69,7 @@ print_backtrace(unsigned long *sp)
 	putc ('\n');
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -96,8 +95,7 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
@@ -122,8 +120,7 @@ void dump_pci (void)
 }
 #endif
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -180,8 +177,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -192,8 +188,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -204,8 +199,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -217,8 +211,7 @@ SoftEmuException(struct pt_regs *regs)
 }
 
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -233,8 +226,7 @@ UnknownException(struct pt_regs *regs)
 extern void do_bedbug_breakpoint(struct pt_regs *);
 #endif
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 
   printf("Debugger trap at @ %lx\n", regs->nip );
@@ -247,8 +239,7 @@ DebugException(struct pt_regs *regs)
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int	retval;
diff --git a/arch/powerpc/cpu/mpc8260/u-boot.lds b/arch/powerpc/cpu/mpc8260/u-boot.lds
index 60b71ec..42385fc 100644
--- a/arch/powerpc/cpu/mpc8260/u-boot.lds
+++ b/arch/powerpc/cpu/mpc8260/u-boot.lds
@@ -59,9 +59,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index 6635109..e64b0c3 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -56,6 +56,7 @@ int checkcpu(void)
 		u32 partid;
 	} cpu_type_list [] = {
 		CPU_TYPE_ENTRY(8308),
+		CPU_TYPE_ENTRY(8309),
 		CPU_TYPE_ENTRY(8311),
 		CPU_TYPE_ENTRY(8313),
 		CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 76afba5..20d0600 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -268,6 +268,9 @@ void cpu_init_f (volatile immap_t * im)
 #ifdef CONFIG_SYS_SICRL
 	__raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 #endif
+#ifdef CONFIG_SYS_GPR1
+	__raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
+#endif
 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 	__raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 #endif
diff --git a/arch/powerpc/cpu/mpc83xx/fdt.c b/arch/powerpc/cpu/mpc83xx/fdt.c
index 028c8f0..1f54781 100644
--- a/arch/powerpc/cpu/mpc83xx/fdt.c
+++ b/arch/powerpc/cpu/mpc83xx/fdt.c
@@ -88,7 +88,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 				u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
 
 				path = fdt_path_offset(blob, prop);
-				prop = fdt_getprop(blob, path, "interrupts", 0);
+				prop = fdt_getprop(blob, path, "interrupts",
+						   NULL);
 				if (prop)
 					fdt_setprop(blob, path, "interrupts",
 						    &tmp, sizeof(tmp));
@@ -100,7 +101,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 				u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
 
 				path = fdt_path_offset(blob, prop);
-				prop = fdt_getprop(blob, path, "interrupts", 0);
+				prop = fdt_getprop(blob, path, "interrupts",
+						   NULL);
 				if (prop)
 					fdt_setprop(blob, path, "interrupts",
 						    &tmp, sizeof(tmp));
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index f78099d..b8c05d1 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -52,7 +52,7 @@ typedef struct {
 	mult_t vco_divider;
 } corecnf_t;
 
-corecnf_t corecnf_tab[] = {
+static corecnf_t corecnf_tab[] = {
 	{_byp, _byp},		/* 0x00 */
 	{_byp, _byp},		/* 0x01 */
 	{_byp, _byp},		/* 0x02 */
@@ -105,6 +105,8 @@ int get_clocks(void)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	u32 usbdr_clk;
 #endif
 #ifdef CONFIG_MPC834x
 	u32 usbmph_clk;
@@ -120,14 +122,16 @@ int get_clocks(void)
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
+#if !defined(CONFIG_MPC8309)
 	u32 enc_clk;
+#endif
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 mem_clk;
 #if defined(CONFIG_MPC8360)
 	u32 mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	u32 qepmf;
 	u32 qepdf;
 	u32 qe_clk;
@@ -185,7 +189,10 @@ int get_clocks(void)
 		/* unkown SCCR_TSEC1CM value */
 		return -2;
 	}
+#endif
 
+#if defined(CONFIG_MPC830x) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 	case 0:
 		usbdr_clk = 0;
@@ -260,6 +267,7 @@ int get_clocks(void)
 		return -6;
 	}
 #endif
+#if !defined(CONFIG_MPC8309)
 	switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 	case 0:
 		enc_clk = 0;
@@ -277,6 +285,7 @@ int get_clocks(void)
 		/* unkown SCCR_ENCCM value */
 		return -7;
 	}
+#endif
 
 #if defined(CONFIG_FSL_ESDHC)
 	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
@@ -329,6 +338,8 @@ int get_clocks(void)
 	i2c1_clk = sdhc_clk;
 #elif defined(CONFIG_MPC837x)
 	i2c1_clk = enc_clk;
+#elif defined(CONFIG_MPC8309)
+	i2c1_clk = csb_clk;
 #endif
 #if !defined(CONFIG_MPC832x)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
@@ -444,7 +455,7 @@ int get_clocks(void)
 		return -13;
 	}
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
 	qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -457,6 +468,8 @@ int get_clocks(void)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	gd->usbdr_clk = usbdr_clk;
 #endif
 #if defined(CONFIG_MPC834x)
 	gd->usbmph_clk = usbmph_clk;
@@ -472,14 +485,16 @@ int get_clocks(void)
 #if !defined(CONFIG_MPC832x)
 	gd->i2c2_clk = i2c2_clk;
 #endif
+#if !defined(CONFIG_MPC8309)
 	gd->enc_clk = enc_clk;
+#endif
 	gd->lbiu_clk = lbiu_clk;
 	gd->lclk_clk = lclk_clk;
 	gd->mem_clk = mem_clk;
 #if defined(CONFIG_MPC8360)
 	gd->mem_sec_clk = mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
@@ -516,14 +531,14 @@ ulong get_ddr_freq(ulong dummy)
 	return gd->mem_clk;
 }
 
-int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	char buf[32];
 
 	printf("Clock configuration:\n");
 	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
 	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
+#if defined(CONFIG_QE)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
 #endif
@@ -533,7 +548,9 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_MPC8360)
 	printf("  DDR Secondary:       %-4s MHz\n", strmhz(buf, gd->mem_sec_clk));
 #endif
+#if !defined(CONFIG_MPC8309)
 	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
+#endif
 	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
 #if !defined(CONFIG_MPC832x)
 	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
@@ -549,6 +566,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
+#elif defined(CONFIG_MPC8309)
+	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
 #endif
 #if defined(CONFIG_MPC834x)
 	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c
index 9d71b8b..53a1062 100644
--- a/arch/powerpc/cpu/mpc83xx/traps.c
+++ b/arch/powerpc/cpu/mpc83xx/traps.c
@@ -42,8 +42,7 @@ extern unsigned long search_exception_table(unsigned long);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -63,7 +62,7 @@ print_backtrace(unsigned long *sp)
 	putc ('\n');
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -89,8 +88,7 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
@@ -114,8 +112,7 @@ void dump_pci (void)
 }
 #endif
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -174,8 +171,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -186,8 +182,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -198,8 +193,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -211,8 +205,7 @@ SoftEmuException(struct pt_regs *regs)
 }
 
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -227,8 +220,7 @@ UnknownException(struct pt_regs *regs)
 extern void do_bedbug_breakpoint(struct pt_regs *);
 #endif
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 	printf("Debugger trap at @ %lx\n", regs->nip );
 	show_regs(regs);
@@ -240,8 +232,7 @@ DebugException(struct pt_regs *regs)
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int	retval;
diff --git a/arch/powerpc/cpu/mpc83xx/u-boot.lds b/arch/powerpc/cpu/mpc83xx/u-boot.lds
index 2f4b9ad..d699def 100644
--- a/arch/powerpc/cpu/mpc83xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc83xx/u-boot.lds
@@ -58,9 +58,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
 
   . = .;
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 33e93c8..78c412d 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -66,6 +66,9 @@ COBJS-$(CONFIG_PPC_P2041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P3041)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P4080)	+= ddr-gen3.o
 COBJS-$(CONFIG_PPC_P5020)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_P5040)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_T4240)	+= ddr-gen3.o
+COBJS-$(CONFIG_PPC_B4860)	+= ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)		+= ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)	+= ether_fcc.o
@@ -80,10 +83,14 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_ids.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o
 
 COBJS-$(CONFIG_QE)	+= qe_io.o
 COBJS-$(CONFIG_CPM2)	+= serial_scc.o
-COBJS-$(CONFIG_FSL_CORENET) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
+COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
 
 # SoC specific SERDES support
 COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
@@ -110,6 +117,9 @@ COBJS-$(CONFIG_PPC_P2041) += p2041_serdes.o
 COBJS-$(CONFIG_PPC_P3041) += p3041_serdes.o
 COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o
 COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o
+COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
+COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
+COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
 
 COBJS	= $(COBJS-y)
 COBJS	+= cpu.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
new file mode 100644
index 0000000..7d33731
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 0),
+	SET_QP_INFO(10, 36, 1, 0),
+	SET_QP_INFO(11, 37, 1, 1),
+	SET_QP_INFO(12, 38, 1, 1),
+	SET_QP_INFO(13, 39, 1, 2),
+	SET_QP_INFO(14, 40, 1, 2),
+	SET_QP_INFO(15, 41, 1, 3),
+	SET_QP_INFO(16, 42, 1, 3),
+	SET_QP_INFO(17, 43, 1, 0),
+	SET_QP_INFO(18, 44, 1, 0),
+	SET_QP_INFO(19, 45, 1, 1),
+	SET_QP_INFO(20, 46, 1, 1),
+	SET_QP_INFO(21, 47, 1, 2),
+	SET_QP_INFO(22, 48, 1, 2),
+	SET_QP_INFO(23, 49, 1, 3),
+	SET_QP_INFO(24, 50, 1, 3),
+	SET_QP_INFO(25, 51, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_1(1, 307),
+	SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+	SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+	SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+	SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+	SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+	SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+	SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 678),
+	SET_RMAN_LIODN(1, 679),
+	SET_RMAN_LIODN(2, 680),
+	SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
new file mode 100644
index 0000000..9990202
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+	u8 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x0E, {CPRI8, CPRI7,	CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x12, {CPRI8, CPRI7,	CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x30, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x32, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x33, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x34, {AURORA, AURORA,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{0x3E, {CPRI8, CPRI7,	CPRI6, CPRI5,
+		CPRI4, CPRI3, CPRI2, CPRI1}},
+	{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		AURORA, AURORA,	SRIO1, SRIO1}},
+	{0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA, SRIO1, SRIO1}},
+	{0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		AURORA, AURORA,
+		SRIO1, SRIO1}},
+	{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, AURORA,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2, AURORA, AURORA,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SRIO2, SRIO2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0x9E, {PCIE1, PCIE1,	PCIE1, PCIE1,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0x9A, {PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XFI_FM1_MAC9, XFI_FM1_MAC10}},
+	{0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index e8989bd..2be192d 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -76,11 +76,15 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
 	puts("Work-around for Erratum ESDHC111 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+	puts("Work-around for Erratum A004468 enabled\n");
+#endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
 	puts("Work-around for Erratum ESDHC135 enabled\n");
 #endif
-#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC136)
-	puts("Work-around for Erratum ESDHC136 enabled\n");
+#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
+	if (SVR_MAJ(svr) < 3)
+		puts("Work-around for Erratum ESDHC13 enabled\n");
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
 	puts("Work-around for Erratum ESDHC-A001 enabled\n");
@@ -127,6 +131,12 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 	puts("Work-around for Erratum A004510 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+	puts("Work-around for Erratum SRIO-A004034 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	puts("Work-around for Erratum A004934 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 5ddb294..db232e6 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -60,20 +60,32 @@ int checkcpu (void)
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
+#if (defined(CONFIG_DDR_CLK_FREQ) || \
+	defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
-	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#else
+
+	/*
+	 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
+	 * mode. Previous platform use ddr ratio to do the same. This
+	 * information is only for display here.
+	 */
 #ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	u32 ddr_sync = 0;	/* only async mode is supported */
+#else
 	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
 		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#else	/* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
 	u32 ddr_ratio = 0;
-#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_FSL_CORENET */
+
 	unsigned int i, core, nr_cores = cpu_numcores();
 	u32 mask = cpu_mask();
 
@@ -127,6 +139,11 @@ int checkcpu (void)
 
 	printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
 
+	if (nr_cores > CONFIG_MAX_CPUS) {
+		panic("\nUnexpected number of cores: %d, max is %d\n",
+			nr_cores, CONFIG_MAX_CPUS);
+	}
+
 	get_sys_info(&sysinfo);
 
 	puts("Clock Configuration:");
@@ -181,6 +198,10 @@ int checkcpu (void)
 	}
 #endif
 
+#if defined(CONFIG_FSL_IFC)
+	printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
+#endif
+
 #ifdef CONFIG_CPM2
 	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
@@ -196,6 +217,10 @@ int checkcpu (void)
 	}
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	printf("       QMAN:  %s MHz\n", strmhz(buf1, sysinfo.freqQMAN));
+#endif
+
 #ifdef CONFIG_SYS_DPAA_PME
 	printf("       PME:   %s MHz\n", strmhz(buf1, sysinfo.freqPME));
 #endif
@@ -270,10 +295,7 @@ reset_85xx_watchdog(void)
 	/*
 	 * Clear TSR(WIS) bit by writing 1
 	 */
-	unsigned long val;
-	val = mfspr(SPRN_TSR);
-	val |= TSR_WIS;
-	mtspr(SPRN_TSR, val);
+	mtspr(SPRN_TSR, TSR_WIS);
 }
 #endif	/* CONFIG_WATCHDOG */
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index afb5671..f01804b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -182,7 +182,7 @@ static void enable_cpc(void)
 	printf("Corenet Platform Cache: %d KB enabled\n", size);
 }
 
-void invalidate_cpc(void)
+static void invalidate_cpc(void)
 {
 	int i;
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
@@ -295,6 +295,43 @@ static void __fsl_serdes__init(void)
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int enable_cluster_l2(void)
+{
+	int i = 0;
+	u32 cluster;
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct ccsr_cluster_l2 __iomem *l2cache;
+
+	cluster = in_be32(&gur->tp_cluster[i].lower);
+	if (cluster & TP_CLUSTER_EOC)
+		return 0;
+
+	/* The first cache has already been set up, so skip it */
+	i++;
+
+	/* Look through the remaining clusters, and set up their caches */
+	do {
+		l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+		cluster = in_be32(&gur->tp_cluster[i].lower);
+
+		/* set stash ID to (cluster) * 2 + 32 + 1 */
+		clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
+
+		printf("enable l2 for cluster %d %p\n", i, l2cache);
+
+		out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
+		while ((in_be32(&l2cache->l2csr0) &
+			(L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
+			;
+		out_be32(&l2cache->l2csr0, L2CSR0_L2E);
+		i++;
+	} while (!(cluster & TP_CLUSTER_EOC));
+
+	return 0;
+}
+#endif
+
 /*
  * Initialize L2 as cache.
  *
@@ -306,7 +343,12 @@ int cpu_init_r(void)
 {
 	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_SYS_LBC_LCRR
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+	fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
+#endif
+#ifdef CONFIG_L2_CACHE
+	ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
@@ -356,7 +398,6 @@ int cpu_init_r(void)
 	puts ("L2:    ");
 
 #if defined(CONFIG_L2_CACHE)
-	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile uint cache_ctl;
 	uint ver;
 	u32 l2siz_field;
@@ -467,6 +508,11 @@ int cpu_init_r(void)
 	}
 
 skip_l2:
+#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+	if (l2cache->l2csr0 & L2CSR0_L2E)
+		printf("%d KB enabled\n", (l2cache->l2cfg0 & 0x3fff) * 64);
+
+	enable_cluster_l2();
 #else
 	puts("disabled\n");
 #endif
@@ -478,7 +524,7 @@ skip_l2:
 
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER 
 	char *s = getenv("bootmaster");
 	if (s) {
 		if (!strcmp(s, "SRIO1")) {
@@ -497,11 +543,13 @@ skip_l2:
 	setup_mp();
 #endif
 
-#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 	{
-		void *p;
-		p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
-		setbits_be32(p, 1 << (31 - 14));
+		if (SVR_MAJ(svr) < 3) {
+			void *p;
+			p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
+			setbits_be32(p, 1 << (31 - 14));
+		}
 	}
 #endif
 
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index ca4ed62..f118dd5 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -18,12 +18,14 @@
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			     unsigned int ctrl_num)
 {
-	unsigned int i;
+	unsigned int i, bus_width;
 	volatile ccsr_ddr_t *ddr;
 	u32 temp_sdram_cfg;
+	u32 total_gb_size_per_controller;
+	int timeout;
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	int timeout_save;
 	volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR;
-	u32 total_gb_size_per_controller;
 	unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t;
 	int csn = -1;
 #endif
@@ -52,8 +54,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 		return;
 	}
 
-	out_be32(&ddr->eor, regs->ddr_eor);
-
+	if (regs->ddr_eor)
+		out_be32(&ddr->eor, regs->ddr_eor);
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	debug("Workaround for ERRATUM_DDR111_DDR134\n");
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
@@ -121,6 +123,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
 	out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 	out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
+	if (regs->ddr_wrlvl_cntl_2)
+		out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
+	if (regs->ddr_wrlvl_cntl_3)
+		out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
+
 	out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
 	out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
 	out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
@@ -134,6 +141,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			out_be32(&ddr->debug[i], regs->debug[i]);
 		}
 	}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	out_be32(&ddr->debug[28], 0x00003000);
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 	out_be32(&ddr->debug[12], 0x00000015);
@@ -270,9 +280,48 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 	asm volatile("sync;isync");
 
+	total_gb_size_per_controller = 0;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (!(regs->cs[i].config & 0x80000000))
+			continue;
+		total_gb_size_per_controller += 1 << (
+			((regs->cs[i].config >> 14) & 0x3) + 2 +
+			((regs->cs[i].config >> 8) & 0x7) + 12 +
+			((regs->cs[i].config >> 0) & 0x7) + 8 +
+			3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
+			26);			/* minus 26 (count of 64M) */
+	}
+	if (fsl_ddr_get_intl3r() & 0x80000000)	/* 3-way interleaving */
+		total_gb_size_per_controller *= 3;
+	else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
+		total_gb_size_per_controller <<= 1;
+	/*
+	 * total memory / bus width = transactions needed
+	 * transactions needed / data rate = seconds
+	 * to add plenty of buffer, double the time
+	 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+	 * Let's wait for 800ms
+	 */
+	bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK)
+			>> SDRAM_CFG_DBW_SHIFT);
+	timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
+		(get_ddr_freq(0) >> 20)) << 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+	timeout_save = timeout;
+#endif
+	total_gb_size_per_controller >>= 4;	/* shift down to gb size */
+	debug("total %d GB\n", total_gb_size_per_controller);
+	debug("Need to wait up to %d * 10ms\n", timeout);
+
 	/* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
-	while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
+	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
 		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
 	/* continue this workaround */
@@ -330,23 +379,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	while (in_be32(&ddr->debug[1]) & 0x400)
 		udelay(10000);          /* throttle polling rate */
 
-	/* 7. Wait for 400ms/GB */
-	total_gb_size_per_controller = 0;
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		if (i == csn) {
-			total_gb_size_per_controller +=
-				((csn_bnds_backup & 0xFFFF) >> 6)
-				- (csn_bnds_backup >> 22) + 1;
-		} else {
-			total_gb_size_per_controller +=
-				((regs->cs[i].bnds & 0xFFFF) >> 6)
-				- (regs->cs[i].bnds >> 22) + 1;
-		}
-	}
-	if (in_be32(&ddr->sdram_cfg) & 0x80000)
-		total_gb_size_per_controller <<= 1;
-	debug("Wait for %d ms\n", total_gb_size_per_controller * 400);
-	udelay(total_gb_size_per_controller * 400000);
+	/* 7. Wait for state machine 2nd run, roughly 400ms/GB */
+	debug("Wait for %d * 10ms\n", timeout_save);
+	udelay(timeout_save * 10000);
 
 	/* 8. Set sdram_cfg_2[dinit] if options requires */
 	setbits_be32(&ddr->sdram_cfg_2,
@@ -354,8 +389,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 	debug("Setting sdram_cfg_2 to 0x%08x\n", in_be32(&ddr->sdram_cfg_2));
 
 	/* 9. Poll until dinit is cleared */
-	while (in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)
-		udelay(10000);
+	timeout = timeout_save;
+	debug("Need to wait up to %d * 10ms\n", timeout);
+	while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
+		(timeout >= 0)) {
+		udelay(10000);		/* throttle polling rate */
+		timeout--;
+	}
+
+	if (timeout <= 0)
+		printf("Waiting for D_INIT timeout. Memory may not work.\n");
 
 	/* 10. Clear EEBACR[3] */
 	clrbits_be32(&ecm->eebacr, 10000000);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index a0a9b4c..ab09330 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -47,8 +47,8 @@ extern void ft_srio_setup(void *blob);
 void ft_fixup_cpu(void *blob, u64 memory_limit)
 {
 	int off;
-	ulong spin_tbl_addr = get_spin_phys_addr();
-	u32 bootpg = determine_mp_bootpg();
+	phys_addr_t spin_tbl_addr = get_spin_phys_addr();
+	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 id = get_my_id();
 	const char *enable_method;
 
@@ -97,7 +97,16 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 	if ((u64)bootpg < memory_limit) {
 		off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 		if (off < 0)
-			printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
+			printf("Failed to reserve memory for bootpg: %s\n",
+				fdt_strerror(off));
+	}
+	/* Reserve spin table page */
+	if (spin_tbl_addr < memory_limit) {
+		off = fdt_add_mem_rsv(blob,
+			(spin_tbl_addr & ~0xffful), 4096);
+		if (off < 0)
+			printf("Failed to reserve memory for spin table: %s\n",
+				fdt_strerror(off));
 	}
 }
 #endif
@@ -220,12 +229,19 @@ static inline void ft_fixup_l2cache(void *blob)
 
 	/* we dont bother w/L3 since no platform of this type has one */
 }
-#elif defined(CONFIG_BACKSIDE_L2_CACHE)
+#elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
+	defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 static inline void ft_fixup_l2cache(void *blob)
 {
 	int off, l2_off, l3_off = -1;
 	u32 *ph;
+#ifdef	CONFIG_BACKSIDE_L2_CACHE
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
+#else
+	struct ccsr_cluster_l2 *l2cache =
+		(struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+	u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
+#endif
 	u32 size, line_size, num_ways, num_sets;
 	int has_l2 = 1;
 
@@ -257,7 +273,12 @@ static inline void ft_fixup_l2cache(void *blob)
 		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+			/* Only initialize every eighth thread */
+			if (reg && !((*reg) % 8))
+#else
 			if (reg)
+#endif
 				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 					 (*reg * 2) + 32 + 1);
 #endif
@@ -390,6 +411,11 @@ static void ft_fixup_dpaa_clks(void *blob)
 #endif
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	do_fixup_by_compat_u32(blob, "fsl,qman",
+			"clock-frequency", sysinfo.freqQMAN, 1);
+#endif
+
 #ifdef CONFIG_SYS_DPAA_PME
 	do_fixup_by_compat_u32(blob, "fsl,pme",
 		"clock-frequency", sysinfo.freqPME, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
new file mode 100644
index 0000000..01dcdf6
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/fsl_law.h>
+#include <asm/errno.h>
+#include "fsl_corenet2_serdes.h"
+
+static u64 serdes1_prtcl_map;
+static u64 serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+static u64 serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+static u64 serdes4_prtcl_map;
+#endif
+
+#ifdef DEBUG
+static const char *serdes_prtcl_str[] = {
+	[NONE] = "NA",
+	[PCIE1] = "PCIE1",
+	[PCIE2] = "PCIE2",
+	[PCIE3] = "PCIE3",
+	[PCIE4] = "PCIE4",
+	[SATA1] = "SATA1",
+	[SATA2] = "SATA2",
+	[SRIO1] = "SRIO1",
+	[SRIO2] = "SRIO2",
+	[SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
+	[SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
+	[SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
+	[SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
+	[SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
+	[SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
+	[SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
+	[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
+	[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
+	[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
+	[XAUI_FM1] = "XAUI_FM1",
+	[XAUI_FM2] = "XAUI_FM2",
+	[AURORA] = "DEBUG",
+	[CPRI1] = "CPRI1",
+	[CPRI2] = "CPRI2",
+	[CPRI3] = "CPRI3",
+	[CPRI4] = "CPRI4",
+	[CPRI5] = "CPRI5",
+	[CPRI6] = "CPRI6",
+	[CPRI7] = "CPRI7",
+	[CPRI8] = "CPRI8",
+	[XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
+	[XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
+	[XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
+	[XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
+	[HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
+	[HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
+	[HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
+	[HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
+	[QSGMII_FM1_A] = "QSGMII_FM1_A",
+	[QSGMII_FM1_B] = "QSGMII_FM1_B",
+	[QSGMII_FM2_A] = "QSGMII_FM2_A",
+	[QSGMII_FM2_B] = "QSGMII_FM2_B",
+	[XFI_FM1_MAC9] = "XFI_FM1_MAC9",
+	[XFI_FM1_MAC10] = "XFI_FM1_MAC10",
+	[XFI_FM2_MAC9] = "XFI_FM2_MAC9",
+	[XFI_FM2_MAC10] = "XFI_FM2_MAC10",
+	[INTERLAKEN] = "INTERLAKEN",
+};
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	u64 ret = 0;
+
+	ret |= (1ULL << device) & serdes1_prtcl_map;
+	ret |= (1ULL << device) & serdes2_prtcl_map;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+	ret |= (1ULL << device) & serdes3_prtcl_map;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+	ret |= (1ULL << device) & serdes4_prtcl_map;
+#endif
+
+	return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+	const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u32 cfg = in_be32(&gur->rcwsr[4]);
+	int i;
+
+	switch (sd) {
+	case FSL_SRDS_1:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+		break;
+	case FSL_SRDS_2:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+		break;
+#ifdef CONFIG_SYS_FSL_SRDS_3
+	case FSL_SRDS_3:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
+		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+	case FSL_SRDS_4:
+		cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
+		cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
+		break;
+#endif
+	default:
+		printf("invalid SerDes%d\n", sd);
+		break;
+	}
+	/* Is serdes enabled at all? */
+	if (unlikely(cfg == 0))
+		return -ENODEV;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(sd, cfg, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
+{
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	u64 serdes_prtcl_map = 0;
+	u32 cfg;
+	int lane;
+
+	cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
+	/* Is serdes enabled at all? */
+	if (!cfg) {
+		printf("SERDES%d is not enabled\n", sd + 1);
+		return 0;
+	}
+
+	cfg >>= sd_prctl_shift;
+	printf("Using SERDES%d Protocol: 0x%x\n", sd + 1, cfg);
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+		serdes_prtcl_map |= (1ULL << lane_prtcl);
+	}
+
+	return serdes_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+
+	serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+		FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT);
+	serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT);
+#ifdef CONFIG_SYS_FSL_SRDS_3
+	serdes3_prtcl_map = serdes_init(FSL_SRDS_3,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+		FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_4
+	serdes4_prtcl_map = serdes_init(FSL_SRDS_4,
+		CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+		FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
+		FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT);
+#endif
+
+}
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
new file mode 100644
index 0000000..2258f41
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FSL_CORENET2_SERDES_H
+#define __FSL_CORENET2_SERDES_H
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_lane_enabled(int lane);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+#endif /* __FSL_CORENET2_SERDES_H */
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 2a68060..7f466ac 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -92,10 +92,17 @@ static const struct {
 	{ 17, 163, FSL_SRDS_BANK_2 },
 	{ 18, 164, FSL_SRDS_BANK_2 },
 	{ 19, 165, FSL_SRDS_BANK_2 },
+#ifdef CONFIG_PPC_P4080
 	{ 20, 170, FSL_SRDS_BANK_3 },
 	{ 21, 171, FSL_SRDS_BANK_3 },
 	{ 22, 172, FSL_SRDS_BANK_3 },
 	{ 23, 173, FSL_SRDS_BANK_3 },
+#else
+	{ 20, 166, FSL_SRDS_BANK_3 },
+	{ 21, 167, FSL_SRDS_BANK_3 },
+	{ 22, 168, FSL_SRDS_BANK_3 },
+	{ 23, 169, FSL_SRDS_BANK_3 },
+#endif
 };
 
 int serdes_get_lane_idx(int lane)
@@ -482,7 +489,7 @@ static void wait_for_rstdone(unsigned int bank)
 }
 
 
-void __soc_serdes_init(void)
+static void __soc_serdes_init(void)
 {
 	/* Allow for SoC-specific initialization in <SOC>_serdes.c  */
 };
@@ -493,6 +500,9 @@ void fsl_serdes_init(void)
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int cfg;
 	serdes_corenet_t *srds_regs;
+#ifdef CONFIG_PPC_P5040
+	serdes_corenet_t *srds2_regs;
+#endif
 	int lane, bank, idx;
 	int have_bank[SRDS_MAX_BANK] = {};
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -574,6 +584,34 @@ void fsl_serdes_init(void)
 		}
 	}
 
+#ifdef CONFIG_PPC_P5040
+	/*
+	 * Lanes on bank 4 on P5040 are commented-out, but for some SERDES
+	 * protocols, these lanes are routed to SATA.  We use serdes_prtcl_map
+	 * to decide whether a protocol is supported on a given lane, so SATA
+	 * will be identified as not supported, and therefore not initialized.
+	 * So for protocols which use SATA on bank4, we add SATA support in
+	 * serdes_prtcl_map.
+	 */
+	switch (cfg) {
+	case 0x0:
+	case 0x1:
+	case 0x2:
+	case 0x3:
+	case 0x4:
+	case 0x5:
+	case 0x6:
+	case 0x7:
+		serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
+		break;
+	default:
+		srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+
+		/* We don't need bank 4, so power it down */
+		setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
+	}
+#endif
+
 	soc_serdes_init();
 
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -617,6 +655,38 @@ void fsl_serdes_init(void)
 		}
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004699
+	/*
+	 * To avoid the situation that resulted in the P4080 erratum
+	 * SERDES-8, a given SerDes bank will use the PLLs from the previous
+	 * bank if one of the PLL frequencies is a multiple of the other.  For
+	 * instance, if bank 3 is running at 2.5GHz and bank 2 is at 1.25GHz,
+	 * then bank 3 will use bank 2's PLL.  P5040 Erratum A-004699 says
+	 * that, in this situation, lane synchronization is not initiated.  So
+	 * when we detect a bank with a "borrowed" PLL, we have to manually
+	 * initiate lane synchronization.
+	 */
+	for (bank = FSL_SRDS_BANK_2; bank <= FSL_SRDS_BANK_3; bank++) {
+		/* Determine the first lane for this bank */
+		unsigned int lane;
+
+		for (lane = 0; lane < SRDS_MAX_LANES; lane++)
+			if (lanes[lane].bank == bank)
+				break;
+		idx = lanes[lane].idx;
+
+		/*
+		 * Check if the PLL for the bank is borrowed.  The UOTHL
+		 * bit of the first lane will tell us that.
+		 */
+		if (in_be32(&srds_regs->lane[idx].gcr0) & SRDS_GCR0_UOTHL) {
+			/* Manually start lane synchronization */
+			setbits_be32(&srds_regs->bank[bank].pllcr0,
+				     SRDS_PLLCR0_PVCOCNT_EN);
+		}
+	}
+#endif
+
 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) || defined (CONFIG_SYS_P4080_ERRATUM_SERDES9)
 	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
 		enum srds_prtcl lane_prtcl;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
index f261351..3c551e9 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h
@@ -22,9 +22,6 @@
 #ifndef __FSL_CORENET_SERDES_H
 #define __FSL_CORENET_SERDES_H
 
-#define SRDS_MAX_LANES		18
-#define SRDS_MAX_BANK		3
-
 enum srds_bank {
 	FSL_SRDS_BANK_1  = 0,
 	FSL_SRDS_BANK_2  = 1,
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 11881c9..2e53367 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -40,6 +40,7 @@ int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset)
 	return liodn_bases[dpaa_dev].num_ids;
 }
 
+#ifdef CONFIG_SYS_SRIO
 static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
 {
 	int i;
@@ -54,6 +55,7 @@ static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size)
 		}
 	}
 }
+#endif
 
 static void set_liodn(struct liodn_id_table *tbl, int size)
 {
@@ -181,8 +183,10 @@ void set_liodns(void)
 	/* setup general liodn offsets */
 	set_liodn(liodn_tbl, liodn_tbl_sz);
 
+#ifdef CONFIG_SYS_SRIO
 	/* setup SRIO port liodns */
 	set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz);
+#endif
 
 	/* setup SEC block liodn bases & offsets if we have one */
 	if (IS_E_PROCESSOR(get_svr())) {
@@ -219,6 +223,7 @@ void set_liodns(void)
 #endif
 }
 
+#ifdef CONFIG_SYS_SRIO
 static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 {
 	int i, srio_off;
@@ -247,6 +252,57 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
 		}
 	}
 }
+#endif
+
+#define CONFIG_SYS_MAX_PCI_EPS		8
+#define CONFIG_SYS_PCI_EP_LIODN_START	256
+
+static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
+{
+	int off, pci_idx = 0, pci_cnt = 0, i, rc;
+	const uint32_t *base_liodn;
+	uint32_t liodn_offs[CONFIG_SYS_MAX_PCI_EPS + 1] = { 0 };
+
+	/*
+	 * Count the number of pci nodes.
+	 * It's needed later when the interleaved liodn offsets are generated.
+	 */
+	off = fdt_node_offset_by_compatible(fdt, -1, compat);
+	while (off != -FDT_ERR_NOTFOUND) {
+		pci_cnt++;
+		off = fdt_node_offset_by_compatible(fdt, off, compat);
+	}
+
+	for (off = fdt_node_offset_by_compatible(fdt, -1, compat);
+	     off != -FDT_ERR_NOTFOUND;
+	     off = fdt_node_offset_by_compatible(fdt, off, compat)) {
+		base_liodn = fdt_getprop(fdt, off, "fsl,liodn", &rc);
+		if (!base_liodn) {
+			char path[64];
+
+			if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+				strcpy(path, "(unknown)");
+			printf("WARNING Could not get liodn of node %s: %s\n",
+			       path, fdt_strerror(rc));
+			continue;
+		}
+		for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
+			liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
+					i * pci_cnt + pci_idx - *base_liodn;
+		rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
+				 liodn_offs, sizeof(liodn_offs));
+		if (rc) {
+			char path[64];
+
+			if (fdt_get_path(fdt, off, path, sizeof(path)) < 0)
+				strcpy(path, "(unknown)");
+			printf("WARNING Unable to set fsl,liodn-offset-list for "
+			       "node %s: %s\n", path, fdt_strerror(rc));
+			continue;
+		}
+		pci_idx++;
+	}
+}
 
 static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
 {
@@ -277,7 +333,9 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz)
 
 void fdt_fixup_liodn(void *blob)
 {
+#ifdef CONFIG_SYS_SRIO
 	fdt_fixup_srio_liodn(blob, srio_liodn_tbl);
+#endif
 
 	fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz);
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -295,4 +353,6 @@ void fdt_fixup_liodn(void *blob)
 #ifdef CONFIG_SYS_DPAA_RMAN
 	fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
 #endif
+
+	fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
 }
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index ffc2a9a..e1197ac 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -27,9 +27,13 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
+u32 fsl_ddr_get_intl3r(void);
+
+extern u32 __spin_table[];
 
 u32 get_my_id()
 {
@@ -76,17 +80,16 @@ int cpu_status(int nr)
 		return 0;
 
 	if (nr == id) {
-		table = (u32 *)get_spin_virt_addr();
+		table = (u32 *)&__spin_table;
 		printf("table base @ 0x%p\n", table);
 	} else {
-		table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+		table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
 		printf("Running on cpu %d\n", id);
 		printf("\n");
 		printf("table @ 0x%p\n", table);
 		printf("   addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
-		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
 		printf("   r3   - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
-		printf("   r6   - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
+		printf("   pir  - 0x%08x\n", table[BOOT_ENTRY_PIR]);
 	}
 
 	return 0;
@@ -149,12 +152,11 @@ static u8 boot_entry_map[4] = {
 	0,
 	BOOT_ENTRY_PIR,
 	BOOT_ENTRY_R3_LOWER,
-	BOOT_ENTRY_R6_LOWER,
 };
 
 int cpu_release(int nr, int argc, char * const argv[])
 {
-	u32 i, val, *table = (u32 *)get_spin_virt_addr() + nr * NUM_BOOT_ENTRY;
+	u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
 	u64 boot_addr;
 
 	if (hold_cores_in_reset(1))
@@ -172,8 +174,8 @@ int cpu_release(int nr, int argc, char * const argv[])
 
 	boot_addr = simple_strtoull(argv[0], NULL, 16);
 
-	/* handle pir, r3, r6 */
-	for (i = 1; i < 4; i++) {
+	/* handle pir, r3 */
+	for (i = 1; i < 3; i++) {
 		if (argv[i][0] != '-') {
 			u8 entry = boot_entry_map[i];
 			val = simple_strtoul(argv[i], NULL, 16);
@@ -191,38 +193,80 @@ int cpu_release(int nr, int argc, char * const argv[])
 	return 0;
 }
 
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
 {
-	/* if we have 4G or more of memory, put the boot page at 4Gb-4k */
-	if ((u64)gd->ram_size > 0xfffff000)
-		return (0xfffff000);
+	u32 bootpg;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+	u32 svr = get_svr();
+	u32 granule_size, check;
+	struct law_entry e;
+#endif
 
-	return (gd->ram_size - 4096);
-}
 
-ulong get_spin_phys_addr(void)
-{
-	extern ulong __secondary_start_page;
-	extern ulong __spin_table;
+	/* use last 4K of mapped memory */
+	bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
+		CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
+		CONFIG_SYS_SDRAM_BASE - 4096;
+	if (pagesize)
+		*pagesize = 4096;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
+/*
+ * Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
+ * to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
+ * the way boot page chosen in u-boot avoids hitting this erratum. So only
+ * thw workaround for 3-way interleaving is needed.
+ *
+ * To make sure boot page translation works with 3-Way DDR interleaving
+ * enforce a check for the following constrains
+ * 8K granule size requires BRSIZE=8K and
+ *    bootpg >> log2(BRSIZE) %3 == 1
+ * 4K and 1K granule size requires BRSIZE=4K and
+ *    bootpg >> log2(BRSIZE) %3 == 0
+ */
+	if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
+		e = find_law(bootpg);
+		switch (e.trgt_id) {
+		case LAW_TRGT_IF_DDR_INTLV_123:
+			granule_size = fsl_ddr_get_intl3r() & 0x1f;
+			if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
+				if (pagesize)
+					*pagesize = 8192;
+				bootpg &= 0xffffe000;	/* align to 8KB */
+				check = bootpg >> 13;
+				while ((check % 3) != 1)
+					check--;
+				bootpg = check << 13;
+				debug("Boot page (8K) at 0x%08x\n", bootpg);
+				break;
+			} else {
+				bootpg &= 0xfffff000;	/* align to 4KB */
+				check = bootpg >> 12;
+				while ((check % 3) != 0)
+					check--;
+				bootpg = check << 12;
+				debug("Boot page (4K) at 0x%08x\n", bootpg);
+			}
+				break;
+		default:
+			break;
+		}
+	}
+#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
 
-	return (determine_mp_bootpg() +
-		(ulong)&__spin_table - (ulong)&__secondary_start_page);
+	return bootpg;
 }
 
-ulong get_spin_virt_addr(void)
+phys_addr_t get_spin_phys_addr(void)
 {
-	extern ulong __secondary_start_page;
-	extern ulong __spin_table;
-
-	return (CONFIG_BPTR_VIRT_ADDR +
-		(ulong)&__spin_table - (ulong)&__secondary_start_page);
+	return virt_to_phys(&__spin_table);
 }
 
 #ifdef CONFIG_FSL_CORENET
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 {
-	u32 cpu_up_mask, whoami;
-	u32 *table = (u32 *)get_spin_virt_addr();
+	u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
+	u32 *table = (u32 *)&__spin_table;
 	volatile ccsr_gur_t *gur;
 	volatile ccsr_local_t *ccm;
 	volatile ccsr_rcpm_t *rcpm;
@@ -241,7 +285,11 @@ static void plat_mp_up(unsigned long bootpg)
 	out_be32(&ccm->bstrl, bootpg);
 
 	e = find_law(bootpg);
-	out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
+	/* pagesize is only 4K or 8K */
+	if (pagesize == 8192)
+		brsize = LAW_SIZE_8K;
+	out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
+	debug("BRSIZE is 0x%x\n", brsize);
 
 	/* readback to sync write */
 	in_be32(&ccm->bstrar);
@@ -294,10 +342,10 @@ static void plat_mp_up(unsigned long bootpg)
 #endif
 }
 #else
-static void plat_mp_up(unsigned long bootpg)
+static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
 {
 	u32 up, cpu_up_mask, whoami;
-	u32 *table = (u32 *)get_spin_virt_addr();
+	u32 *table = (u32 *)&__spin_table;
 	volatile u32 bpcr;
 	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -374,27 +422,52 @@ static void plat_mp_up(unsigned long bootpg)
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 
 	lmb_reserve(lmb, bootpg, 4096);
 }
 
 void setup_mp(void)
 {
-	extern ulong __secondary_start_page;
-	extern ulong __bootpg_addr;
-	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg = determine_mp_bootpg();
+	extern u32 __secondary_start_page;
+	extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
+
+	int i;
+	ulong fixup = (u32)&__secondary_start_page;
+	u32 bootpg, bootpg_map, pagesize;
+
+	bootpg = determine_mp_bootpg(&pagesize);
+
+	/*
+	 * pagesize is only 4K or 8K
+	 * we only use the last 4K of boot page
+	 * bootpg_map saves the address for the boot page
+	 * 8K is used for the workaround of 3-way DDR interleaving
+	 */
+
+	bootpg_map = bootpg;
+
+	if (pagesize == 8192)
+		bootpg += 4096;	/* use 2nd half */
 
 	/* Some OSes expect secondary cores to be held in reset */
 	if (hold_cores_in_reset(0))
 		return;
 
-	/* Store the bootpg's SDRAM address for use by secondary CPU cores */
-	__bootpg_addr = bootpg;
+	/*
+	 * Store the bootpg's cache-able half address for use by secondary
+	 * CPU cores to continue to boot
+	 */
+	__bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
+
+	/* Store spin table's physical address for use by secondary cores */
+	__spin_table_addr = (u32)get_spin_phys_addr();
+
+	/* flush bootpg it before copying invalidate any staled cacheline */
+	flush_cache(bootpg, 4096);
 
 	/* look for the tlb covering the reset page, there better be one */
-	int i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
+	i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
 
 	/* we found a match */
 	if (i != -1) {
@@ -407,7 +480,7 @@ void setup_mp(void)
 
 		memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
 
-		plat_mp_up(bootpg);
+		plat_mp_up(bootpg_map, pagesize);
 	} else {
 		puts("WARNING: No reset page TLB. "
 			"Skipping secondary core setup\n");
diff --git a/arch/powerpc/cpu/mpc85xx/mp.h b/arch/powerpc/cpu/mpc85xx/mp.h
index 87bac37..ad9950b 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.h
+++ b/arch/powerpc/cpu/mpc85xx/mp.h
@@ -3,8 +3,7 @@
 
 #include <asm/mp.h>
 
-ulong get_spin_phys_addr(void);
-ulong get_spin_virt_addr(void);
+phys_addr_t get_spin_phys_addr(void);
 u32 get_my_id(void);
 int hold_cores_in_reset(int verbose);
 
@@ -16,7 +15,7 @@ int hold_cores_in_reset(int verbose);
 #define BOOT_ENTRY_PIR		5
 #define BOOT_ENTRY_R6_UPPER	6
 #define BOOT_ENTRY_R6_LOWER	7
-#define NUM_BOOT_ENTRY		8
+#define NUM_BOOT_ENTRY		16	/* pad to 64 bytes */
 #define SIZE_BOOT_ENTRY		(NUM_BOOT_ENTRY * sizeof(u32))
 
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
new file mode 100644
index 0000000..878ee3e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 2, 1, 0),
+	SET_QP_INFO(3, 4, 2, 1),
+	SET_QP_INFO(5, 6, 3, 2),
+	SET_QP_INFO(7, 8, 4, 3),
+	SET_QP_INFO(9, 10, 5, 0),
+	SET_QP_INFO(11, 12, 6, 1),
+	SET_QP_INFO(13, 14, 7, 2),
+	SET_QP_INFO(15, 16, 8, 3),
+	SET_QP_INFO(17, 18, 9, 0),	/* for now, set sdest to 0 */
+	SET_QP_INFO(19, 20, 10, 0),	/* for now, set sdest to 0 */
+};
+#endif
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(31),
+	SET_BMAN_LIODN(32),
+#endif
+
+	SET_SDHC_LIODN(1, 64),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 93),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 94),
+
+	SET_SATA_LIODN(1, 95),
+	SET_SATA_LIODN(2, 96),
+
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 195),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
+	SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
+
+	SET_DMA_LIODN(1, 193),
+	SET_DMA_LIODN(2, 194),
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 6),
+	SET_FMAN_RX_1G_LIODN(1, 1, 7),
+	SET_FMAN_RX_1G_LIODN(1, 2, 8),
+	SET_FMAN_RX_1G_LIODN(1, 3, 9),
+	SET_FMAN_RX_1G_LIODN(1, 4, 10),
+	SET_FMAN_RX_10G_LIODN(1, 0, 11),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(2, 0, 12),
+	SET_FMAN_RX_1G_LIODN(2, 1, 13),
+	SET_FMAN_RX_1G_LIODN(2, 2, 14),
+	SET_FMAN_RX_1G_LIODN(2, 3, 15),
+	SET_FMAN_RX_1G_LIODN(2, 4, 16),
+	SET_FMAN_RX_10G_LIODN(2, 0, 17),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 129, 130),
+	SET_SEC_JR_LIODN_ENTRY(1, 131, 132),
+	SET_SEC_JR_LIODN_ENTRY(2, 133, 134),
+	SET_SEC_JR_LIODN_ENTRY(3, 135, 136),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 89),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 90),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 91),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 92),
+	SET_SEC_DECO_LIODN_ENTRY(0, 139, 140),
+	SET_SEC_DECO_LIODN_ENTRY(1, 141, 142),
+	SET_SEC_DECO_LIODN_ENTRY(2, 143, 144),
+	SET_SEC_DECO_LIODN_ENTRY(3, 145, 146),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+struct liodn_id_table raide_liodn_tbl[] = {
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 0, 60),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(0, 1, 61),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 0, 62),
+	SET_RAID_ENGINE_JQ_LIODN_ENTRY(1, 1, 63),
+};
+int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(64, 101),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(32),
+#endif
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(160),
+#endif
+#ifdef CONFIG_SYS_FSL_RAID_ENGINE
+	[FSL_HW_PORTAL_RAID_ENGINE]  = SET_LIODN_BASE_1(49),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/p5040_serdes.c b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
new file mode 100644
index 0000000..890b88e
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/p5040_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2009-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet_serdes.h"
+
+/*
+ * Note: For P5040, the fourth SerDes bank (with two lanes) is on SerDes2, but
+ * U-boot only supports one SerDes controller.  Therefore, we ignore bank 4 in
+ * this table.  This works because most of the SerDes code is for errata
+ * work-arounds, and there are no P5040 errata that effect bank 4.
+ */
+
+static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
+	[0x00] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2, */ },
+	[0x01] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x02] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x03] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SGMII_FM2_DTSEC1,
+		SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		/* SATA1, SATA2 */ },
+	[0x04] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM2_DTSEC1,
+		SGMII_FM2_DTSEC2, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		/* SATA1, SATA2 */ },
+	[0x05] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE3, SGMII_FM1_DTSEC3,
+		SGMII_FM1_DTSEC4, SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x06] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+		XAUI_FM2, XAUI_FM2, XAUI_FM2, XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x07] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
+		SGMII_FM1_DTSEC3, SGMII_FM2_DTSEC4, XAUI_FM1, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, XAUI_FM2, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, /* SATA1, SATA2 */ },
+	[0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2,
+		/* NONE, NONE */ },
+	[0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
+		NONE, NONE, SATA1, SATA2, /* NONE, NONE */ },
+	[0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
+		AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM2, XAUI_FM2,
+		XAUI_FM2, XAUI_FM2, /* NONE, NONE */ },
+	[0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+		AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+		NONE, SATA1, SATA2, /* NONE, NONE */ },
+	[0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
+		XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2,
+		/* NONE, NONE */ },
+	[0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
+		SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
+		AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
+		NONE, SATA1, SATA2, /* NONE, NONE */ },
+};
+
+enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
+{
+	if (!serdes_lane_enabled(lane))
+		return NONE;
+
+	return serdes_cfg_tbl[cfg][lane];
+}
+
+int is_serdes_prtcl_valid(u32 prtcl)
+{
+	int i;
+
+	if (prtcl > ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_cfg_tbl[prtcl][i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c
index 6199633..b59ef69 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -182,14 +182,18 @@ void fdt_fixup_qportals(void *blob)
 {
 	int off, err;
 	unsigned int maj, min;
+	unsigned int ip_cfg;
 	u32 rev_1 = in_be32(&qman->ip_rev_1);
+	u32 rev_2 = in_be32(&qman->ip_rev_2);
 	char compat[64];
 	int compat_len;
 
 	maj = (rev_1 >> 8) & 0xff;
 	min = rev_1 & 0xff;
+	ip_cfg = rev_2 & 0xff;
 
-	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u", maj, min) + 1;
+	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
+					maj, min, ip_cfg) + 1;
 	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
@@ -267,14 +271,19 @@ void fdt_fixup_bportals(void *blob)
 {
 	int off, err;
 	unsigned int maj, min;
+	unsigned int ip_cfg;
 	u32 rev_1 = in_be32(&bman->ip_rev_1);
+	u32 rev_2 = in_be32(&bman->ip_rev_2);
 	char compat[64];
 	int compat_len;
 
 	maj = (rev_1 >> 8) & 0xff;
 	min = rev_1 & 0xff;
 
-	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u", maj, min) + 1;
+	ip_cfg = rev_2 & 0xff;
+
+	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
+				 maj, min, ip_cfg) + 1;
 	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 22e73e0..4ba44a9 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -150,29 +150,33 @@ __secondary_start_page:
 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
 
 	/* get our PIR to figure out our table entry */
-	lis	r3,toreset(__spin_table)@h
-	ori	r3,r3,toreset(__spin_table)@l
+	lis	r3,toreset(__spin_table_addr)@h
+	ori	r3,r3,toreset(__spin_table_addr)@l
+	lwz	r3,0(r3)
 
-	/* r10 has the base address for the entry */
+	/*
+	 * r10 has the base address for the entry.
+	 * we cannot access it yet before setting up a new TLB
+	 */
 	mfspr	r0,SPRN_PIR
 #if	defined(CONFIG_E6500)
 /*
  * PIR definition for E6500
  * 0-17 Reserved (logic 0s)
- * 8-19 CHIP_ID,    2’b00      - SoC 1
+ * 8-19 CHIP_ID,    2'b00      - SoC 1
  *                  all others - reserved
- * 20-24 CLUSTER_ID 5’b00000   - CCM 1
+ * 20-24 CLUSTER_ID 5'b00000   - CCM 1
  *                  all others - reserved
- * 25-26 CORE_CLUSTER_ID 2’b00 - cluster 1
- *                       2’b01 - cluster 2
- *                       2’b10 - cluster 3
- *                       2’b11 - cluster 4
- * 27-28 CORE_ID         2’b00 - core 0
- *                       2’b01 - core 1
- *                       2’b10 - core 2
- *                       2’b11 - core 3
- * 29-31 THREAD_ID       3’b000 - thread 0
- *                       3’b001 - thread 1
+ * 25-26 CORE_CLUSTER_ID 2'b00 - cluster 1
+ *                       2'b01 - cluster 2
+ *                       2'b10 - cluster 3
+ *                       2'b11 - cluster 4
+ * 27-28 CORE_ID         2'b00 - core 0
+ *                       2'b01 - core 1
+ *                       2'b10 - core 2
+ *                       2'b11 - core 3
+ * 29-31 THREAD_ID       3'b000 - thread 0
+ *                       3'b001 - thread 1
  */
 	rlwinm  r4,r0,29,25,31
 #elif	defined(CONFIG_E500MC)
@@ -180,16 +184,9 @@ __secondary_start_page:
 #else
 	mr	r4,r0
 #endif
-	slwi	r8,r4,5
+	slwi	r8,r4,6	/* spin table is padded to 64 byte */
 	add	r10,r3,r8
 
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
-	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
-	slwi	r8,r4,1
-	addi	r8,r8,32
-	mtspr	L1CSR2,r8
-#endif
-
 #ifdef CONFIG_E6500
 	mfspr	r0,SPRN_PIR
 	/*
@@ -209,6 +206,13 @@ __secondary_start_page:
 
 	mtspr	SPRN_PIR,r4	/* write to PIR register */
 
+#ifdef CONFIG_SYS_CACHE_STASHING
+	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
+	slwi	r8,r4,1
+	addi	r8,r8,32
+	mtspr	L1CSR2,r8
+#endif
+
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 	/*
@@ -277,73 +281,111 @@ __secondary_start_page:
 	beq	2b
 #endif
 3:
-
-#define EPAPR_MAGIC		(0x45504150)
-#define ENTRY_ADDR_UPPER	0
-#define ENTRY_ADDR_LOWER	4
-#define ENTRY_R3_UPPER		8
-#define ENTRY_R3_LOWER		12
-#define ENTRY_RESV		16
-#define ENTRY_PIR		20
-#define ENTRY_R6_UPPER		24
-#define ENTRY_R6_LOWER		28
-#define ENTRY_SIZE		32
-
-	/* setup the entry */
-	li	r3,0
-	li	r8,1
-	stw	r4,ENTRY_PIR(r10)
-	stw	r3,ENTRY_ADDR_UPPER(r10)
-	stw	r8,ENTRY_ADDR_LOWER(r10)
-	stw	r3,ENTRY_R3_UPPER(r10)
-	stw	r4,ENTRY_R3_LOWER(r10)
-	stw	r3,ENTRY_R6_UPPER(r10)
-	stw	r3,ENTRY_R6_LOWER(r10)
-
-	/* load r13 with the address of the 'bootpg' in SDRAM */
-	lis	r13,toreset(__bootpg_addr)@h
-	ori	r13,r13,toreset(__bootpg_addr)@l
+	/* setup mapping for the spin table, WIMGE=0b00100 */
+	lis	r13,toreset(__spin_table_addr)@h
+	ori	r13,r13,toreset(__spin_table_addr)@l
 	lwz	r13,0(r13)
+	/* mask by 4K */
+	rlwinm	r13,r13,0,0,19
 
-	/* setup mapping for AS = 1, and jump there */
 	lis	r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
 	mtspr	SPRN_MAS0,r11
 	lis	r11,(MAS1_VALID|MAS1_IPROT)@h
 	ori	r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
 	mtspr	SPRN_MAS1,r11
-	oris	r11,r13,(MAS2_I|MAS2_G)@h
-	ori	r11,r13,(MAS2_I|MAS2_G)@l
+	oris	r11,r13,(MAS2_M|MAS2_G)@h
+	ori	r11,r13,(MAS2_M|MAS2_G)@l
 	mtspr	SPRN_MAS2,r11
 	oris	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
 	ori	r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
 	mtspr	SPRN_MAS3,r11
+	li	r11,0
+	mtspr	SPRN_MAS7,r11
 	tlbwe
 
-	bl	1f
-1:	mflr	r11
 	/*
-	 * OR in 0xfff to create a mask of the bootpg SDRAM address.  We use
-	 * this mask to fixup the cpu spin table and the address that we want
-	 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
-	 * bootpg is at 0x7ffff000 in SDRAM.
+	 * __bootpg_addr has the address of __second_half_boot_page
+	 * jump there in AS=1 space with cache enabled
 	 */
-	ori	r13,r13,0xfff
-	and	r11, r11, r13
-	and	r10, r10, r13
-
-	addi	r11,r11,(2f-1b)
+	lis	r13,toreset(__bootpg_addr)@h
+	ori	r13,r13,toreset(__bootpg_addr)@l
+	lwz	r11,0(r13)
+	mtspr	SPRN_SRR0,r11
 	mfmsr	r13
 	ori	r12,r13,MSR_IS|MSR_DS@l
-
-	mtspr	SPRN_SRR0,r11
 	mtspr	SPRN_SRR1,r12
 	rfi
 
+	/*
+	 * Allocate some space for the SDRAM address of the bootpg.
+	 * This variable has to be in the boot page so that it can
+	 * be accessed by secondary cores when they come out of reset.
+	 */
+	.align L1_CACHE_SHIFT
+	.globl __bootpg_addr
+__bootpg_addr:
+	.long	0
+
+	.global __spin_table_addr
+__spin_table_addr:
+	.long	0
+
+	/*
+	 * This variable is set by cpu_init_r() after parsing hwconfig
+	 * to enable workaround for erratum NMG_CPU_A011.
+	 */
+	.align L1_CACHE_SHIFT
+	.global enable_cpu_a011_workaround
+enable_cpu_a011_workaround:
+	.long	1
+
+	/* Fill in the empty space.  The actual reset vector is
+	 * the last word of the page */
+__secondary_start_code_end:
+	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
+__secondary_reset_vector:
+	b	__secondary_start_page
+
+
+/* this is a separated page for the spin table and cacheable boot code */
+	.align L1_CACHE_SHIFT
+	.global __second_half_boot_page
+__second_half_boot_page:
+#define EPAPR_MAGIC		0x45504150
+#define ENTRY_ADDR_UPPER	0
+#define ENTRY_ADDR_LOWER	4
+#define ENTRY_R3_UPPER		8
+#define ENTRY_R3_LOWER		12
+#define ENTRY_RESV		16
+#define ENTRY_PIR		20
+#define ENTRY_SIZE		64
+	/*
+	 * setup the entry
+	 * r10 has the base address of the spin table.
+	 * spin table is defined as
+	 * struct {
+	 *	uint64_t entry_addr;
+	 *	uint64_t r3;
+	 *	uint32_t rsvd1;
+	 *	uint32_t pir;
+	 * };
+	 * we pad this struct to 64 bytes so each entry is in its own cacheline
+	 */
+	li	r3,0
+	li	r8,1
+	mfspr	r4,SPRN_PIR
+	stw	r3,ENTRY_ADDR_UPPER(r10)
+	stw	r3,ENTRY_R3_UPPER(r10)
+	stw	r4,ENTRY_R3_LOWER(r10)
+	stw	r3,ENTRY_RESV(r10)
+	stw	r4,ENTRY_PIR(r10)
+	msync
+	stw	r8,ENTRY_ADDR_LOWER(r10)
+
 	/* spin waiting for addr */
-2:
-	lwz	r4,ENTRY_ADDR_LOWER(r10)
+3:	lwz	r4,ENTRY_ADDR_LOWER(r10)
 	andi.	r11,r4,1
-	bne	2b
+	bne	3b
 	isync
 
 	/* setup IVORs to match fixed offsets */
@@ -362,11 +404,20 @@ __secondary_start_page:
 	/* mask by ~64M to setup our tlb we will jump to */
 	rlwinm	r12,r4,0,0,5
 
-	/* setup r3, r4, r5, r6, r7, r8, r9 */
+	/*
+	 * setup r3, r4, r5, r6, r7, r8, r9
+	 * r3 contains the value to put in the r3 register at secondary cpu
+	 * entry. The high 32-bits are ignored on 32-bit chip implementations.
+	 * 64-bit chip implementations however shall load all 64-bits
+	 */
+#ifdef CONFIG_SYS_PPC64
+	ld	r3,ENTRY_R3_UPPER(r10)
+#else
 	lwz	r3,ENTRY_R3_LOWER(r10)
+#endif
 	li	r4,0
 	li	r5,0
-	lwz	r6,ENTRY_R6_LOWER(r10)
+	li	r6,0
 	lis	r7,(64*1024*1024)@h
 	li	r8,0
 	li	r9,0
@@ -404,32 +455,10 @@ __secondary_start_page:
 	mtspr	SPRN_SRR1,r13
 	rfi
 
-	/*
-	 * Allocate some space for the SDRAM address of the bootpg.
-	 * This variable has to be in the boot page so that it can
-	 * be accessed by secondary cores when they come out of reset.
-	 */
-	.globl __bootpg_addr
-__bootpg_addr:
-	.long	0
 
-	.align L1_CACHE_SHIFT
+	.align 6
 	.globl __spin_table
 __spin_table:
 	.space CONFIG_MAX_CPUS*ENTRY_SIZE
-
-	/*
-	 * This variable is set by cpu_init_r() after parsing hwconfig
-	 * to enable workaround for erratum NMG_CPU_A011.
-	 */
-	.align L1_CACHE_SHIFT
-	.global enable_cpu_a011_workaround
-enable_cpu_a011_workaround:
-	.long	1
-
-	/* Fill in the empty space.  The actual reset vector is
-	 * the last word of the page */
-__secondary_start_code_end:
-	.space 4092 - (__secondary_start_code_end - __secondary_start_page)
-__secondary_reset_vector:
-	b	__secondary_start_page
+__spin_table_end:
+	.space 4096 - (__spin_table_end - __spin_table)
diff --git a/arch/powerpc/cpu/mpc85xx/serial_scc.c b/arch/powerpc/cpu/mpc85xx/serial_scc.c
index fe9af55..6345362 100644
--- a/arch/powerpc/cpu/mpc85xx/serial_scc.c
+++ b/arch/powerpc/cpu/mpc85xx/serial_scc.c
@@ -220,13 +220,6 @@ static void mpc85xx_serial_putc(const char c)
 	tbdf->cbd_sc |= BD_SC_READY;
 }
 
-static void mpc85xx_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
-
 static int mpc85xx_serial_getc(void)
 {
 	volatile cbd_t		*rbdf;
@@ -268,7 +261,7 @@ static struct serial_device mpc85xx_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= mpc85xx_serial_setbrg,
 	.putc	= mpc85xx_serial_putc,
-	.puts	= mpc85xx_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= mpc85xx_serial_getc,
 	.tstc	= mpc85xx_serial_tstc,
 };
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index abfeb26..801ee07 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -39,6 +39,10 @@ DECLARE_GLOBAL_DATA_PTR;
 void get_sys_info (sys_info_t * sysInfo)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#ifdef CONFIG_FSL_IFC
+	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	u32 ccr;
+#endif
 #ifdef CONFIG_FSL_CORENET
 	volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
 	unsigned int cpu;
@@ -72,16 +76,22 @@ void get_sys_info (sys_info_t * sysInfo)
 		[13] = 2,	/* CC4 PPL / 2 */
 		[14] = 4,	/* CC4 PPL / 4 */
 	};
-	uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
-	uint ratio[4];
+	uint i, freqCC_PLL[6], rcw_tmp;
+	uint ratio[6];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	uint mem_pll_rat;
 
 	sysInfo->freqSystemBus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+#else
 	sysInfo->freqDDRBus = sysclk;
+#endif
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
-	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
+	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+			FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
+			& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	if (mem_pll_rat > 2)
 		sysInfo->freqDDRBus *= mem_pll_rat;
 	else
@@ -91,27 +101,151 @@ void get_sys_info (sys_info_t * sysInfo)
 	ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
 	ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
 	ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
-	for (i = 0; i < 4; i++) {
+	ratio[4] = (in_be32(&clk->pllc5gsr) >> 1) & 0x3f;
+	ratio[5] = (in_be32(&clk->pllc6gsr) >> 1) & 0x3f;
+	for (i = 0; i < 6; i++) {
 		if (ratio[i] > 4)
 			freqCC_PLL[i] = sysclk * ratio[i];
 		else
 			freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
 	}
-	rcw_tmp = in_be32(&gur->rcwsr[3]);
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	/*
+	 * Each cluster has up to 4 cores, sharing the same PLL selection.
+	 * The cluster assignment is fixed per SoC. There is no way identify the
+	 * assignment so far, presuming the "first configuration" which is to
+	 * fill the lower cluster group first before moving up to next group.
+	 * PLL1, PLL2, PLL3 are cluster group A, feeding core 0~3 on cluster 1
+	 * and core 4~7 on cluster 2
+	 * PLL4, PLL5, PLL6 are cluster group B, feeding core 8~11 on cluster 3
+	 * and core 12~15 on cluster 4 if existing
+	 */
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
-		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + (cpu / 4) * 8) >> 27)
+				& 0xf;
 		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+		if (cplx_pll > 3)
+			printf("Unsupported architecture configuration"
+				" in function %s\n", __func__);
+		cplx_pll += (cpu / 8) * 3;
 
 		sysInfo->freqProcessor[cpu] =
 			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
 	}
+#define PME_CLK_SEL	0xe0000000
+#define PME_CLK_SHIFT	29
+#define FM1_CLK_SEL	0x1c000000
+#define FM1_CLK_SHIFT	26
+	rcw_tmp = in_be32(&gur->rcwsr[7]);
+
+#ifdef CONFIG_SYS_DPAA_PME
+	switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqPME = freqCC_PLL[0];
+		break;
+	case 2:
+		sysInfo->freqPME = freqCC_PLL[0] / 2;
+		break;
+	case 3:
+		sysInfo->freqPME = freqCC_PLL[0] / 3;
+		break;
+	case 4:
+		sysInfo->freqPME = freqCC_PLL[0] / 4;
+		break;
+	case 6:
+		sysInfo->freqPME = freqCC_PLL[1] / 2;
+		break;
+	case 7:
+		sysInfo->freqPME = freqCC_PLL[1] / 3;
+		break;
+	default:
+		printf("Error: Unknown PME clock select!\n");
+	case 0:
+		sysInfo->freqPME = sysInfo->freqSystemBus / 2;
+		break;
 
+	}
+#endif
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqFMan[0] = freqCC_PLL[3];
+		break;
+	case 2:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 2;
+		break;
+	case 3:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 3;
+		break;
+	case 4:
+		sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
+		break;
+	case 6:
+		sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
+		break;
+	case 7:
+		sysInfo->freqFMan[0] = freqCC_PLL[4] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan1 clock select!\n");
+	case 0:
+		sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
+		break;
+	}
+#if (CONFIG_SYS_NUM_FMAN) == 2
+#define FM2_CLK_SEL	0x00000038
+#define FM2_CLK_SHIFT	3
+	rcw_tmp = in_be32(&gur->rcwsr[15]);
+	switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
+	case 1:
+		sysInfo->freqFMan[1] = freqCC_PLL[4];
+		break;
+	case 2:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 2;
+		break;
+	case 3:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 3;
+		break;
+	case 4:
+		sysInfo->freqFMan[1] = freqCC_PLL[4] / 4;
+		break;
+	case 6:
+		sysInfo->freqFMan[1] = freqCC_PLL[3] / 2;
+		break;
+	case 7:
+		sysInfo->freqFMan[1] = freqCC_PLL[3] / 3;
+		break;
+	default:
+		printf("Error: Unknown FMan2 clock select!\n");
+	case 0:
+		sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
+		break;
+	}
+#endif	/* CONFIG_SYS_NUM_FMAN == 2 */
+#endif	/* CONFIG_SYS_DPAA_FMAN */
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
+		u32 c_pll_sel = (in_be32(&clk->clkc0csr + cpu*8) >> 27) & 0xf;
+		u32 cplx_pll = core_cplx_PLL[c_pll_sel];
+
+		sysInfo->freqProcessor[cpu] =
+			 freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
+	}
 #define PME_CLK_SEL	0x80000000
 #define FM1_CLK_SEL	0x40000000
 #define FM2_CLK_SEL	0x20000000
 #define HWA_ASYNC_DIV	0x04000000
 #if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
 #define HWA_CC_PLL	1
+#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
+#define HWA_CC_PLL	2
 #elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
 #define HWA_CC_PLL	2
 #else
@@ -151,11 +285,10 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 #endif
 
-#else
-	uint plat_ratio,e500_ratio,half_freqSystemBus;
-#if defined(CONFIG_FSL_LBC)
-	uint lcrr_div;
-#endif
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#else /* CONFIG_FSL_CORENET */
+	uint plat_ratio, e500_ratio, half_freqSystemBus;
 	int i;
 #ifdef CONFIG_QE
 	__maybe_unused u32 qe_ratio;
@@ -202,6 +335,7 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif /* CONFIG_FSL_CORENET */
 
 #if defined(CONFIG_FSL_LBC)
+	uint lcrr_div;
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -228,6 +362,13 @@ void get_sys_info (sys_info_t * sysInfo)
 		sysInfo->freqLocalBus = lcrr_div;
 	}
 #endif
+
+#if defined(CONFIG_FSL_IFC)
+	ccr = in_be32(&ifc_regs->ifc_ccr);
+	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
+
+	sysInfo->freqLocalBus = sysInfo->freqSystemBus / ccr;
+#endif
 }
 
 
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 9e04257..ac17f9d 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -169,7 +169,7 @@ l2_disabled:
 	 *
 	 */
 
-#if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
+#ifdef CONFIG_SYS_CACHE_STASHING
 	/* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
 	li	r2,(32 + 0)
 	mtspr	L1CSR2,r2
@@ -211,6 +211,77 @@ l2_disabled:
 	andi.	r1,r3,L1CSR0_DCE@l
 	beq	2b
 
+	.macro	create_tlb1_entry esel ts tsize epn wimg rpn perm phy_high scratch
+	lis	\scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	lis	\scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS1(1, 1, 0, \ts, \tsize)@l
+	mtspr	MAS1, \scratch
+	lis	\scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+	mtspr	MAS2, \scratch
+	lis	\scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+	mtspr	MAS3, \scratch
+	lis	\scratch, \phy_high@h
+	ori	\scratch, \scratch, \phy_high@l
+	mtspr	MAS7, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
+	.macro	create_tlb0_entry esel ts tsize epn wimg rpn perm phy_high scratch
+	lis	\scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	lis	\scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS1(1, 0, 0, \ts, \tsize)@l
+	mtspr	MAS1, \scratch
+	lis	\scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+	mtspr	MAS2, \scratch
+	lis	\scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS3(\rpn, 0, \perm)@l
+	mtspr	MAS3, \scratch
+	lis	\scratch, \phy_high@h
+	ori	\scratch, \scratch, \phy_high@l
+	mtspr	MAS7, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
+	.macro	delete_tlb1_entry esel scratch
+	lis	\scratch, FSL_BOOKE_MAS0(1, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(1, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	li	\scratch, 0
+	mtspr	MAS1, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
+	.macro	delete_tlb0_entry esel epn wimg scratch
+	lis	\scratch, FSL_BOOKE_MAS0(0, \esel, 0)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS0(0, \esel, 0)@l
+	mtspr	MAS0, \scratch
+	li	\scratch, 0
+	mtspr	MAS1, \scratch
+	lis	\scratch, FSL_BOOKE_MAS2(\epn, \wimg)@h
+	ori	\scratch, \scratch, FSL_BOOKE_MAS2(\epn, \wimg)@l
+	mtspr	MAS2, \scratch
+	isync
+	msync
+	tlbwe
+	isync
+	.endm
+
 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(CONFIG_NAND_SPL)
 /*
  * TLB entry for debuggging in AS1
@@ -220,61 +291,35 @@ l2_disabled:
  * in AS1.
  */
 
-	lis     r6,FSL_BOOKE_MAS0(1,
-			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@h
-	ori     r6,r6,FSL_BOOKE_MAS0(1,
-			CONFIG_SYS_PPC_E500_DEBUG_TLB, 0)@l
-
 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * bacause flash's virtual address maps to 0xff800000 - 0xffffffff.
  * and this window is outside of 4K boot window.
  */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_4M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
-							(MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000,
-							(MAS2_I|MAS2_G))@l
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_4M, \
+		CONFIG_SYS_MONITOR_BASE & 0xffc00000,  MAS2_I|MAS2_G, \
+		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 
-	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
-	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,(MAS2_I|MAS2_G))@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #else
 /*
  * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
  * because "nexti" will resize TLB to 4K
  */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE,
-							(MAS2_I))@l
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
+		0, BOOKE_PAGESZ_256K, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I, \
+		CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #endif
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	tlbwe
-	isync
 #endif
 
 /*
@@ -392,27 +437,11 @@ l2_disabled:
 	 */
 
 	/* create a temp mapping TLB0[0] for LBCR  */
-	lis     r6,FSL_BOOKE_MAS0(0, 0, 0)@h
-	ori     r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
-
-	lis     r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
-
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	isync
-	msync
-	tlbwe
+	create_tlb0_entry 0, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G, \
+		CONFIG_SYS_LBC_ADDR, MAS3_SW|MAS3_SR, \
+		0, r6
 
 	/* Set LBCR register */
 	lis     r4,CONFIG_SYS_LBCR_ADDR@h
@@ -551,49 +580,22 @@ create_ccsr_new_tlb:
 	ori	r8, r8, CONFIG_SYS_CCSRBAR@l
 	lis	r9, (CONFIG_SYS_CCSRBAR + 0x1000)@h
 	ori	r9, r9, (CONFIG_SYS_CCSRBAR + 0x1000)@l
-	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
-	lis     r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
-	ori     r1, r1, FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
-	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@h
-	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS_LOW, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-	lis	r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@h
-	ori	r7, r7, CONFIG_SYS_CCSRBAR_PHYS_HIGH@l
-	mtspr   MAS7, r7
-#endif
-	mtspr   MAS0, r0
-	mtspr   MAS1, r1
-	mtspr   MAS2, r2
-	mtspr   MAS3, r3
-	isync
-	msync
-	tlbwe
-
+	create_tlb0_entry 0, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, \
+		CONFIG_SYS_CCSRBAR_PHYS_LOW, MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
 	/*
 	 * Create a TLB for the current location of CCSR.  Register R9 is reserved
 	 * for the virtual address of this TLB (CONFIG_SYS_CCSRBAR + 0x1000).
 	 */
 create_ccsr_old_tlb:
-	lis     r0, FSL_BOOKE_MAS0(0, 1, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
-	lis     r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@h
-	ori     r3, r3, FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_DEFAULT, 0, (MAS3_SW|MAS3_SR))@l
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-	li	r7, 0	/* The default CCSR address is always a 32-bit number */
-	mtspr   MAS7, r7
-#endif
-	mtspr   MAS0, r0
-	/* MAS1 is the same as above */
-	mtspr   MAS2, r2
-	mtspr   MAS3, r3
-	isync
-	msync
-	tlbwe
+	create_tlb0_entry 1, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_CCSRBAR_DEFAULT, MAS3_SW|MAS3_SR, \
+		0, r3 /* The default CCSR address is always a 32-bit number */
+
 
 	/*
 	 * We have a TLB for what we think is the current (old) CCSR.  Let's
@@ -743,29 +745,46 @@ write_new_ccsrbar:
 
 	/* Delete the temporary TLBs */
 delete_temp_tlbs:
-	lis     r0, FSL_BOOKE_MAS0(0, 0, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 0, 0)@l
-	li	r1, 0
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, (MAS2_I|MAS2_G))@l
-	mtspr   MAS0, r0
-	mtspr   MAS1, r1
-	mtspr   MAS2, r2
-	isync
-	msync
-	tlbwe
+	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G, r3
+	delete_tlb0_entry 1, CONFIG_SYS_CCSRBAR + 0x1000, MAS2_I|MAS2_G, r3
 
-	lis     r0, FSL_BOOKE_MAS0(0, 1, 0)@h
-	ori     r0, r0, FSL_BOOKE_MAS0(0, 1, 0)@l
-	lis     r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@h
-	ori     r2, r2, FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR + 0x1000, (MAS2_I|MAS2_G))@l
-	mtspr   MAS0, r0
-	mtspr   MAS2, r2
-	isync
-	msync
-	tlbwe
 #endif /* #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR_PHYS) */
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+create_ccsr_l2_tlb:
+	/*
+	 * Create a TLB for the MMR location of CCSR
+	 * to access L2CSR0 register
+	 */
+	create_tlb0_entry 0, \
+		0, BOOKE_PAGESZ_4K, \
+		CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, \
+		CONFIG_SYS_CCSRBAR_PHYS_LOW + 0xC20000, MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_CCSRBAR_PHYS_HIGH, r3
+
+enable_l2_cluster_l2:
+	/* enable L2 cache */
+	lis	r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@h
+	ori	r3, r3, (CONFIG_SYS_CCSRBAR + 0xC20000)@l
+	li	r4, 33	/* stash id */
+	stw	r4, 4(r3)
+	lis	r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@h
+	ori	r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l
+	sync
+	stw	r4, 0(r3)	/* invalidate L2 */
+1:	sync
+	lwz	r0, 0(r3)
+	twi	0, r0, 0
+	isync
+	and.	r1, r0, r4
+	bne	1b
+	lis	r4, L2CSR0_L2E@h
+	sync
+	stw	r4, 0(r3)	/* eanble L2 */
+delete_ccsr_l2_tlb:
+	delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3
+#endif
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 #define DCSR_LAWBARH0	(CONFIG_SYS_CCSRBAR + 0x1000)
 #define LAW_SIZE_1M	0x13
@@ -1019,83 +1038,50 @@ create_init_ram_area:
 
 #if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SECURE_BOOT)
 	/* create a temp mapping in AS=1 to the 4M boot window */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_4M, \
+		CONFIG_SYS_MONITOR_BASE & 0xffc00000, MAS2_I|MAS2_G, \
+		0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
-
-	/* The 85xx has the default boot window 0xff800000 - 0xffffffff */
-	lis     r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
 #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
 	/* create a temp mapping in AS = 1 for Flash mapping
 	 * created by PBL for ISBC code
 	*/
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_PBI_FLASH_WINDOW, 0,
-						(MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #else
 	/*
 	 * create a temp mapping in AS=1 to the 1M CONFIG_SYS_MONITOR_BASE space, the main
 	 * image has been relocated to CONFIG_SYS_MONITOR_BASE on the second stage.
 	 */
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I|MAS2_G))@l
-
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_MONITOR_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry 15, \
+		1, BOOKE_PAGESZ_1M, \
+		CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
+		CONFIG_SYS_MONITOR_BASE, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #endif
 
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	isync
-	msync
-	tlbwe
-
 	/* create a temp mapping in AS=1 to the stack */
-	lis     r6,FSL_BOOKE_MAS0(1, 14, 0)@h
-	ori     r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
-
-	lis     r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
-	ori     r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
-
-	lis     r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
-	ori     r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
-
 #if defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) && \
     defined(CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH)
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
-				(MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, 0,
-				(MAS3_SX|MAS3_SW|MAS3_SR))@l
-	li      r10,CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH
-	mtspr	MAS7,r10
+	create_tlb1_entry 14, \
+		1, BOOKE_PAGESZ_16K, \
+		CONFIG_SYS_INIT_RAM_ADDR, 0, \
+		CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW, MAS3_SX|MAS3_SW|MAS3_SR, \
+		CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH, r6
+
 #else
-	lis     r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
-	ori     r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
+	create_tlb1_entry 14, \
+		1, BOOKE_PAGESZ_16K, \
+		CONFIG_SYS_INIT_RAM_ADDR, 0, \
+		CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, \
+		0, r6
 #endif
 
-	mtspr   MAS0,r6
-	mtspr   MAS1,r7
-	mtspr   MAS2,r8
-	mtspr   MAS3,r9
-	isync
-	msync
-	tlbwe
-
 	lis	r6,MSR_IS|MSR_DS|MSR_DE@h
 	ori	r6,r6,MSR_IS|MSR_DS|MSR_DE@l
 	lis	r7,switch_as@h
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
new file mode 100644
index 0000000..a8f16b1
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	/* dqrr liodn, frame data liodn, liodn off, sdest */
+	SET_QP_INFO(1, 27, 1, 0),
+	SET_QP_INFO(2, 28, 1, 0),
+	SET_QP_INFO(3, 29, 1, 1),
+	SET_QP_INFO(4, 30, 1, 1),
+	SET_QP_INFO(5, 31, 1, 2),
+	SET_QP_INFO(6, 32, 1, 2),
+	SET_QP_INFO(7, 33, 1, 3),
+	SET_QP_INFO(8, 34, 1, 3),
+	SET_QP_INFO(9, 35, 1, 4),
+	SET_QP_INFO(10, 36, 1, 4),
+	SET_QP_INFO(11, 37, 1, 5),
+	SET_QP_INFO(12, 38, 1, 5),
+	SET_QP_INFO(13, 39, 1, 6),
+	SET_QP_INFO(14, 40, 1, 6),
+	SET_QP_INFO(15, 41, 1, 7),
+	SET_QP_INFO(16, 42, 1, 7),
+	SET_QP_INFO(17, 43, 1, 8),
+	SET_QP_INFO(18, 44, 1, 8),
+	SET_QP_INFO(19, 45, 1, 9),
+	SET_QP_INFO(20, 46, 1, 9),
+	SET_QP_INFO(21, 47, 1, 10),
+	SET_QP_INFO(22, 48, 1, 10),
+	SET_QP_INFO(23, 49, 1, 11),
+	SET_QP_INFO(24, 50, 1, 11),
+	SET_QP_INFO(65, 89, 1, 0),
+	SET_QP_INFO(66, 90, 1, 0),
+	SET_QP_INFO(67, 91, 1, 1),
+	SET_QP_INFO(68, 92, 1, 1),
+	SET_QP_INFO(69, 93, 1, 2),
+	SET_QP_INFO(70, 94, 1, 2),
+	SET_QP_INFO(71, 95, 1, 3),
+	SET_QP_INFO(72, 96, 1, 3),
+	SET_QP_INFO(73, 97, 1, 4),
+	SET_QP_INFO(74, 98, 1, 4),
+	SET_QP_INFO(75, 99, 1, 5),
+	SET_QP_INFO(76, 100, 1, 5),
+	SET_QP_INFO(77, 101, 1, 6),
+	SET_QP_INFO(78, 102, 1, 6),
+	SET_QP_INFO(79, 103, 1, 7),
+	SET_QP_INFO(80, 104, 1, 7),
+	SET_QP_INFO(81, 105, 1, 8),
+	SET_QP_INFO(82, 106, 1, 8),
+	SET_QP_INFO(83, 107, 1, 9),
+	SET_QP_INFO(84, 108, 1, 9),
+	SET_QP_INFO(85, 109, 1, 10),
+	SET_QP_INFO(86, 110, 1, 10),
+	SET_QP_INFO(87, 111, 1, 11),
+	SET_QP_INFO(88, 112, 1, 11),
+	SET_QP_INFO(25, 51, 1, 0),
+	SET_QP_INFO(26, 52, 1, 0),
+};
+#endif
+
+struct srio_liodn_id_table srio_liodn_tbl[] = {
+	SET_SRIO_LIODN_1(1, 307),
+	SET_SRIO_LIODN_1(2, 387),
+};
+int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+
+struct liodn_id_table liodn_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_LIODN(62),
+	SET_BMAN_LIODN(63),
+#endif
+
+	SET_SDHC_LIODN(1, 552),
+
+	SET_PME_LIODN(117),
+
+	SET_USB_LIODN(1, "fsl-usb2-mph", 553),
+	SET_USB_LIODN(2, "fsl-usb2-dr", 554),
+
+	SET_SATA_LIODN(1, 555),
+	SET_SATA_LIODN(2, 556),
+
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
+	SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
+
+	SET_DMA_LIODN(1, 147),
+	SET_DMA_LIODN(2, 227),
+
+	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
+	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
+	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
+	SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0),
+
+#ifdef CONFIG_SYS_PMAN
+	SET_PMAN_LIODN(1, 513),
+	SET_PMAN_LIODN(2, 514),
+	SET_PMAN_LIODN(3, 515),
+#endif
+
+	/* SET_NEXUS_LIODN(557), -- not yet implemented */
+};
+int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct liodn_id_table fman1_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(1, 0, 88),
+	SET_FMAN_RX_1G_LIODN(1, 1, 89),
+	SET_FMAN_RX_1G_LIODN(1, 2, 90),
+	SET_FMAN_RX_1G_LIODN(1, 3, 91),
+	SET_FMAN_RX_1G_LIODN(1, 4, 92),
+	SET_FMAN_RX_1G_LIODN(1, 5, 93),
+	SET_FMAN_RX_10G_LIODN(1, 0, 94),
+	SET_FMAN_RX_10G_LIODN(1, 1, 95),
+};
+int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
+#if (CONFIG_SYS_NUM_FMAN == 2)
+struct liodn_id_table fman2_liodn_tbl[] = {
+	SET_FMAN_RX_1G_LIODN(2, 0, 88),
+	SET_FMAN_RX_1G_LIODN(2, 1, 89),
+	SET_FMAN_RX_1G_LIODN(2, 2, 90),
+	SET_FMAN_RX_1G_LIODN(2, 3, 91),
+	SET_FMAN_RX_1G_LIODN(2, 4, 92),
+	SET_FMAN_RX_1G_LIODN(2, 5, 93),
+	SET_FMAN_RX_10G_LIODN(2, 0, 94),
+	SET_FMAN_RX_10G_LIODN(2, 1, 95),
+};
+int fman2_liodn_tbl_sz = ARRAY_SIZE(fman2_liodn_tbl);
+#endif
+#endif
+
+struct liodn_id_table sec_liodn_tbl[] = {
+	SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
+	SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
+	SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
+	SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
+	SET_SEC_RTIC_LIODN_ENTRY(a, 453),
+	SET_SEC_RTIC_LIODN_ENTRY(b, 549),
+	SET_SEC_RTIC_LIODN_ENTRY(c, 550),
+	SET_SEC_RTIC_LIODN_ENTRY(d, 551),
+	SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
+	SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
+	SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
+	SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
+	SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
+	SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
+	SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
+	SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
+};
+int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
+
+#ifdef CONFIG_SYS_DPAA_RMAN
+struct liodn_id_table rman_liodn_tbl[] = {
+	/* Set RMan block 0-3 liodn offset */
+	SET_RMAN_LIODN(0, 678),
+	SET_RMAN_LIODN(1, 679),
+	SET_RMAN_LIODN(2, 680),
+	SET_RMAN_LIODN(3, 681),
+};
+int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl);
+#endif
+
+struct liodn_id_table liodn_bases[] = {
+#ifdef CONFIG_SYS_DPAA_DCE
+	[FSL_HW_PORTAL_DCE]  = SET_LIODN_BASE_2(618, 694),
+#endif
+	[FSL_HW_PORTAL_SEC]  = SET_LIODN_BASE_2(462, 558),
+#ifdef CONFIG_SYS_DPAA_FMAN
+	[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
+#if (CONFIG_SYS_NUM_FMAN == 2)
+	[FSL_HW_PORTAL_FMAN2] = SET_LIODN_BASE_1(1069),
+#endif
+#endif
+#ifdef CONFIG_SYS_DPAA_PME
+	[FSL_HW_PORTAL_PME]   = SET_LIODN_BASE_2(770, 846),
+#endif
+#ifdef CONFIG_SYS_DPAA_RMAN
+	[FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922),
+#endif
+};
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
new file mode 100644
index 0000000..102defa
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_serdes.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include "fsl_corenet2_serdes.h"
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10,
+		XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
+	{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
+		HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+	{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+		SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+	{38, {NONE, NONE, QSGMII_FM1_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+		SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC10, XAUI_FM2_MAC10,
+		XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
+	{2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
+		HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+	{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{38, {NONE, NONE, QSGMII_FM2_B, NONE,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+		SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+		NONE, NONE, QSGMII_FM1_A, NONE}},
+	{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+		XFI_FM2_MAC10, XFI_FM2_MAC9,
+		SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+		SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+	{}
+};
+static struct serdes_config serdes3_cfg_tbl[] = {
+	/* SerDes 3 */
+	{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+	{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+	{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+	{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
+	{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+	{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		PCIE2, PCIE2, PCIE2, PCIE2}},
+	{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+		SRIO1, SRIO1, SRIO1, SRIO1}},
+	{}
+};
+static struct serdes_config serdes4_cfg_tbl[] = {
+	/* SerDes 4 */
+	{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+	{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+	{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+	{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
+	{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
+	{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+	{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
+	{}
+};
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+	serdes3_cfg_tbl,
+	serdes4_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 929f6a6..a548dec 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -249,7 +249,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
 {
 	int i;
 	unsigned int tlb_size;
-	unsigned int wimge = 0;
+	unsigned int wimge = MAS2_M;
 	unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
 	unsigned int max_cam;
 	u64 size, memsize = (u64)memsize_in_meg << 20;
diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c
index 7800717..476ae93 100644
--- a/arch/powerpc/cpu/mpc85xx/traps.c
+++ b/arch/powerpc/cpu/mpc85xx/traps.c
@@ -82,8 +82,7 @@ extern void do_bedbug_breakpoint(struct pt_regs *);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -103,7 +102,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -131,24 +130,21 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
 }
 
-void
-CritcalInputException(struct pt_regs *regs)
+void CritcalInputException(struct pt_regs *regs)
 {
 	panic("Critical Input Exception");
 }
 
 int machinecheck_count = 0;
 int machinecheck_error = 0;
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 	unsigned int mcsr, mcsrr0, mcsrr1, mcar;
@@ -220,8 +216,7 @@ MachineCheckException(struct pt_regs *regs)
 	}
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -233,8 +228,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 	long esr_val;
 
@@ -257,8 +251,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-PITException(struct pt_regs *regs)
+void PITException(struct pt_regs *regs)
 {
 	/*
 	 * Reset PIT interrupt
@@ -271,9 +264,7 @@ PITException(struct pt_regs *regs)
 	timer_interrupt(NULL);
 }
 
-
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -285,8 +276,7 @@ UnknownException(struct pt_regs *regs)
 	_exception(0, regs);
 }
 
-void
-ExtIntException(struct pt_regs *regs)
+void ExtIntException(struct pt_regs *regs)
 {
 	volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 
@@ -305,8 +295,7 @@ ExtIntException(struct pt_regs *regs)
 	print_backtrace((unsigned long *)regs->gpr[1]);
 }
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 	printf("Debugger trap at @ %lx\n", regs->nip );
 	show_regs(regs);
@@ -318,8 +307,7 @@ DebugException(struct pt_regs *regs)
 /* Probe an address by reading.	 If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index 8ba9399..f7c4a22 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -70,9 +70,10 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 668158f..46dbaed 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -53,6 +53,10 @@ SECTIONS
 	}
 	_edata  =  .;
 
+	.u_boot_list : {
+		#include <u-boot.lst>
+	}
+
 	. = ALIGN(8);
 	__init_begin = .;
 	__init_end = .;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index efe34b7..4a40a1f 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -77,9 +77,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c
index 61f5110..2f955fe 100644
--- a/arch/powerpc/cpu/mpc86xx/fdt.c
+++ b/arch/powerpc/cpu/mpc86xx/fdt.c
@@ -20,7 +20,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #ifdef CONFIG_MP
 	int off;
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 #endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c
index 30c99eb..de705f0 100644
--- a/arch/powerpc/cpu/mpc86xx/mp.c
+++ b/arch/powerpc/cpu/mpc86xx/mp.c
@@ -90,8 +90,11 @@ int cpu_release(int nr, int argc, char * const argv[])
 	return 1;
 }
 
-u32 determine_mp_bootpg(void)
+u32 determine_mp_bootpg(unsigned int *pagesize)
 {
+	if (pagesize)
+		*pagesize = 4096;
+
 	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
 	if ((u64)gd->ram_size > 0xfffff000)
 		return (0xfff00000);
@@ -101,7 +104,7 @@ u32 determine_mp_bootpg(void)
 
 void cpu_mp_lmb_reserve(struct lmb *lmb)
 {
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 
 	/* tell u-boot we stole a page */
 	lmb_reserve(lmb, bootpg, 4096);
@@ -115,7 +118,7 @@ void setup_mp(void)
 {
 	extern ulong __secondary_start_page;
 	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg = determine_mp_bootpg();
+	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 bootpg_va;
 
 	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c
index 406403e..50069d5 100644
--- a/arch/powerpc/cpu/mpc86xx/traps.c
+++ b/arch/powerpc/cpu/mpc86xx/traps.c
@@ -52,8 +52,7 @@ extern ulong get_effective_memsize(void);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -74,8 +73,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void
-show_regs(struct pt_regs *regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -103,16 +101,14 @@ show_regs(struct pt_regs *regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception in kernel pc %lx signal %d", regs->nip, signr);
 }
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -158,8 +154,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler) (regs))
@@ -170,8 +165,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 	unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL;
 	int i, j;
@@ -196,8 +190,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler) (regs))
@@ -208,8 +201,7 @@ SoftEmuException(struct pt_regs *regs)
 	panic("Software Emulation Exception");
 }
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler) (regs))
@@ -226,8 +218,7 @@ UnknownException(struct pt_regs *regs)
  * If not present, return -1,
  * otherwise return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 	return 0;
 }
diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds
index 121e529..8bfadf2 100644
--- a/arch/powerpc/cpu/mpc86xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc86xx/u-boot.lds
@@ -64,9 +64,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index b348a98..d7c9090 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -460,7 +460,7 @@ static void fec_pin_init(int fecidx)
 
 #endif /* !CONFIG_RMII */
 
-#elif !defined(CONFIG_ICU862) && !defined(CONFIG_IAD210)
+#elif !defined(CONFIG_ICU862)
 		/*
 		 * Configure all of port D for MII.
 		 */
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 2c93e24..2ef77b4 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -473,20 +473,6 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	*((uint *) BCSR1) &= ~BCSR1_ETHEN;
 #endif /* MPC860ADS */
 
-#if defined(CONFIG_AMX860)
-	/*
-	 * Port B is used to control the PHY,MC68160.
-	 */
-	immr->im_cpm.cp_pbdir |=
-		(PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
-
-	immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
-	immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
-
-	immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
-	immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
-#endif /* AMX860 */
-
 #ifdef CONFIG_RPXCLASSIC
 	*((uchar *) BCSR0) &= ~BCSR0_ETHLPBK;
 	*((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
@@ -542,7 +528,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	 */
 #if defined (CONFIG_FADS)
 	udelay (10000);		/* wait 10 ms */
-#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
+#elif defined(CONFIG_RPXCLASSIC)
 	udelay (100000);	/* wait 100 ms */
 #endif
 
diff --git a/arch/powerpc/cpu/mpc8xx/traps.c b/arch/powerpc/cpu/mpc8xx/traps.c
index 343dced..f0ab78d 100644
--- a/arch/powerpc/cpu/mpc8xx/traps.c
+++ b/arch/powerpc/cpu/mpc8xx/traps.c
@@ -52,8 +52,7 @@ extern unsigned long search_exception_table(unsigned long);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -73,7 +72,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -101,16 +100,14 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception in kernel pc %lx signal %d",regs->nip,signr);
 }
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup;
 
@@ -153,8 +150,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -165,8 +161,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -177,8 +172,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-SoftEmuException(struct pt_regs *regs)
+void SoftEmuException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -190,8 +184,7 @@ SoftEmuException(struct pt_regs *regs)
 }
 
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -202,8 +195,7 @@ UnknownException(struct pt_regs *regs)
 	_exception(0, regs);
 }
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
   printf("Debugger trap at @ %lx\n", regs->nip );
   show_regs(regs);
@@ -215,8 +207,7 @@ DebugException(struct pt_regs *regs)
 /* Probe an address by reading.  If not present, return -1, otherwise
  * return 0.
  */
-int
-addr_probe(uint *addr)
+int addr_probe(uint *addr)
 {
 #if 0
 	int	retval;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 78a8f92..e8613be 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-struct cpu_type cpu_type_list [] = {
+static struct cpu_type cpu_type_list[] = {
 #if defined(CONFIG_MPC85xx)
 	CPU_TYPE_ENTRY(8533, 8533, 1),
 	CPU_TYPE_ENTRY(8535, 8535, 1),
@@ -73,6 +73,17 @@ struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(P4080, P4080, 8),
 	CPU_TYPE_ENTRY(P5010, P5010, 1),
 	CPU_TYPE_ENTRY(P5020, P5020, 2),
+	CPU_TYPE_ENTRY(P5021, P5021, 2),
+	CPU_TYPE_ENTRY(P5040, P5040, 4),
+	CPU_TYPE_ENTRY(T4240, T4240, 0),
+	CPU_TYPE_ENTRY(T4120, T4120, 0),
+	CPU_TYPE_ENTRY(B4860, B4860, 0),
+	CPU_TYPE_ENTRY(G4860, G4860, 0),
+	CPU_TYPE_ENTRY(G4060, G4060, 0),
+	CPU_TYPE_ENTRY(B4440, B4440, 0),
+	CPU_TYPE_ENTRY(G4440, G4440, 0),
+	CPU_TYPE_ENTRY(B4420, B4420, 0),
+	CPU_TYPE_ENTRY(B4220, B4220, 0),
 	CPU_TYPE_ENTRY(BSC9130, 9130, 1),
 	CPU_TYPE_ENTRY(BSC9131, 9131, 1),
 #elif defined(CONFIG_MPC86xx)
@@ -114,7 +125,7 @@ u32 compute_ppc_cpumask(void)
 #define compute_ppc_cpumask()	1
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
-struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
+static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
 
 struct cpu_type *identify_cpu(u32 ver)
 {
@@ -132,7 +143,7 @@ struct cpu_type *identify_cpu(u32 ver)
 /*
  * Return a 32-bit mask indicating which cores are present on this SOC.
  */
-u32 cpu_mask()
+u32 cpu_mask(void)
 {
 	ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
 	struct cpu_type *cpu = gd->cpu;
@@ -151,7 +162,8 @@ u32 cpu_mask()
 /*
  * Return the number of cores on this SOC.
  */
-int cpu_numcores() {
+int cpu_numcores(void)
+{
 	struct cpu_type *cpu = gd->cpu;
 
 	/*
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 2592873..088cc0e 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -28,7 +28,7 @@
 	#error "Undefined _DDR_ADDR"
 #endif
 
-u32 fsl_ddr_get_version(void)
+static u32 fsl_ddr_get_version(void)
 {
 	ccsr_ddr_t *ddr;
 	u32 ver_major_minor_errata;
@@ -229,6 +229,26 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 
 #if !defined(CONFIG_FSL_DDR1)
+static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
+{
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
+	if (dimm_params[0].n_ranks == 4)
+		return 1;
+#endif
+
+#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
+	if ((dimm_params[0].n_ranks == 2) &&
+		(dimm_params[1].n_ranks == 2))
+		return 1;
+
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+	if (dimm_params[0].n_ranks == 4)
+		return 1;
+#endif
+#endif
+	return 0;
+}
+
 /*
  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
  *
@@ -236,7 +256,8 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
  * dreams up non-zero default values to be backwards compatible.
  */
 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
-				const memctl_options_t *popts)
+				const memctl_options_t *popts,
+				const dimm_params_t *dimm_params)
 {
 	unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 	unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
@@ -266,7 +287,18 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int data_rate = get_ddr_freq(0);
 	tmrd_mclk = 4;
 	/* set the turnaround time */
-	trwt_mclk = 1;
+
+	/*
+	 * for single quad-rank DIMM and two dual-rank DIMMs
+	 * to avoid ODT overlap
+	 */
+	if (avoid_odt_overlap(dimm_params)) {
+		twwt_mclk = 2;
+		trrt_mclk = 1;
+	}
+	/* for faster clock, need more time for data setup */
+	trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
+
 	if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 		twrt_mclk = 1;
 
@@ -451,8 +483,8 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
 		| ((caslat_ctrl & 0xF) << 16)
 		| ((refrec_ctrl & 0xF) << 12)
 		| ((wrrec_mclk & 0x0F) << 8)
-		| ((acttoact_mclk & 0x07) << 4)
-		| ((wrtord_mclk & 0x07) << 0)
+		| ((acttoact_mclk & 0x0F) << 4)
+		| ((wrtord_mclk & 0x0F) << 0)
 		);
 	debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 }
@@ -659,6 +691,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int dqs_cfg;		/* DQS configuration */
 	unsigned int odt_cfg = 0;	/* ODT configuration */
 	unsigned int num_pr;		/* Number of posted refreshes */
+	unsigned int slow = 0;		/* DDR will be run less than 1250 */
 	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
 	unsigned int ap_en;		/* Address Parity Enable */
 	unsigned int d_init;		/* DRAM data initialization */
@@ -692,6 +725,10 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	obc_cfg = 0;
 #endif
 
+#if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
+	slow = get_ddr_freq(0) < 1249000000;
+#endif
+
 	if (popts->registered_dimm_en) {
 		rcw_en = 1;
 		ap_en = popts->ap_en;
@@ -720,6 +757,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 		| ((dqs_cfg & 0x3) << 26)
 		| ((odt_cfg & 0x3) << 21)
 		| ((num_pr & 0xf) << 12)
+		| ((slow & 1) << 11)
 		| (qd_en << 9)
 		| (unq_mrs_en << 8)
 		| ((obc_cfg & 0x1) << 6)
@@ -1347,6 +1385,11 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
 			       | ((wrlvl_start & 0x1F) << 0)
 			       );
 	debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
+	ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
+	debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
+	ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
+	debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
+
 }
 
 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
@@ -1370,6 +1413,12 @@ static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
 	debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
 }
 
+static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+	ddr->ddr_cdr2 = popts->ddr_cdr2;
+	debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
+}
+
 unsigned int
 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 {
@@ -1466,7 +1515,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 				break;
 			}
 			sa = common_dimm->base_address;
-			ea = common_dimm->total_mem - 1;
+			ea = sa + common_dimm->total_mem - 1;
 		} else if (!popts->memctl_interleaving) {
 			/*
 			 * If memory interleaving between controllers is NOT
@@ -1480,7 +1529,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 			case FSL_DDR_CS0_CS1_CS2_CS3:
 				sa = common_dimm->base_address;
-				ea = common_dimm->total_mem - 1;
+				ea = sa + common_dimm->total_mem - 1;
 				break;
 			case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 				if ((i >= 2) && (dimm_number == 0)) {
@@ -1537,17 +1586,19 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 		sa >>= 24;
 		ea >>= 24;
 
-		ddr->cs[i].bnds = (0
-			| ((sa & 0xFFF) << 16)	/* starting address MSB */
-			| ((ea & 0xFFF) << 0)	/* ending address MSB */
-			);
+		if (cs_en) {
+			ddr->cs[i].bnds = (0
+				| ((sa & 0xFFF) << 16)/* starting address MSB */
+				| ((ea & 0xFFF) << 0)	/* ending address MSB */
+				);
+		} else {
+			debug("FSLDDR: setting bnds to 0 for inactive CS\n");
+			ddr->cs[i].bnds = 0;
+		}
 
 		debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
-		if (cs_en) {
-			set_csn_config(dimm_number, i, ddr, popts, dimm_params);
-			set_csn_config_2(i, ddr);
-		} else
-			debug("CS%d is disabled.\n", i);
+		set_csn_config(dimm_number, i, ddr, popts, dimm_params);
+		set_csn_config_2(i, ddr);
 	}
 
 	/*
@@ -1560,7 +1611,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 	set_ddr_eor(ddr, popts);
 
 #if !defined(CONFIG_FSL_DDR1)
-	set_timing_cfg_0(ddr, popts);
+	set_timing_cfg_0(ddr, popts, dimm_params);
 #endif
 
 	set_timing_cfg_3(ddr, popts, common_dimm, cas_latency);
@@ -1569,6 +1620,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 				cas_latency, additive_latency);
 
 	set_ddr_cdr1(ddr, popts);
+	set_ddr_cdr2(ddr, popts);
 	set_ddr_sdram_cfg(ddr, popts, common_dimm);
 	ip_rev = fsl_ddr_get_version();
 	if (ip_rev > 0x40400)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
index f59d105..cb71f94 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/interactive.c
@@ -452,6 +452,8 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
+		CTRL_OPTIONS(ddr_cdr1),
+		CTRL_OPTIONS(ddr_cdr2),
 		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
 		CTRL_OPTIONS(tFAW_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
@@ -518,6 +520,8 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 		CFG_REGS(timing_cfg_5),
 		CFG_REGS(ddr_zq_cntl),
 		CFG_REGS(ddr_wrlvl_cntl),
+		CFG_REGS(ddr_wrlvl_cntl_2),
+		CFG_REGS(ddr_wrlvl_cntl_3),
 		CFG_REGS(ddr_sr_cntr),
 		CFG_REGS(ddr_sdram_rcw_1),
 		CFG_REGS(ddr_sdram_rcw_2),
@@ -525,6 +529,7 @@ static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
 		CFG_REGS(ddr_cdr2),
 		CFG_REGS(err_disable),
 		CFG_REGS(err_int_en),
+		CFG_REGS(ddr_eor),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
@@ -584,6 +589,8 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 		CFG_REGS(timing_cfg_5),
 		CFG_REGS(ddr_zq_cntl),
 		CFG_REGS(ddr_wrlvl_cntl),
+		CFG_REGS(ddr_wrlvl_cntl_2),
+		CFG_REGS(ddr_wrlvl_cntl_3),
 		CFG_REGS(ddr_sr_cntr),
 		CFG_REGS(ddr_sdram_rcw_1),
 		CFG_REGS(ddr_sdram_rcw_2),
@@ -593,7 +600,7 @@ static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
 		CFG_REGS(err_int_en),
 		CFG_REGS(ddr_sdram_rcw_2),
 		CFG_REGS(ddr_sdram_rcw_2),
-
+		CFG_REGS(ddr_eor),
 	};
 	static const unsigned int n_opts = ARRAY_SIZE(options);
 
@@ -689,6 +696,8 @@ static void print_memctl_options(const memctl_options_t *popts)
 		CTRL_OPTIONS(rcw_override),
 		CTRL_OPTIONS(rcw_1),
 		CTRL_OPTIONS(rcw_2),
+		CTRL_OPTIONS_HEX(ddr_cdr1),
+		CTRL_OPTIONS_HEX(ddr_cdr2),
 		CTRL_OPTIONS(tCKE_clock_pulse_width_ps),
 		CTRL_OPTIONS(tFAW_window_four_activates_ps),
 		CTRL_OPTIONS(trwt_override),
@@ -1597,6 +1606,7 @@ unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo)
 			 * doesn't return
 			 */
 			do_reset(NULL, 0, 0, NULL);
+			printf("Reset didn't work\n");
 		}
 
 		if (strcmp(argv[0], "recompute") == 0) {
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index 03a784c..9adde31 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -11,7 +11,8 @@
 
 #include "ddr.h"
 
-unsigned int
+#if defined(CONFIG_FSL_DDR3)
+static unsigned int
 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 			 common_timing_params_t *outpdimm,
 			 unsigned int number_of_dimms)
@@ -65,6 +66,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 
 	return 0;
 }
+#endif
 
 /*
  * compute_lowest_common_dimm_parameters()
@@ -76,7 +78,7 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
 unsigned int
 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 				      common_timing_params_t *outpdimm,
-				      unsigned int number_of_dimms)
+				      const unsigned int number_of_dimms)
 {
 	unsigned int i, j;
 
@@ -126,13 +128,20 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 			temp1++;
 			continue;
 		}
+
+		/*
+		 * check if quad-rank DIMM is plugged if
+		 * CONFIG_CHIP_SELECT_QUAD_CAPABLE is not defined
+		 * Only the board with proper design is capable
+		 */
+#ifndef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 		if (dimm_params[i].n_ranks == 4 && \
 		  CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
 			printf("Found Quad-rank DIMM, not able to support.");
 			temp1++;
 			continue;
 		}
-
+#endif
 		/*
 		 * Find minimum tCKmax_ps to find fastest slow speed,
 		 * i.e., this is the slowest the whole system can go.
@@ -236,11 +245,14 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 	if (outpdimm->all_DIMMs_registered)
 		for (j = 0; j < 16; j++) {
 			outpdimm->rcw[j] = dimm_params[0].rcw[j];
-			for (i = 1; i < number_of_dimms; i++)
+			for (i = 1; i < number_of_dimms; i++) {
+				if (!dimm_params[i].n_ranks)
+					continue;
 				if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
 					temp1 = 1;
 					break;
 				}
+			}
 		}
 
 	if (temp1 != 0)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index b47268c..d6b73c7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -77,7 +77,19 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
 				sizeof(generic_spd_eeprom_t));
 
 	if (ret) {
-		printf("DDR: failed to read SPD from address %u\n", i2c_address);
+		if (i2c_address ==
+#ifdef SPD_EEPROM_ADDRESS
+				SPD_EEPROM_ADDRESS
+#elif defined(SPD_EEPROM_ADDRESS1)
+				SPD_EEPROM_ADDRESS1
+#endif
+				) {
+			printf("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		} else {
+			debug("DDR: failed to read SPD from address %u\n",
+				i2c_address);
+		}
 		memset(spd, 0, sizeof(generic_spd_eeprom_t));
 	}
 }
@@ -526,6 +538,17 @@ phys_size_t fsl_ddr_sdram(void)
 #endif
 		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 
+	/* setup 3-way interleaving before enabling DDRC */
+	switch (info.memctl_opts[0].memctl_interleaving_mode) {
+	case FSL_DDR_3WAY_1KB_INTERLEAVING:
+	case FSL_DDR_3WAY_4KB_INTERLEAVING:
+	case FSL_DDR_3WAY_8KB_INTERLEAVING:
+		fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode);
+		break;
+	default:
+		break;
+	}
+
 	/* Program configuration registers. */
 	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 		debug("Programming controller %u\n", i);
@@ -561,7 +584,6 @@ phys_size_t fsl_ddr_sdram(void)
 			case FSL_DDR_3WAY_8KB_INTERLEAVING:
 				law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 				if (i == 0) {
-					fsl_ddr_set_intl3r(info.memctl_opts[i].memctl_interleaving_mode);
 					fsl_ddr_set_lawbar(&info.common_timing_params[i],
 						law_memctl, i);
 				}
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 13e4825..2f13b8f 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -474,6 +474,34 @@ static const struct dynamic_odt odt_unknown[4] = {
 	}
 };
 #endif
+
+/*
+ * Automatically seleect bank interleaving mode based on DIMMs
+ * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
+ * This function only deal with one or two slots per controller.
+ */
+static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
+{
+#if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+	if (pdimm[0].n_ranks == 4)
+		return FSL_DDR_CS0_CS1_CS2_CS3;
+	else if (pdimm[0].n_ranks == 2)
+		return FSL_DDR_CS0_CS1;
+#elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+	if (pdimm[0].n_ranks == 4)
+		return FSL_DDR_CS0_CS1_CS2_CS3;
+#endif
+	if (pdimm[0].n_ranks == 2) {
+		if (pdimm[1].n_ranks == 2)
+			return FSL_DDR_CS0_CS1_CS2_CS3;
+		else
+			return FSL_DDR_CS0_CS1;
+	}
+#endif
+	return 0;
+}
+
 unsigned int populate_memctl_options(int all_DIMMs_registered,
 			memctl_options_t *popts,
 			dimm_params_t *pdimm,
@@ -510,6 +538,14 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 		}
 	} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
 		switch (pdimm[0].n_ranks) {
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+		case 4:
+			pdodt = single_Q;
+			if (pdimm[1].n_ranks)
+				printf("Error: Quad- and Dual-rank DIMMs "
+					"cannot be used together\n");
+			break;
+#endif
 		case 2:
 			switch (pdimm[1].n_ranks) {
 			case 2:
@@ -900,6 +936,9 @@ done:
 		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
 						 "cs0_cs1_cs2_cs3", buf))
 			popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
+		else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
+						"auto", buf))
+			popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
 		else
 			printf("hwconfig has unrecognized parameter for bank_intlv.\n");
 		switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
@@ -912,6 +951,10 @@ done:
 					"interleaving disabled!\n", ctrl_num);
 			}
 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+			if (pdimm[0].n_ranks == 4)
+				break;
+#endif
 			if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
 				popts->ba_intlv_ctl = 0;
 				printf("Not enough bank(chip-select) for "
@@ -1063,7 +1106,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
 			break;
 		}
 		debug("%d of %d controllers are interleaving.\n", j, k);
-		if (j != k) {
+		if (j && (j != k)) {
 			for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 				pinfo->memctl_opts[i].memctl_interleaving = 0;
 			printf("Not all controllers have compatible "
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 664ad09..940ffff 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -121,6 +121,16 @@ void fsl_ddr_set_intl3r(const unsigned int granule_size)
 #endif
 }
 
+u32 fsl_ddr_get_intl3r(void)
+{
+	u32 val = 0;
+#ifdef CONFIG_E6500
+	u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
+	val = *mcintl3r;
+#endif
+	return val;
+}
+
 void board_add_ram_info(int use_default)
 {
 #if defined(CONFIG_MPC83xx)
@@ -140,6 +150,18 @@ void board_add_ram_info(int use_default)
 	uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 	int cas_lat;
 
+#if CONFIG_NUM_DDR_CONTROLLERS >= 2
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+		sdram_cfg = in_be32(&ddr->sdram_cfg);
+	}
+#endif
+#if CONFIG_NUM_DDR_CONTROLLERS >= 3
+	if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
+		ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+		sdram_cfg = in_be32(&ddr->sdram_cfg);
+	}
+#endif
 	puts(" (DDR");
 	switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 		SDRAM_CFG_SDRAM_TYPE_SHIFT) {
diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c
index 32ab050..68db8e2 100644
--- a/arch/powerpc/cpu/mpc8xxx/fdt.c
+++ b/arch/powerpc/cpu/mpc8xxx/fdt.c
@@ -139,6 +139,8 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 	const char *phys[] = { "ulpi", "utmi" };
 	const char *mode = NULL;
 	const char *phy_type = NULL;
+	const char *dr_mode_type = NULL;
+	const char *dr_phy_type = NULL;
 	char usb1_defined = 0;
 	int usb_mode_off = -1;
 	int usb_phy_off = -1;
@@ -156,6 +158,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 					break;
 				}
 			}
+
 			for (j = 0; j < ARRAY_SIZE(phys); j++) {
 				if (hwconfig_subarg_cmp(str, "phy_type",
 						phys[j])) {
@@ -163,31 +166,46 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 					break;
 				}
 			}
-			if (mode_idx >= 0) {
-				usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
-					modes[mode_idx], NULL, usb_mode_off);
-				if (usb_mode_off < 0)
-					return;
-			}
-			if (phy_idx >= 0) {
-				usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
-					NULL, phys[phy_idx], usb_phy_off);
-				if (usb_phy_off < 0)
-					return;
-			}
+
+			dr_mode_type = modes[mode_idx];
+			dr_phy_type = phys[phy_idx];
+
+			/* use usb_dr_mode and usb_phy_type if
+			   usb1_defined = 0; these variables are to
+			   be deprecated */
 			if (!strcmp(str, "usb1"))
 				usb1_defined = 1;
-			if (mode_idx < 0 && phy_idx < 0)
+
+			if (mode_idx < 0 && phy_idx < 0) {
 				printf("WARNING: invalid phy or mode\n");
+				return;
+			}
 		}
+
+		usb_mode_off = fdt_fixup_usb_mode_phy_type(blob,
+			dr_mode_type, NULL, usb_mode_off);
+
+		if (usb_mode_off < 0)
+			return;
+
+		usb_phy_off = fdt_fixup_usb_mode_phy_type(blob,
+			NULL, dr_phy_type, usb_phy_off);
+
+		if (usb_phy_off < 0)
+			return;
 	}
+
 	if (!usb1_defined) {
 		int usb_off = -1;
 		mode = getenv("usb_dr_mode");
 		phy_type = getenv("usb_phy_type");
-		if (!mode && !phy_type)
-			return;
-		fdt_fixup_usb_mode_phy_type(blob, mode, phy_type, usb_off);
+		if (mode || phy_type) {
+			printf("WARNING: usb_dr_mode and usb_phy_type "
+				"are to be deprecated soon. Use "
+				"hwconfig to set these values instead!!\n");
+			fdt_fixup_usb_mode_phy_type(blob, mode,
+				phy_type, usb_off);
+		}
 	}
 }
 #endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
index 023ac9a..c1fe579 100644
--- a/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
@@ -11,7 +11,7 @@
 
 #ifdef CONFIG_MPC85xx
 /* Boards should provide their own version of this if they use lbc sdram */
-void __lbc_sdram_init(void)
+static void __lbc_sdram_init(void)
 {
 	/* Do nothing */
 }
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 0cb65b3..6e6f7dc 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -22,7 +22,9 @@
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
+#include <asm/errno.h>
 
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define SRIO_PORT_ACCEPT_ALL 0x10000001
 #define SRIO_IB_ATMU_AR 0x80f55000
 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@@ -31,10 +33,16 @@
 #define SRIO_MAINT_WIN_SIZE 0x1000000 /* 16M */
 #define SRIO_RW_WIN_SIZE 0x100000 /* 1M */
 #define SRIO_LCSBA1CSR 0x60000000
+#endif
 
 #if defined(CONFIG_FSL_CORENET)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR3_SRIO1
+	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR3_SRIO2
+#else
 	#define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1
 	#define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2
+#endif
 	#define _DEVDISR_RMU   FSL_CORENET_DEVDISR_RMU
 	#define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
 #elif defined(CONFIG_MPC85xx)
@@ -52,16 +60,206 @@
 #error "No defines for DEVDISR_SRIO"
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+/*
+ * Erratum A-004034
+ * Affects: SRIO
+ * Description: During port initialization, the SRIO port performs
+ * lane synchronization (detecting valid symbols on a lane) and
+ * lane alignment (coordinating multiple lanes to receive valid data
+ * across lanes). Internal errors in lane synchronization and lane
+ * alignment may cause failure to achieve link initialization at
+ * the configured port width.
+ * An SRIO port configured as a 4x port may see one of these scenarios:
+ * 1. One or more lanes fails to achieve lane synchronization. Depending
+ * on which lanes fail, this may result in downtraining from 4x to 1x
+ * on lane 0, 4x to 1x on lane R (redundant lane).
+ * 2. The link may fail to achieve lane alignment as a 4x, even though
+ * all 4 lanes achieve lane synchronization, and downtrain to a 1x.
+ * An SRIO port configured as a 1x port may fail to complete port
+ * initialization (PnESCSR[PU] never deasserts) because of scenario 1.
+ * Impact: SRIO port may downtrain to 1x, or may fail to complete
+ * link initialization. Once a port completes link initialization
+ * successfully, it will operate normally.
+ */
+static int srio_erratum_a004034(u8 port)
+{
+	serdes_corenet_t *srds_regs;
+	u32 conf_lane;
+	u32 init_lane;
+	int idx, first, last;
+	u32 i;
+	unsigned long long end_tick;
+	struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+
+	srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+	conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
+			>> (12 - port * 4)) & 0x3;
+	init_lane = (in_be32((void *)&srio_regs->lp_serial
+			.port[port].pccsr) >> 27) & 0x7;
+
+	/*
+	 * Start a counter set to ~2 ms after the SERDES reset is
+	 * complete (SERDES SRDSBnRSTCTL[RST_DONE]=1 for n
+	 * corresponding to the SERDES bank/PLL for the SRIO port).
+	 */
+	 if (in_be32((void *)&srds_regs->bank[0].rstctl)
+		& SRDS_RSTCTL_RSTDONE) {
+		/*
+		 * Poll the port uninitialized status (SRIO PnESCSR[PO]) until
+		 * PO=1 or the counter expires. If the counter expires, the
+		 * port has failed initialization: go to recover steps. If PO=1
+		 * and the desired port width is 1x, go to normal steps. If
+		 * PO = 1 and the desired port width is 4x, go to recover steps.
+		 */
+		end_tick = usec2ticks(2000) + get_ticks();
+		do {
+			if (in_be32((void *)&srio_regs->lp_serial
+				.port[port].pescsr) & 0x2) {
+				if (conf_lane == 0x1)
+					goto host_ok;
+				else {
+					if (init_lane == 0x2)
+						goto host_ok;
+					else
+						break;
+				}
+			}
+		} while (end_tick > get_ticks());
+
+		/* recover at most 3 times */
+		for (i = 0; i < 3; i++) {
+			/* Set SRIO PnCCSR[PD]=1 */
+			setbits_be32((void *)&srio_regs->lp_serial
+					.port[port].pccsr,
+					0x800000);
+			/*
+			* Set SRIO PnPCR[OBDEN] on the host to
+			* enable the discarding of any pending packets.
+			*/
+			setbits_be32((void *)&srio_regs->impl.port[port].pcr,
+				0x04);
+			/* Wait 50 us */
+			udelay(50);
+			/* Run sync command */
+			isync();
+
+			if (port)
+				first = serdes_get_first_lane(SRIO2);
+			else
+				first = serdes_get_first_lane(SRIO1);
+			if (unlikely(first < 0))
+				return -ENODEV;
+			if (conf_lane == 0x1)
+				last = first;
+			else
+				last = first + 3;
+			/*
+			 * Set SERDES BnGCRm0[RRST]=0 for each SRIO
+			 * bank n and lane m.
+			 */
+			for (idx = first; idx <= last; idx++)
+				clrbits_be32(&srds_regs->lane[idx].gcr0,
+				SRDS_GCR0_RRST);
+			/*
+			 * Read SERDES BnGCRm0 for each SRIO
+			 * bank n and lane m
+			 */
+			for (idx = first; idx <= last; idx++)
+				in_be32(&srds_regs->lane[idx].gcr0);
+			/* Run sync command */
+			isync();
+			/* Wait >= 100 ns */
+			udelay(1);
+			/*
+			 * Set SERDES BnGCRm0[RRST]=1 for each SRIO
+			 * bank n and lane m.
+			 */
+			for (idx = first; idx <= last; idx++)
+				setbits_be32(&srds_regs->lane[idx].gcr0,
+				SRDS_GCR0_RRST);
+			/*
+			 * Read SERDES BnGCRm0 for each SRIO
+			 * bank n and lane m
+			 */
+			for (idx = first; idx <= last; idx++)
+				in_be32(&srds_regs->lane[idx].gcr0);
+			/* Run sync command */
+			isync();
+			/* Wait >= 300 ns */
+			udelay(1);
+
+			/* Write 1 to clear all bits in SRIO PnSLCSR */
+			out_be32((void *)&srio_regs->impl.port[port].slcsr,
+				0xffffffff);
+			/* Clear SRIO PnPCR[OBDEN] on the host */
+			clrbits_be32((void *)&srio_regs->impl.port[port].pcr,
+				0x04);
+			/* Set SRIO PnCCSR[PD]=0 */
+			clrbits_be32((void *)&srio_regs->lp_serial
+				.port[port].pccsr,
+				0x800000);
+			/* Wait >= 24 ms */
+			udelay(24000);
+			/* Poll the state of the port again */
+			init_lane =
+				(in_be32((void *)&srio_regs->lp_serial
+					.port[port].pccsr) >> 27) & 0x7;
+			if (in_be32((void *)&srio_regs->lp_serial
+				.port[port].pescsr) & 0x2) {
+				if (conf_lane == 0x1)
+					goto host_ok;
+				else {
+					if (init_lane == 0x2)
+						goto host_ok;
+				}
+			}
+			if (i == 2)
+				return -ENODEV;
+		}
+	} else
+		return -ENODEV;
+
+host_ok:
+	/* Poll PnESCSR[OES] on the host until it is clear */
+	end_tick = usec2ticks(1000000) + get_ticks();
+	do {
+		if (!(in_be32((void *)&srio_regs->lp_serial.port[port].pescsr)
+			& 0x10000)) {
+			out_be32(((void *)&srio_regs->lp_serial
+				.port[port].pescsr), 0xffffffff);
+			out_be32(((void *)&srio_regs->phys_err
+				.port[port].edcsr), 0);
+			out_be32(((void *)&srio_regs->logical_err.ltledcsr), 0);
+			return 0;
+		}
+	} while (end_tick > get_ticks());
+
+	return -ENODEV;
+}
+#endif
+
 void srio_init(void)
 {
 	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
 	int srio1_used = 0, srio2_used = 0;
+	u32 *devdisr;
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	devdisr = &gur->devdisr3;
+#else
+	devdisr = &gur->devdisr;
+#endif
 	if (is_serdes_configured(SRIO1)) {
 		set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
 				law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
 				LAW_TRGT_IF_RIO_1);
 		srio1_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+		if (srio_erratum_a004034(0) < 0)
+			printf("SRIO1: enabled but port error\n");
+		else
+#endif
 		printf("SRIO1: enabled\n");
 	} else {
 		printf("SRIO1: disabled\n");
@@ -73,7 +271,13 @@ void srio_init(void)
 				law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
 				LAW_TRGT_IF_RIO_2);
 		srio2_used = 1;
+#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+		if (srio_erratum_a004034(1) < 0)
+			printf("SRIO2: enabled but port error\n");
+		else
+#endif
 		printf("SRIO2: enabled\n");
+
 	} else {
 		printf("SRIO2: disabled\n");
 	}
@@ -82,20 +286,20 @@ void srio_init(void)
 #ifdef CONFIG_FSL_CORENET
 	/* On FSL_CORENET devices we can disable individual ports */
 	if (!srio1_used)
-		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1);
+		setbits_be32(devdisr, _DEVDISR_SRIO1);
 	if (!srio2_used)
-		setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2);
+		setbits_be32(devdisr, _DEVDISR_SRIO2);
 #endif
 
 	/* neither port is used - disable everything */
 	if (!srio1_used && !srio2_used) {
-		setbits_be32(&gur->devdisr, _DEVDISR_SRIO1);
-		setbits_be32(&gur->devdisr, _DEVDISR_SRIO2);
-		setbits_be32(&gur->devdisr, _DEVDISR_RMU);
+		setbits_be32(devdisr, _DEVDISR_SRIO1);
+		setbits_be32(devdisr, _DEVDISR_SRIO2);
+		setbits_be32(devdisr, _DEVDISR_RMU);
 	}
 }
 
-#ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 void srio_boot_master(int port)
 {
 	struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c
index 9baa7a1..dae19cb 100644
--- a/arch/powerpc/cpu/ppc4xx/traps.c
+++ b/arch/powerpc/cpu/ppc4xx/traps.c
@@ -74,8 +74,7 @@ extern void do_bedbug_breakpoint(struct pt_regs *);
  * Trap & Exception support
  */
 
-void
-print_backtrace(unsigned long *sp)
+static void print_backtrace(unsigned long *sp)
 {
 	int cnt = 0;
 	unsigned long i;
@@ -95,7 +94,7 @@ print_backtrace(unsigned long *sp)
 	printf("\n");
 }
 
-void show_regs(struct pt_regs * regs)
+void show_regs(struct pt_regs *regs)
 {
 	int i;
 
@@ -121,16 +120,14 @@ void show_regs(struct pt_regs * regs)
 }
 
 
-void
-_exception(int signr, struct pt_regs *regs)
+static void _exception(int signr, struct pt_regs *regs)
 {
 	show_regs(regs);
 	print_backtrace((unsigned long *)regs->gpr[1]);
 	panic("Exception");
 }
 
-void
-MachineCheckException(struct pt_regs *regs)
+void MachineCheckException(struct pt_regs *regs)
 {
 	unsigned long fixup, val;
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
@@ -312,8 +309,7 @@ MachineCheckException(struct pt_regs *regs)
 	panic("machine check");
 }
 
-void
-AlignmentException(struct pt_regs *regs)
+void AlignmentException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -325,8 +321,7 @@ AlignmentException(struct pt_regs *regs)
 	panic("Alignment Exception");
 }
 
-void
-ProgramCheckException(struct pt_regs *regs)
+void ProgramCheckException(struct pt_regs *regs)
 {
 	long esr_val;
 
@@ -349,8 +344,7 @@ ProgramCheckException(struct pt_regs *regs)
 	panic("Program Check Exception");
 }
 
-void
-DecrementerPITException(struct pt_regs *regs)
+void DecrementerPITException(struct pt_regs *regs)
 {
 	/*
 	 * Reset PIT interrupt
@@ -364,8 +358,7 @@ DecrementerPITException(struct pt_regs *regs)
 }
 
 
-void
-UnknownException(struct pt_regs *regs)
+void UnknownException(struct pt_regs *regs)
 {
 #if defined(CONFIG_CMD_KGDB)
 	if (debugger_exception_handler && (*debugger_exception_handler)(regs))
@@ -377,8 +370,7 @@ UnknownException(struct pt_regs *regs)
 	_exception(0, regs);
 }
 
-void
-DebugException(struct pt_regs *regs)
+void DebugException(struct pt_regs *regs)
 {
 	printf("Debugger trap at @ %lx\n", regs->nip );
 	show_regs(regs);
diff --git a/arch/powerpc/cpu/ppc4xx/u-boot.lds b/arch/powerpc/cpu/ppc4xx/u-boot.lds
index 2466b79..a96ddd5 100644
--- a/arch/powerpc/cpu/ppc4xx/u-boot.lds
+++ b/arch/powerpc/cpu/ppc4xx/u-boot.lds
@@ -78,9 +78,11 @@ SECTIONS
   PROVIDE (edata = .);
 
   . = .;
-  __u_boot_cmd_start = .;
-  .u_boot_cmd : { *(.u_boot_cmd) }
-  __u_boot_cmd_end = .;
+
+  . = ALIGN(4);
+  .u_boot_list : {
+	#include <u-boot.lst>
+  }
 
   . = .;
   __start___ex_table = .;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index aa27741..03baaee 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -27,6 +27,8 @@
 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
 #endif
 
+#define FSL_DDR_VER_4_7	47
+
 /* Number of TLB CAM entries we have on FSL Book-E chips */
 #if defined(CONFIG_E500MC)
 #define CONFIG_SYS_NUM_TLBCAMS		64
@@ -311,6 +313,7 @@
 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM	2
 
 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -331,6 +334,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -338,8 +342,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P3041)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			4
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -360,6 +366,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -367,8 +374,10 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2	0x11
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			8
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	4
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -389,7 +398,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
-#define CONFIG_SYS_FSL_ERRATUM_ESDHC136
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
 #define CONFIG_SYS_P4080_ERRATUM_CPU22
 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
@@ -398,6 +407,7 @@
 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
@@ -406,8 +416,11 @@
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x20
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
 
 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
 #define CONFIG_MAX_CPUS			2
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_NUM_LAWS		32
@@ -426,12 +439,43 @@
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
 #define CONFIG_SYS_FSL_ERRATUM_A004510
 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
+#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
+
+#elif defined(CONFIG_PPC_P5040)
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	3
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	5
+#define CONFIG_SYS_NUM_FM1_10GEC	1
+#define CONFIG_SYS_NUM_FM2_DTSEC	5
+#define CONFIG_SYS_NUM_FM2_10GEC	1
+#define CONFIG_NUM_DDR_CONTROLLERS	2
+#define CONFIG_SYS_FM_MURAM_SIZE	0x28000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_USB138
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
+#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
+#define CONFIG_SYS_FSL_ERRATUM_A004699
+#define CONFIG_SYS_FSL_ELBC_MULTIBIT_ECC
+#define CONFIG_SYS_FSL_ERRATUM_A004510
+#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV	0x10
+#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
 
 #elif defined(CONFIG_BSC9131)
 #define CONFIG_MAX_CPUS			1
@@ -445,6 +489,63 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_PPC_T4240)
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_MAX_CPUS			12
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	5
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SRDS_3
+#define CONFIG_SYS_FSL_SRDS_4
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		2
+#define CONFIG_SYS_NUM_FM1_DTSEC	8
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_SYS_NUM_FM2_DTSEC	8
+#define CONFIG_SYS_NUM_FM2_10GEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	3
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v3.0"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
+#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+
+#elif defined(CONFIG_PPC_B4860)
+#define CONFIG_SYS_PPC64		/* 64-bit core */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
+#define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
+#define CONFIG_MAX_CPUS			4
+#define CONFIG_SYS_FSL_NUM_CC_PLLS	4
+#define CONFIG_SYS_FSL_NUM_LAWS		32
+#define CONFIG_SYS_FSL_SEC_COMPAT	4
+#define CONFIG_SYS_NUM_FMAN		1
+#define CONFIG_SYS_NUM_FM1_DTSEC	6
+#define CONFIG_SYS_NUM_FM1_10GEC	2
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_4_7
+#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FM_MURAM_SIZE	0x60000
+#define CONFIG_SYS_FSL_TBCLK_DIV	16
+#define CONFIG_SYS_FSL_PCIE_COMPAT	"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SRIO_MAX_PORTS	2
+#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM	9
+#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM	5
+#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
+
 #else
 #error Processor type not defined for this platform
 #endif
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index e271342..640d329 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -84,6 +84,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define FSL_DDR_4WAY_4KB_INTERLEAVING	0x1C
 #define FSL_DDR_4WAY_8KB_INTERLEAVING	0x1D
 
+#define SDRAM_CS_CONFIG_EN		0x80000000
+
 /* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
  */
 #define SDRAM_CFG_MEM_EN		0x80000000
@@ -96,6 +98,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
 #define SDRAM_CFG_DYN_PWR		0x00200000
 #define SDRAM_CFG_DBW_MASK		0x00180000
+#define SDRAM_CFG_DBW_SHIFT		19
 #define SDRAM_CFG_32_BE			0x00080000
 #define SDRAM_CFG_16_BE			0x00100000
 #define SDRAM_CFG_8_BE			0x00040000
@@ -145,6 +148,31 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 
 /* DDR_CDR1 */
 #define DDR_CDR1_DHC_EN	0x80000000
+#define DDR_CDR1_ODT_SHIFT	17
+#define DDR_CDR1_ODT_MASK	0x6
+#define DDR_CDR2_ODT_MASK	0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+
+#if (defined(CONFIG_SYS_FSL_DDR_VER) && \
+	(CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))
+#define DDR_CDR_ODT_OFF		0x0
+#define DDR_CDR_ODT_120ohm	0x1
+#define DDR_CDR_ODT_180ohm	0x2
+#define DDR_CDR_ODT_75ohm	0x3
+#define DDR_CDR_ODT_110ohm	0x4
+#define DDR_CDR_ODT_60hm	0x5
+#define DDR_CDR_ODT_70ohm	0x6
+#define DDR_CDR_ODT_47ohm	0x7
+#else
+#define DDR_CDR_ODT_75ohm	0x0
+#define DDR_CDR_ODT_55ohm	0x1
+#define DDR_CDR_ODT_60ohm	0x2
+#define DDR_CDR_ODT_50ohm	0x3
+#define DDR_CDR_ODT_150ohm	0x4
+#define DDR_CDR_ODT_43ohm	0x5
+#define DDR_CDR_ODT_120ohm	0x6
+#endif
 
 /* Record of register values computed */
 typedef struct fsl_ddr_cfg_regs_s {
@@ -177,6 +205,8 @@ typedef struct fsl_ddr_cfg_regs_s {
 	unsigned int timing_cfg_5;
 	unsigned int ddr_zq_cntl;
 	unsigned int ddr_wrlvl_cntl;
+	unsigned int ddr_wrlvl_cntl_2;
+	unsigned int ddr_wrlvl_cntl_3;
 	unsigned int ddr_sr_cntr;
 	unsigned int ddr_sdram_rcw_1;
 	unsigned int ddr_sdram_rcw_2;
@@ -262,6 +292,8 @@ typedef struct memctl_options_s {
 	unsigned int wrlvl_override;
 	unsigned int wrlvl_sample;		/* Write leveling */
 	unsigned int wrlvl_start;
+	unsigned int wrlvl_ctl_2;
+	unsigned int wrlvl_ctl_3;
 
 	unsigned int half_strength_driver_enable;
 	unsigned int twoT_en;
@@ -288,6 +320,7 @@ typedef struct memctl_options_s {
 	unsigned int rcw_2;
 	/* control register 1 */
 	unsigned int ddr_cdr1;
+	unsigned int ddr_cdr2;
 
 	unsigned int trwt_override;
 	unsigned int trwt;			/* read-to-write turnaround */
@@ -298,6 +331,7 @@ extern phys_size_t fsl_ddr_sdram_size(void);
 extern int fsl_use_spd(void);
 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 					unsigned int ctrl_num);
+u32 fsl_ddr_get_intl3r(void);
 
 /*
  * The 85xx boards have a common prototype for fixed_sdram so put the
diff --git a/arch/powerpc/include/asm/fsl_fman.h b/arch/powerpc/include/asm/fsl_fman.h
index 2c0c9bc..299daca 100644
--- a/arch/powerpc/include/asm/fsl_fman.h
+++ b/arch/powerpc/include/asm/fsl_fman.h
@@ -423,6 +423,14 @@ typedef struct fm_10gec_mdio {
 	u8	res[4*1024];
 } fm_10gec_mdio_t;
 
+typedef struct fm_memac {
+	u8	res[4*1024];
+} fm_memac_t;
+
+typedef struct fm_memac_mdio {
+	u8	res[4*1024];
+} fm_memac_mdio_t;
+
 typedef struct fm_1588 {
 	u8	res[4*1024];
 } fm_1588_t;
@@ -446,6 +454,14 @@ typedef struct ccsr_fman {
 	u8			res1[8*1024];
 	fm_soft_parser_t	fm_soft_parser;
 	u8			res2[96*1024];
+#ifdef CONFIG_SYS_FMAN_V3
+	struct {
+		fm_memac_t		fm_memac;
+		fm_memac_mdio_t		fm_memac_mdio;
+	} memac[10];
+	u8			res4[32*1024];
+	fm_memac_mdio_t		fm_dedicated_mdio[2];
+#else
 	struct {
 		fm_dtsec_t	fm_dtesc;
 		fm_mdio_t	fm_mdio;
@@ -455,6 +471,7 @@ typedef struct ccsr_fman {
 		fm_10gec_mdio_t		fm_10gec_mdio;
 	} mac_10g[1];
 	u8			res4[48*1024];
+#endif
 	fm_1588_t		fm_1588;
 	u8			res5[4*1024];
 } ccsr_fman_t;
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index a9973b8..d759de9 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -94,6 +94,11 @@ extern void fdt_fixup_liodn(void *blob);
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
 		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 
+#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
+	SET_LIODN_ENTRY_1(compat, liodn,\
+		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
+		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
+
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, liodn) \
 	SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
@@ -118,6 +123,12 @@ extern void fdt_fixup_liodn(void *blob);
 		CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
 		CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 
+#define SET_PMAN_LIODN(num, liodn) \
+	SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
+		offsetof(struct ccsr_pman, ppa1) + \
+		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+
 /* -1 from portID due to how immap has the registers */
 #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
 	CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
@@ -184,11 +195,13 @@ extern void fdt_fixup_liodn(void *blob);
 extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
 extern struct liodn_id_table raide_liodn_tbl[];
 extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
+#ifdef CONFIG_SYS_SRIO
 extern struct srio_liodn_id_table srio_liodn_tbl[];
+extern int srio_liodn_tbl_sz;
+#endif
 extern struct liodn_id_table rman_liodn_tbl[];
 extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
 extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
-extern int srio_liodn_tbl_sz;
 extern int rman_liodn_tbl_sz;
 
 #endif
diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h
new file mode 100644
index 0000000..d6b60e6
--- /dev/null
+++ b/arch/powerpc/include/asm/fsl_memac.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *	Roy Zang <tie-fei.zang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __MEMAC_H__
+#define __MEMAC_H__
+
+#include <phy.h>
+
+struct memac {
+	/* memac general control and status registers */
+	u32	res_0[2];
+	u32	command_config;	/* Control and configuration register */
+	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
+	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
+	u32	maxfrm;		/* Maximum frame length register */
+	u32	res_18[5];
+	u32	hashtable_ctrl;	/* Hash table control register */
+	u32	res_30[4];
+	u32	ievent;		/* Interrupt event register */
+	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
+	u32	res_48;
+	u32	imask;		/* interrupt mask register */
+	u32	res_50;
+	u32	cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
+	u32	cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
+	u32	rx_pause_status;	/* Receive pause status register */
+	u32	res_78[2];
+	u32	mac_addr[14];	/* MAC address */
+	u32	lpwake_timer;	/* EEE low power wakeup timer register */
+	u32	sleep_timer;	/* Transmit EEE Low Power Timer register */
+	u32	res_c0[8];
+	u32	statn_config;	/* Statistics configuration register */
+	u32	res_e4[7];
+
+	/* memac statistics counter registers */
+	u32	rx_eoct_l;	/* Rx ethernet octests lower */
+	u32	rx_eoct_u;	/* Rx ethernet octests upper */
+	u32	rx_oct_l;	/* Rx octests lower */
+	u32	rx_oct_u;	/* Rx octests upper */
+	u32	rx_align_err_l;	/* Rx alignment error lower */
+	u32	rx_align_err_u;	/* Rx alignment error upper */
+	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
+	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
+	u32	rx_frame_l;	/* Rx frame counter lower */
+	u32	rx_frame_u;	/* Rx frame counter upper */
+	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
+	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
+	u32	rx_vlan_l;	/* Rx VLAN frame lower */
+	u32	rx_vlan_u;	/* Rx VLAN frame upper */
+	u32	rx_err_l;	/* Rx frame error lower */
+	u32	rx_err_u;	/* Rx frame error upper */
+	u32	rx_uni_l;	/* Rx unicast frame lower */
+	u32	rx_uni_u;	/* Rx unicast frame upper */
+	u32	rx_multi_l;	/* Rx multicast frame lower */
+	u32	rx_multi_u;	/* Rx multicast frame upper */
+	u32	rx_brd_l;	/* Rx broadcast frame lower */
+	u32	rx_brd_u;	/* Rx broadcast frame upper */
+	u32	rx_drop_l;	/* Rx dropped packets lower */
+	u32	rx_drop_u;	/* Rx dropped packets upper */
+	u32	rx_pkt_l;	/* Rx packets lower */
+	u32	rx_pkt_u;	/* Rx packets upper */
+	u32	rx_undsz_l;	/* Rx undersized packet lower */
+	u32	rx_undsz_u;	/* Rx undersized packet upper */
+	u32	rx_64_l;	/* Rx 64 oct packet lower */
+	u32	rx_64_u;	/* Rx 64 oct packet upper */
+	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
+	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
+	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
+	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
+	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
+	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
+	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
+	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
+	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
+	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
+	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
+	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
+	u32	rx_oversz_l;	/* Rx oversized packet lower */
+	u32	rx_oversz_u;	/* Rx oversized packet upper */
+	u32	rx_jabber_l;	/* Rx Jabber packet lower */
+	u32	rx_jabber_u;	/* Rx Jabber packet upper */
+	u32	rx_frag_l;	/* Rx Fragment packet lower */
+	u32	rx_frag_u;	/* Rx Fragment packet upper */
+	u32	rx_cnp_l;	/* Rx control packet lower */
+	u32	rx_cnp_u;	/* Rx control packet upper */
+	u32	rx_drntp_l;	/* Rx dripped not truncated packet lower */
+	u32	rx_drntp_u;	/* Rx dripped not truncated packet upper */
+	u32	res_1d0[0xc];
+
+	u32	tx_eoct_l;	/* Tx ethernet octests lower */
+	u32	tx_eoct_u;	/* Tx ethernet octests upper */
+	u32	tx_oct_l;	/* Tx octests lower */
+	u32	tx_oct_u;	/* Tx octests upper */
+	u32	res_210[0x2];
+	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
+	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
+	u32	tx_frame_l;	/* Tx frame counter lower */
+	u32	tx_frame_u;	/* Tx frame counter upper */
+	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
+	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
+	u32	tx_vlan_l;	/* Tx VLAN frame lower */
+	u32	tx_vlan_u;	/* Tx VLAN frame upper */
+	u32	tx_frame_err_l;	/* Tx frame error lower */
+	u32	tx_frame_err_u;	/* Tx frame error upper */
+	u32	tx_uni_l;	/* Tx unicast frame lower */
+	u32	tx_uni_u;	/* Tx unicast frame upper */
+	u32	tx_multi_l;	/* Tx multicast frame lower */
+	u32	tx_multi_u;	/* Tx multicast frame upper */
+	u32	tx_brd_l;	/* Tx broadcast frame lower */
+	u32	tx_brd_u;	/* Tx broadcast frame upper */
+	u32	res_258[0x2];
+	u32	tx_pkt_l;	/* Tx packets lower */
+	u32	tx_pkt_u;	/* Tx packets upper */
+	u32	tx_undsz_l;	/* Tx undersized packet lower */
+	u32	tx_undsz_u;	/* Tx undersized packet upper */
+	u32	tx_64_l;	/* Tx 64 oct packet lower */
+	u32	tx_64_u;	/* Tx 64 oct packet upper */
+	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
+	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
+	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
+	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
+	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
+	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
+	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
+	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
+	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
+	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
+	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
+	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
+	u32	res_2a8[0x6];
+	u32	tx_cnp_l;	/* Tx control packet lower */
+	u32	tx_cnp_u;	/* Tx control packet upper */
+	u32	res_2c8[0xe];
+
+	/* Line interface control register */
+	u32 if_mode;		/* interface mode control */
+	u32 if_status;		/* interface status */
+	u32 res_308[0xe];
+
+	/* HiGig/2 Register */
+	u32 hg_config;	/* HiGig2 control and configuration */
+	u32 res_344[0x3];
+	u32 hg_pause_quanta;	/* HiGig2 pause quanta */
+	u32 res_354[0x3];
+	u32 hg_pause_thresh;	/* HiGig2 pause quanta threshold */
+	u32 res_364[0x3];
+	u32 hgrx_pause_status;	/* HiGig2 rx pause quanta status */
+	u32 hg_fifos_status;	/* HiGig2 fifos status */
+	u32 rhm;	/* Rx HiGig2 message counter register */
+	u32 thm;/* Tx HiGig2 message counter register */
+	u32 res_380[0x320];
+};
+
+/* COMMAND_CONFIG - command and configuration register */
+#define MEMAC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
+#define MEMAC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
+#define MEMAC_CMD_CFG_RXTX_EN	(MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
+
+/* HASHTABLE_CTRL - Hashtable control register */
+#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
+#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
+
+/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
+#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
+
+/* IMASK - interrupt mask register */
+#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
+#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
+#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
+#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
+#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
+#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
+#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
+#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
+#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
+#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
+#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
+#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
+#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
+#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
+#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
+#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
+
+#define IMASK_MASK_ALL		0x00000000
+
+/* IEVENT - interrupt event register */
+#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
+#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
+#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
+#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
+#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
+#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
+#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
+#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
+#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
+#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
+#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
+#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
+#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
+#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
+#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
+#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
+
+#define IEVENT_CLEAR_ALL	0xffffffff
+
+/* IF_MODE - Interface Mode Register */
+#define IF_MODE_EN_AUTO	0x00008000 /* 1 - Enable automatic speed selection */
+#define IF_MODE_XGMII	0x00000000 /* 00- XGMII(10) interface mode */
+#define IF_MODE_GMII		0x00000002 /* 10- GMII interface mode */
+#define IF_MODE_MASK	0x00000003 /* mask for mode interface mode */
+#define IF_MODE_RG		0x00000004 /* 1- RGMII */
+#define IF_MODE_RM		0x00000008 /* 1- RGMII */
+
+#define IF_DEFAULT	(IF_GMII)
+
+/* Internal PHY Registers - SGMII */
+#define PHY_SGMII_CR_PHY_RESET      0x8000
+#define PHY_SGMII_CR_RESET_AN       0x0200
+#define PHY_SGMII_CR_DEF_VAL        0x1140
+#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
+#define PHY_SGMII_IF_MODE_AN        0x0002
+#define PHY_SGMII_IF_MODE_SGMII     0x0001
+
+struct memac_mdio_controller {
+	u32	res0[0xc];
+	u32	mdio_stat;	/* MDIO configuration and status */
+	u32	mdio_ctl;	/* MDIO control */
+	u32	mdio_data;	/* MDIO data */
+	u32	mdio_addr;	/* MDIO address */
+};
+
+#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
+#define MDIO_STAT_BSY		(1 << 0)
+#define MDIO_STAT_RD_ER		(1 << 1)
+#define MDIO_STAT_PRE		(1 << 5)
+#define MDIO_STAT_ENC		(1 << 6)
+#define MDIO_STAT_HOLD_15_CLK	(7 << 2)
+
+#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
+#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
+#define MDIO_CTL_PRE_DIS	(1 << 10)
+#define MDIO_CTL_SCAN_EN	(1 << 11)
+#define MDIO_CTL_POST_INC	(1 << 14)
+#define MDIO_CTL_READ		(1 << 15)
+
+#define MDIO_DATA(x)		(x & 0xffff)
+#define MDIO_DATA_BSY		(1 << 31)
+
+struct fsl_enet_mac;
+
+void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
+		int max_rx_len);
+
+#endif
diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h
index 5644044..b75f5b9 100644
--- a/arch/powerpc/include/asm/fsl_portals.h
+++ b/arch/powerpc/include/asm/fsl_portals.h
@@ -32,15 +32,16 @@ enum fsl_dpaa_dev {
 	FSL_HW_PORTAL_FMAN2,
 #endif
 #endif
-#ifdef CONFIG_SYS_DPAA_PME
 	FSL_HW_PORTAL_PME,
-#endif
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 	FSL_HW_PORTAL_RAID_ENGINE,
 #endif
 #ifdef CONFIG_SYS_DPAA_RMAN
 	FSL_HW_PORTAL_RMAN,
 #endif
+#ifdef CONFIG_SYS_DPAA_DCE
+	FSL_HW_PORTAL_DCE,
+#endif
 
 };
 
diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h
index 22525f1..6cd7379 100644
--- a/arch/powerpc/include/asm/fsl_serdes.h
+++ b/arch/powerpc/include/asm/fsl_serdes.h
@@ -37,11 +37,17 @@ enum srds_prtcl {
 	SGMII_FM1_DTSEC3,
 	SGMII_FM1_DTSEC4,
 	SGMII_FM1_DTSEC5,
+	SGMII_FM1_DTSEC6,
+	SGMII_FM1_DTSEC9,
+	SGMII_FM1_DTSEC10,
 	SGMII_FM2_DTSEC1,
 	SGMII_FM2_DTSEC2,
 	SGMII_FM2_DTSEC3,
 	SGMII_FM2_DTSEC4,
 	SGMII_FM2_DTSEC5,
+	SGMII_FM2_DTSEC6,
+	SGMII_FM2_DTSEC9,
+	SGMII_FM2_DTSEC10,
 	SGMII_TSEC1,
 	SGMII_TSEC2,
 	SGMII_TSEC3,
@@ -49,13 +55,49 @@ enum srds_prtcl {
 	XAUI_FM1,
 	XAUI_FM2,
 	AURORA,
+	CPRI1,
+	CPRI2,
+	CPRI3,
+	CPRI4,
+	CPRI5,
+	CPRI6,
+	CPRI7,
+	CPRI8,
+	XAUI_FM1_MAC9,
+	XAUI_FM1_MAC10,
+	XAUI_FM2_MAC9,
+	XAUI_FM2_MAC10,
+	HIGIG_FM1_MAC9,
+	HIGIG_FM1_MAC10,
+	HIGIG_FM2_MAC9,
+	HIGIG_FM2_MAC10,
+	QSGMII_FM1_A,		/* A indicates MACs 1-4 */
+	QSGMII_FM1_B,		/* B indicates MACs 5,6,9,10 */
+	QSGMII_FM2_A,
+	QSGMII_FM2_B,
+	XFI_FM1_MAC9,
+	XFI_FM1_MAC10,
+	XFI_FM2_MAC9,
+	XFI_FM2_MAC10,
+	INTERLAKEN,
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+	FSL_SRDS_3  = 2,
+	FSL_SRDS_4  = 3,
 };
 
 int is_serdes_configured(enum srds_prtcl device);
 void fsl_serdes_init(void);
 
 #ifdef CONFIG_FSL_CORENET
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+#else
 int serdes_get_first_lane(enum srds_prtcl device);
+#endif
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9
 void serdes_reset_rx(enum srds_prtcl device);
 #endif
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 5a5877f..cb3a80b 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -38,7 +38,7 @@
 typedef	struct	global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	bus_clk;
 #if defined(CONFIG_8xx)
@@ -63,6 +63,8 @@ typedef	struct	global_data {
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
+#elif defined(CONFIG_MPC8309)
+	u32 usbdr_clk;
 #endif
 #if defined (CONFIG_MPC834x)
 	u32 usbmph_clk;
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 2ba502a..679832c 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,12 +73,19 @@ typedef struct sysconf83xx {
 	u32 obir;		/* Output Buffer Impedance Register */
 	u8 res8[0xC];
 	u32 pecr1;		/* PCI Express control register 1 */
-#ifdef CONFIG_MPC8308
-	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
+#if defined(CONFIG_MPC830x)
+	u32 sdhccr;		/* eSDHC Control Registers for MPC830x */
 #else
 	u32 pecr2;		/* PCI Express control register 2 */
 #endif
+#if defined(CONFIG_MPC8309)
+	u32 can_dbg_ctrl;
+	u32 res9a;
+	u32 gpr1;
+	u8 res9b[0xAC];
+#else
 	u8 res9[0xB8];
+#endif
 } sysconf83xx_t;
 
 /*
@@ -708,7 +715,11 @@ typedef struct serdes83xx {
  * On Chip ROM
  */
 typedef struct rom83xx {
+#if defined(CONFIG_MPC8309)
+	u8 mem[0x8000];
+#else
 	u8 mem[0x10000];
+#endif
 } rom83xx_t;
 
 /*
@@ -972,6 +983,56 @@ typedef struct immap {
 	u8			res8[0xC0000];
 	u8			qe[0x100000];	/* QE block */
 } immap_t;
+#elif defined(CONFIG_MPC8309)
+typedef struct immap {
+	sysconf83xx_t		sysconf;	/* System configuration */
+	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
+	rtclk83xx_t		rtc;		/* Real Time Clock Module Registers */
+	rtclk83xx_t		pit;		/* Periodic Interval Timer */
+	gtm83xx_t		gtm[2];		/* Global Timers Module */
+	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
+	arbiter83xx_t		arbiter;	/* System Arbiter Registers */
+	reset83xx_t		reset;		/* Reset Module */
+	clk83xx_t		clk;		/* System Clock Module */
+	pmc83xx_t		pmc;		/* Power Management Control Module */
+	gpio83xx_t		gpio[2];	/* General purpose I/O module */
+	u8			res0[0x500];	/* res0 1.25 KBytes added for 8309 */
+	qepi83xx_t		qepi;		/* QE Ports Interrupts Registers */
+	qepio83xx_t		qepio;		/* QE Parallel I/O ports */
+	u8			res1[0x800];
+	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
+	fsl_i2c_t		i2c[2];		/* I2C Controllers */
+	u8			res2[0x1300];
+	duart83xx_t		duart[2];	/* DUART */
+	u8			res3[0x200];
+	duart83xx_t		duart1[2];	/* DUART */
+	u8			res4[0x500];
+	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
+	u8			res5[0x1000];
+	u8			spi[0x100];
+	u8			res6[0xf00];
+	dma83xx_t		dma;		/* DMA */
+	pciconf83xx_t		pci_conf[1];	/* PCI Configuration Registers */
+	u8			res7[0x80];
+	ios83xx_t		ios;		/* Sequencer (IOS) */
+	pcictrl83xx_t		pci_ctrl[1];	/* PCI Control & Status Registers */
+	u8			res8[0x13A00];
+	u8			can1[0x1000];	/* Flexcan 1 */
+	u8			can2[0x1000];	/* Flexcan 2 */
+	u8			res9[0x5000];
+	usb83xx_t		usb;
+	u8			res10[0x5000];
+	u8			can3[0x1000];	/* Flexcan 3 */
+	u8			can4[0x1000];	/* Flexcan 4 */
+	u8			res11[0x1000];
+	u8			dma1[0x2000];	/* DMA */
+	sdhc83xx_t		sdhc;		/* SDHC Controller */
+	u8			res12[0xC1000];
+	rom83xx_t		rom;		/* On Chip ROM */
+	u8			res13[0x8000];
+	u8			qe[0x100000];	/* QE block */
+	u8			res14[0xE00000];/* Added for 8309 */
+} immap_t;
 #endif
 
 #define CONFIG_SYS_MPC83xx_DDR_OFFSET	(0x2000)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7de33a7..969f726 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -296,7 +296,9 @@ typedef struct ccsr_pcix {
 	u32	cfg_addr;	/* PCIX Configuration Addr */
 	u32	cfg_data;	/* PCIX Configuration Data */
 	u32	int_ack;	/* PCIX IRQ Acknowledge */
-	u8	res1[3060];
+	u8	res000c[52];
+	u32	liodn_base;	/* PCIX LIODN base register */
+	u8	res0044[3004];
 	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
 	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
 	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
@@ -1687,6 +1689,77 @@ typedef struct ccsr_gur {
 	u32	alt_pmuxcr;	/* Alt function signal multiplex control */
 	u8	res6[12];
 	u32	devdisr;	/* Device disable control */
+	u32	devdisr2;	/* Device disable control 2 */
+	u32	devdisr3;	/* Device disable control 3 */
+	u32	devdisr4;	/* Device disable control 4 */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+	u32	devdisr5;	/* Device disable control 5 */
+#define FSL_CORENET_DEVDISR_PBL	0x80000000
+#define FSL_CORENET_DEVDISR_PMAN	0x40000000
+#define FSL_CORENET_DEVDISR_ESDHC	0x20000000
+#define FSL_CORENET_DEVDISR_DMA1	0x00800000
+#define FSL_CORENET_DEVDISR_DMA2	0x00400000
+#define FSL_CORENET_DEVDISR_USB1	0x00080000
+#define FSL_CORENET_DEVDISR_USB2	0x00040000
+#define FSL_CORENET_DEVDISR_SATA1	0x00008000
+#define FSL_CORENET_DEVDISR_SATA2	0x00004000
+#define FSL_CORENET_DEVDISR_PME	0x00000800
+#define FSL_CORENET_DEVDISR_SEC	0x00000200
+#define FSL_CORENET_DEVDISR_RMU	0x00000080
+#define FSL_CORENET_DEVDISR_DCE	0x00000040
+#define FSL_CORENET_DEVDISR2_DTSEC1_1	0x80000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_2	0x40000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_3	0x20000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_4	0x10000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_5	0x08000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_6	0x04000000
+#define FSL_CORENET_DEVDISR2_DTSEC1_9	0x00800000
+#define FSL_CORENET_DEVDISR2_DTSEC1_10	0x00400000
+#define FSL_CORENET_DEVDISR2_10GEC1_1	0x00800000
+#define FSL_CORENET_DEVDISR2_10GEC1_2	0x00400000
+#define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00080000
+#define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00040000
+#define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00020000
+#define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00010000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00008000
+#define FSL_CORENET_DEVDISR2_DTSEC2_6	0x00004000
+#define FSL_CORENET_DEVDISR2_DTSEC2_9	0x00000800
+#define FSL_CORENET_DEVDISR2_DTSEC2_10	0x00000400
+#define FSL_CORENET_DEVDISR2_10GEC2_1	0x00000800
+#define FSL_CORENET_DEVDISR2_10GEC2_2	0x00000400
+#define FSL_CORENET_DEVDISR2_FM1	0x00000080
+#define FSL_CORENET_DEVDISR2_FM2	0x00000040
+#define FSL_CORENET_DEVDISR2_CPRI	0x00000008
+#define FSL_CORENET_DEVDISR3_PCIE1	0x80000000
+#define FSL_CORENET_DEVDISR3_PCIE2	0x40000000
+#define FSL_CORENET_DEVDISR3_PCIE3	0x20000000
+#define FSL_CORENET_DEVDISR3_PCIE4	0x10000000
+#define FSL_CORENET_DEVDISR3_SRIO1	0x08000000
+#define FSL_CORENET_DEVDISR3_SRIO2	0x04000000
+#define FSL_CORENET_DEVDISR3_QMAN	0x00080000
+#define FSL_CORENET_DEVDISR3_BMAN	0x00040000
+#define FSL_CORENET_DEVDISR3_LA1	0x00008000
+#define FSL_CORENET_DEVDISR3_MAPLE1	0x00000800
+#define FSL_CORENET_DEVDISR3_MAPLE2	0x00000400
+#define FSL_CORENET_DEVDISR3_MAPLE3	0x00000200
+#define FSL_CORENET_DEVDISR4_I2C1	0x80000000
+#define FSL_CORENET_DEVDISR4_I2C2	0x40000000
+#define FSL_CORENET_DEVDISR4_DUART1	0x20000000
+#define FSL_CORENET_DEVDISR4_DUART2	0x10000000
+#define FSL_CORENET_DEVDISR4_ESPI	0x08000000
+#define FSL_CORENET_DEVDISR5_DDR1	0x80000000
+#define FSL_CORENET_DEVDISR5_DDR2	0x40000000
+#define FSL_CORENET_DEVDISR5_DDR3	0x20000000
+#define FSL_CORENET_DEVDISR5_CPC1	0x08000000
+#define FSL_CORENET_DEVDISR5_CPC2	0x04000000
+#define FSL_CORENET_DEVDISR5_CPC3	0x02000000
+#define FSL_CORENET_DEVDISR5_IFC	0x00800000
+#define FSL_CORENET_DEVDISR5_GPIO	0x00400000
+#define FSL_CORENET_DEVDISR5_DBG	0x00200000
+#define FSL_CORENET_DEVDISR5_NAL	0x00100000
+#define FSL_CORENET_DEVDISR5_TIMERS	0x00020000
+#define FSL_CORENET_NUM_DEVDISR		5
+#else
 #define FSL_CORENET_DEVDISR_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR_PCIE3	0x20000000
@@ -1712,7 +1785,6 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR_I2C2	0x00000010
 #define FSL_CORENET_DEVDISR_DUART1	0x00000002
 #define FSL_CORENET_DEVDISR_DUART2	0x00000001
-	u32	devdisr2;	/* Device disable control 2 */
 #define FSL_CORENET_DEVDISR2_PME	0x80000000
 #define FSL_CORENET_DEVDISR2_SEC	0x40000000
 #define FSL_CORENET_DEVDISR2_QMBM	0x08000000
@@ -1731,8 +1803,8 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00000800
 #define FSL_CORENET_NUM_DEVDISR		2
-	u8	res7[8];
 	u32	powmgtcsr;	/* Power management status & control */
+#endif
 	u8	res8[12];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
 	u32	coredisrl;	/* lower portion for support of 64 cores */
@@ -1755,13 +1827,47 @@ typedef struct ccsr_gur {
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
+
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL		0x0000f800
+#define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
+#define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
+#elif defined(CONFIG_PPC_B4860)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
+#endif
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1	0x00200000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2	0x00100000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1	0x00080000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
+#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
+#define FSL_CORENET_RCWSR5_SRDS2_EN		0x00001000
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
@@ -1784,6 +1890,24 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
 #endif
+#if defined(CONFIG_PPC_P5040)
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
+#define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
+#define FSL_CORENET_RCWSR11_EC2                 0x00180000 /* bits 363..364 */
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
+#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
+#endif
+#if defined(CONFIG_PPC_T4240)
+#define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
+#define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
+#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
+#endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
@@ -1880,34 +2004,38 @@ typedef struct ccsr_gur {
 #define rmuliodnr rio1maintliodnr
 
 typedef struct ccsr_clk {
-	u32	clkc0csr;	/* Core 0 Clock control/status */
+	u32	clkc0csr;	/* 0x000 Core 0 Clock control/status */
 	u8	res1[0x1c];
-	u32	clkc1csr;	/* Core 1 Clock control/status */
+	u32	clkc1csr;	/* 0x020 Core 1 Clock control/status */
 	u8	res2[0x1c];
-	u32	clkc2csr;	/* Core 2 Clock control/status */
+	u32	clkc2csr;	/* 0x040 Core 2 Clock control/status */
 	u8	res3[0x1c];
-	u32	clkc3csr;	/* Core 3 Clock control/status */
+	u32	clkc3csr;	/* 0x060 Core 3 Clock control/status */
 	u8	res4[0x1c];
-	u32	clkc4csr;	/* Core 4 Clock control/status */
+	u32	clkc4csr;	/* 0x080 Core 4 Clock control/status */
 	u8	res5[0x1c];
-	u32	clkc5csr;	/* Core 5 Clock control/status */
+	u32	clkc5csr;	/* 0x0a0 Core 5 Clock control/status */
 	u8	res6[0x1c];
-	u32	clkc6csr;	/* Core 6 Clock control/status */
+	u32	clkc6csr;	/* 0x0c0 Core 6 Clock control/status */
 	u8	res7[0x1c];
-	u32	clkc7csr;	/* Core 7 Clock control/status */
+	u32	clkc7csr;	/* 0x0e0 Core 7 Clock control/status */
 	u8	res8[0x71c];
-	u32	pllc1gsr;	/* Cluster PLL 1 General Status */
+	u32	pllc1gsr;	/* 0x800 Cluster PLL 1 General Status */
 	u8	res10[0x1c];
-	u32	pllc2gsr;	/* Cluster PLL 2 General Status */
+	u32	pllc2gsr;	/* 0x820 Cluster PLL 2 General Status */
 	u8	res11[0x1c];
-	u32	pllc3gsr;	/* Cluster PLL 3 General Status */
+	u32	pllc3gsr;	/* 0x840 Cluster PLL 3 General Status */
 	u8	res12[0x1c];
-	u32	pllc4gsr;	/* Cluster PLL 4 General Status */
-	u8	res13[0x39c];
-	u32	pllpgsr;	/* Platform PLL General Status */
+	u32	pllc4gsr;	/* 0x860 Cluster PLL 4 General Status */
+	u8	res13[0x1c];
+	u32	pllc5gsr;	/* 0x880 Cluster PLL 5 General Status */
 	u8	res14[0x1c];
-	u32	plldgsr;	/* DDR PLL General Status */
-	u8	res15[0x3dc];
+	u32	pllc6gsr;	/* 0x8a0 Cluster PLL 6 General Status */
+	u8	res15[0x35c];
+	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
+	u8	res16[0x1c];
+	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
+	u8	res17[0x3dc];
 } ccsr_clk_t;
 
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
@@ -2384,6 +2512,78 @@ typedef struct ccsr_gur {
 
 #define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define MAX_SERDES 4
+#define SRDS_MAX_LANES 8
+#define SRDS_MAX_BANK 2
+typedef struct serdes_corenet {
+	struct {
+		u32	rstctl;	/* Reset Control Register */
+#define SRDS_RSTCTL_RST		0x80000000
+#define SRDS_RSTCTL_RSTDONE	0x40000000
+#define SRDS_RSTCTL_RSTERR	0x20000000
+#define SRDS_RSTCTL_SWRST	0x10000000
+#define SRDS_RSTCTL_SDPD	0x00000020
+		u32	pllcr0; /* PLL Control Register 0 */
+#define SRDS_PLLCR0_POFF		0x80000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
+#define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
+#define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
+#define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
+#define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
+#define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
+#define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
+#define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
+#define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
+#define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
+		u32	pllcr1; /* PLL Control Register 1 */
+#define SRDS_PLLCR1_PLL_BWSEL	0x08000000
+		u32	res_0c;	/* 0x00c */
+		u32	pllcr3;
+		u32	pllcr4;
+		u8	res_18[0x20-0x18];
+	} bank[2];
+	u8	res_40[0x90-0x40];
+	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
+	u8	res_94[0xa0-0x94];
+	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
+	u8	res_a4[0xb0-0xa4];
+	u32	srdsgr0;	/* 0xb0 General Register 0 */
+	u8	res_b4[0xe0-0xb4];
+	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
+	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
+	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
+	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
+	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
+	u8	res_f4[0x100-0xf4];
+	struct {
+		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
+		u8	res_104[0x120-0x104];
+	} srdslnpssr[8];
+	u8	res_200[0x800-0x200];
+	struct {
+		u32	gcr0;	/* 0x800 General Control Register 0 */
+		u32	gcr1;	/* 0x804 General Control Register 1 */
+		u32	gcr2;	/* 0x808 General Control Register 2 */
+		u32	res_80c;
+		u32	recr0;	/* 0x810 Receive Equalization Control */
+		u32	res_814;
+		u32	tecr0;	/* 0x818 Transmit Equalization Control */
+		u32	res_81c;
+		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
+		u8	res_824[0x840-0x824];
+	} lane[8];	/* Lane A, B, C, D, E, F, G, H */
+	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
+} serdes_corenet_t;
+
+#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+
+#define SRDS_MAX_LANES		18
+#define SRDS_MAX_BANK		3
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
@@ -2392,11 +2592,13 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
-#define SRDS_PLLCR0_RFCK_SEL_MASK	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
+#define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
+#define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
@@ -2421,6 +2623,7 @@ typedef struct serdes_corenet {
 		u32	gcr0;	/* General Control Register 0 */
 #define SRDS_GCR0_RRST			0x00400000
 #define SRDS_GCR0_1STLANE		0x00010000
+#define SRDS_GCR0_UOTHL			0x00100000
 		u32	gcr1;	/* General Control Register 1 */
 #define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
 #define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
@@ -2440,6 +2643,7 @@ typedef struct serdes_corenet {
 	} lane[24];
 	u32 res6[384];
 } serdes_corenet_t;
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 enum {
 	FSL_SRDS_B1_LANE_A = 0,
@@ -2482,8 +2686,8 @@ typedef struct ccsr_sec {
 	struct {
 		u32	ms;	/* DECO LIODN Register, MS */
 		u32	ls;	/* DECO LIODN Register, LS */
-	} decoliodnr[5];
-	u8	res4[0x58];
+	} decoliodnr[8];
+	u8	res4[0x40];
 	u32	dar;		/* DECO Avail Register */
 	u32	drr;		/* DECO Reset Register */
 	u8	res5[0xe78];
@@ -2523,13 +2727,16 @@ typedef struct ccsr_sec {
 #endif
 
 typedef struct ccsr_qman {
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	u8	res0[0x200];
+#else
 	struct {
 		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
 		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
 		u32	res;
 		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
 	} qcsp[32];
-
+#endif
 	/* Not actually reserved, but irrelevant to u-boot */
 	u8	res[0xbf8 - 0x200];
 	u32	ip_rev_1;
@@ -2554,6 +2761,14 @@ typedef struct ccsr_qman {
 	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
 	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
 	u8	res7[0x2e8];
+#ifdef CONFIG_SYS_FSL_QMAN_V3
+	struct {
+		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
+		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
+		u32	res;
+		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
+	} qcsp[50];
+#endif
 } ccsr_qman_t;
 
 typedef struct ccsr_bman {
@@ -2617,14 +2832,48 @@ struct ccsr_rman {
 };
 #endif
 
+#ifdef CONFIG_SYS_PMAN
+struct ccsr_pman {
+	u8	res_00[0x40];
+	u32	poes1;		/* PMAN Operation Error Status Register 1 */
+	u32	poes2;		/* PMAN Operation Error Status Register 2 */
+	u32	poeah;		/* PMAN Operation Error Address High */
+	u32	poeal;		/* PMAN Operation Error Address Low */
+	u8	res_50[0x50];
+	u32	pr1;		/* PMAN Revision Register 1 */
+	u32	pr2;		/* PMAN Revision Register 2 */
+	u8	res_a8[0x8];
+	u32	pcap;		/* PMAN Capabilities Register */
+	u8	res_b4[0xc];
+	u32	pc1;		/* PMAN Control Register 1 */
+	u32	pc2;		/* PMAN Control Register 2 */
+	u32	pc3;		/* PMAN Control Register 3 */
+	u32	pc4;		/* PMAN Control Register 4 */
+	u32	pc5;		/* PMAN Control Register 5 */
+	u32	pc6;		/* PMAN Control Register 6 */
+	u8	res_d8[0x8];
+	u32	ppa1;		/* PMAN Prefetch Attributes Register 1 */
+	u32	ppa2;		/* PMAN Prefetch Attributes Register 2 */
+	u8	res_e8[0x8];
+	u32	pics;		/* PMAN Interrupt Control and Status */
+	u8	res_f4[0xf0c];
+};
+#endif
+
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
+#ifdef CONFIG_SYS_PMAN
+#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
+#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
+#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
+#endif
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET		0x9000
 #define CONFIG_SYS_MPC85xx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
+#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
@@ -2635,10 +2884,17 @@ struct ccsr_rman {
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
+#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
+#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
+#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
+#else
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
+#endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET		CONFIG_SYS_MPC85xx_USB1_OFFSET
@@ -2657,7 +2913,9 @@ struct ccsr_rman {
 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
+#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
+#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
 #define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
@@ -2665,7 +2923,10 @@ struct ccsr_rman {
 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
+#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
+#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
+#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CONFIG_SYS_MPC85xx_DDR_OFFSET		0x2000
@@ -2775,6 +3036,8 @@ struct ccsr_rman {
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
@@ -2808,4 +3071,62 @@ struct ccsr_rman {
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+struct ccsr_cluster_l2 {
+	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
+	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
+	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
+	u8  res_0c[500];/* 0x00c - 0x1ff */
+	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
+	u8  res_204[4];
+	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
+	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
+	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
+	u8  res_214[4];
+	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
+	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
+	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
+	u8  res_224[4];
+	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
+	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
+	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
+	u8  res_234[4];
+	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
+	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
+	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
+	u8  res244[4];
+	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
+	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
+	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
+	u8  res_254[4];
+	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
+	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
+	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
+	u8  res_264[4];
+	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
+	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
+	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
+	u8  res274[4];
+	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
+	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
+	u8  res_280[0xb80]; /* 0x280 - 0xdff */
+	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
+	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
+	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
+	u8  res_e0c[20];	/* 0xe0c - 0x01f */
+	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
+	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
+	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
+	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
+	u32 l2errdet;	/* 0xe40 L2 cache error detect */
+	u32 l2errdis;	/* 0xe44 L2 cache error disable */
+	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
+	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
+	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
+	u32 l2erraddr;	/* 0xe54 L2 cache error address */
+	u32 l2errctl;	/* 0xe58 L2 cache error control */
+};
+#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #endif /*__IMMAP_85xx__*/
diff --git a/arch/powerpc/include/asm/immap_qe.h b/arch/powerpc/include/asm/immap_qe.h
index 9be9dca..f0b989a 100644
--- a/arch/powerpc/include/asm/immap_qe.h
+++ b/arch/powerpc/include/asm/immap_qe.h
@@ -20,7 +20,7 @@
 #define QE_MURAM_SIZE		0xc000UL
 #define MAX_QE_RISC		2
 #define QE_NUM_OF_SNUM		28
-#elif defined(CONFIG_MPC832x)
+#elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
 #define QE_MURAM_SIZE		0x4000UL
 #define MAX_QE_RISC		1
 #define QE_NUM_OF_SNUM		28
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index 9e20861..1f12c29 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -127,7 +127,6 @@ static inline void isync(void)
 /*
  * Non ordered and non-swapping "raw" accessors
  */
-#define __iomem
 #define PCI_FIX_ADDR(addr)	(addr)
 
 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
diff --git a/arch/powerpc/include/asm/mp.h b/arch/powerpc/include/asm/mp.h
index fe490ba..9188ede 100644
--- a/arch/powerpc/include/asm/mp.h
+++ b/arch/powerpc/include/asm/mp.h
@@ -25,7 +25,7 @@
 
 void setup_mp(void);
 void cpu_mp_lmb_reserve(struct lmb *lmb);
-u32 determine_mp_bootpg(void);
+u32 determine_mp_bootpg(unsigned int *pagesize);
 int is_core_disabled(int nr);
 
 #ifdef CONFIG_E6500
diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h
index 5a608a5..2aed514 100644
--- a/arch/powerpc/include/asm/mpc85xx_gpio.h
+++ b/arch/powerpc/include/asm/mpc85xx_gpio.h
@@ -98,7 +98,10 @@ static inline int gpio_direction_input(unsigned gpio)
 
 static inline int gpio_direction_output(unsigned gpio, int value)
 {
-	mpc85xx_gpio_set_low(1U << gpio);
+	if (value)
+		mpc85xx_gpio_set_high(1U << gpio);
+	else
+		mpc85xx_gpio_set_low(1U << gpio);
 	return 0;
 }
 
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index d570d79..e35d9b6 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -1404,7 +1404,7 @@ struct sdram_timing {
 /*
  * Prototypes
  */
-inline void ppc4xx_ibm_ddr2_register_dump(void);
+void ppc4xx_ibm_ddr2_register_dump(void);
 u32 mfdcr_any(u32);
 void mtdcr_any(u32, u32);
 u32 ddr_wrdtr(u32);
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 36695e2..7aa3231 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1095,6 +1095,17 @@
 #define SVR_P4080	0x820000
 #define SVR_P5010	0x822100
 #define SVR_P5020	0x822000
+#define SVR_P5021	0X820500
+#define SVR_P5040	0x820400
+#define SVR_T4240	0x824000
+#define SVR_T4120	0x824001
+#define SVR_B4860	0X868000
+#define SVR_G4860	0x868001
+#define SVR_G4060	0x868003
+#define SVR_B4440	0x868100
+#define SVR_G4440	0x868101
+#define SVR_B4420	0x868102
+#define SVR_B4220	0x868103
 
 #define SVR_8610	0x80A000
 #define SVR_8641	0x809000
diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h
index b2fa2b5..7229a98 100644
--- a/arch/powerpc/include/asm/u-boot.h
+++ b/arch/powerpc/include/asm/u-boot.h
@@ -81,7 +81,7 @@ typedef struct bd_info {
 	unsigned long	bi_ipbfreq;	/* IPB Bus Freq, in MHz */
 	unsigned long	bi_pcifreq;	/* PCI Bus Freq, in MHz */
 #endif
-	unsigned long	bi_baudrate;	/* Console Baudrate */
+	unsigned int	bi_baudrate;	/* Console Baudrate */
 #if defined(CONFIG_405)   || \
     defined(CONFIG_405GP) || \
     defined(CONFIG_405CR) || \
diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile
index 965f9ea..808021c 100644
--- a/arch/powerpc/lib/Makefile
+++ b/arch/powerpc/lib/Makefile
@@ -50,6 +50,7 @@ COBJS-y	+= cache.o
 COBJS-y	+= extable.o
 COBJS-y	+= interrupts.o
 COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
+COBJS-${CONFIG_CMD_IDE} += ide.o
 COBJS-y	+= time.o
 
 # Workaround for local bus unaligned access problems
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index b860141..1b051e1 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -163,7 +163,7 @@ static int init_baudrate(void)
 
 /***********************************************************************/
 
-void __board_add_ram_info(int use_default)
+static void __board_add_ram_info(int use_default)
 {
 	/* please define platform specific board_add_ram_info() */
 }
@@ -171,7 +171,7 @@ void __board_add_ram_info(int use_default)
 void board_add_ram_info(int)
 	__attribute__ ((weak, alias("__board_add_ram_info")));
 
-int __board_flash_wp_on(void)
+static int __board_flash_wp_on(void)
 {
 	/*
 	 * Most flashes can't be detected when write protection is enabled,
@@ -184,7 +184,7 @@ int __board_flash_wp_on(void)
 int board_flash_wp_on(void)
 	__attribute__ ((weak, alias("__board_flash_wp_on")));
 
-void __cpu_secondary_init_r(void)
+static void __cpu_secondary_init_r(void)
 {
 }
 
@@ -262,7 +262,7 @@ static int init_func_watchdog_reset(void)
  * Initialization sequence
  */
 
-init_fnc_t *init_sequence[] = {
+static init_fnc_t *init_sequence[] = {
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	probecpu,
 #endif
@@ -345,7 +345,7 @@ ulong get_effective_memsize(void)
 #endif
 }
 
-int __fixup_cpu(void)
+static int __fixup_cpu(void)
 {
 	return 0;
 }
@@ -402,7 +402,7 @@ void board_init_f(ulong bootflag)
 
 #ifdef CONFIG_POST
 	post_bootmode_init();
-	post_run(NULL, POST_ROM | post_bootmode_get(0));
+	post_run(NULL, POST_ROM | post_bootmode_get(NULL));
 #endif
 
 	WATCHDOG_RESET();
@@ -440,8 +440,8 @@ void board_init_f(ulong bootflag)
 	 * We need to make sure the location we intend to put secondary core
 	 * boot code is reserved and not used by any part of u-boot
 	 */
-	if (addr > determine_mp_bootpg()) {
-		addr = determine_mp_bootpg();
+	if (addr > determine_mp_bootpg(NULL)) {
+		addr = determine_mp_bootpg(NULL);
 		debug("Reserving MP boot page to %08lx\n", addr);
 	}
 #endif
diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c
index 53dc4df..ac5bd6d 100644
--- a/arch/powerpc/lib/bootm.c
+++ b/arch/powerpc/lib/bootm.c
@@ -326,7 +326,7 @@ static int boot_body_linux(bootm_headers_t *images)
 	return 0;
 }
 
-__attribute__((noinline))
+noinline
 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
 {
 	int	ret;
diff --git a/arch/powerpc/lib/extable.c b/arch/powerpc/lib/extable.c
index 7408d5c..60983ae 100644
--- a/arch/powerpc/lib/extable.c
+++ b/arch/powerpc/lib/extable.c
@@ -63,8 +63,6 @@ search_one_table(const struct exception_table_entry *first,
 	return 0;
 }
 
-int	ex_tab_message = 1;
-
 unsigned long
 search_exception_table(unsigned long addr)
 {
@@ -74,8 +72,7 @@ search_exception_table(unsigned long addr)
 	ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr);
 	/* if the serial port does not hang in exception, printf can be used */
 #if !defined(CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION)
-	if (ex_tab_message)
-		debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
+	debug("Bus Fault @ 0x%08lx, fixup 0x%08lx\n", addr, ret);
 #endif
 	if (ret) return ret;
 
diff --git a/arch/powerpc/lib/ide.c b/arch/powerpc/lib/ide.c
new file mode 100644
index 0000000..139a94a
--- /dev/null
+++ b/arch/powerpc/lib/ide.c
@@ -0,0 +1,201 @@
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Code taken from cmd_ide.c */
+#include <common.h>
+#include <ata.h>
+#include "ide.h"
+
+#ifdef CONFIG_IDE_8xx_DIRECT
+#include <mpc8xx.h>
+#include <pcmcia.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
+ * 70	   165	    30	   PIO-Mode 0, [ns]
+ *  4	     9	     2		       [Cycles]
+ * 50	   125	    20	   PIO-Mode 1, [ns]
+ *  3	     7	     2		       [Cycles]
+ * 30	   100	    15	   PIO-Mode 2, [ns]
+ *  2	     6	     1		       [Cycles]
+ * 30	    80	    10	   PIO-Mode 3, [ns]
+ *  2	     5	     1		       [Cycles]
+ * 25	    70	    10	   PIO-Mode 4, [ns]
+ *  2	     4	     1		       [Cycles]
+ */
+
+static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = {
+    /*  Setup  Length  Hold  */
+	{ 70,	165,	30 },		/* PIO-Mode 0, [ns]	*/
+	{ 50,	125,	20 },		/* PIO-Mode 1, [ns]	*/
+	{ 30,	101,	15 },		/* PIO-Mode 2, [ns]	*/
+	{ 30,	 80,	10 },		/* PIO-Mode 3, [ns]	*/
+	{ 25,	 70,	10 },		/* PIO-Mode 4, [ns]	*/
+};
+
+static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1];
+
+#ifndef CONFIG_SYS_PIO_MODE
+#define CONFIG_SYS_PIO_MODE	0	/* use a relaxed default */
+#endif
+static int pio_mode = CONFIG_SYS_PIO_MODE;
+
+/* Make clock cycles and always round up */
+
+#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U)
+
+static void set_pcmcia_timing(int pmode)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+	ulong timings;
+
+	debug("Set timing for PIO Mode %d\n", pmode);
+
+	timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold)
+		| PCMCIA_SST(pio_config_clk[pmode].t_setup)
+		| PCMCIA_SL(pio_config_clk[pmode].t_length);
+
+	/*
+	 * IDE 0
+	 */
+	pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0;
+#if (CONFIG_SYS_PCMCIA_POR0 != 0)
+	pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings;
+#else
+	pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0;
+#endif
+	debug("PBR0: %08x  POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0);
+
+	pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1;
+#if (CONFIG_SYS_PCMCIA_POR1 != 0)
+	pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings;
+#else
+	pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1;
+#endif
+	debug("PBR1: %08x  POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1);
+
+	pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2;
+#if (CONFIG_SYS_PCMCIA_POR2 != 0)
+	pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings;
+#else
+	pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2;
+#endif
+	debug("PBR2: %08x  POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2);
+
+	pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3;
+#if (CONFIG_SYS_PCMCIA_POR3 != 0)
+	pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings;
+#else
+	pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3;
+#endif
+	debug("PBR3: %08x  POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3);
+
+	/*
+	 * IDE 1
+	 */
+	pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4;
+#if (CONFIG_SYS_PCMCIA_POR4 != 0)
+	pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings;
+#else
+	pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4;
+#endif
+	debug("PBR4: %08x  POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4);
+
+	pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5;
+#if (CONFIG_SYS_PCMCIA_POR5 != 0)
+	pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings;
+#else
+	pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5;
+#endif
+	debug("PBR5: %08x  POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5);
+
+	pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6;
+#if (CONFIG_SYS_PCMCIA_POR6 != 0)
+	pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings;
+#else
+	pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6;
+#endif
+	debug("PBR6: %08x  POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6);
+
+	pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7;
+#if (CONFIG_SYS_PCMCIA_POR7 != 0)
+	pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings;
+#else
+	pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7;
+#endif
+	debug("PBR7: %08x  POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7);
+
+}
+
+int ide_preinit(void)
+{
+	int i;
+	/* Initialize PIO timing tables */
+	for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) {
+		pio_config_clk[i].t_setup =
+			PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk);
+		pio_config_clk[i].t_length =
+			PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk);
+		pio_config_clk[i].t_hold =
+			PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk);
+		debug("PIO Mode %d: setup=%2d ns/%d clk" "  len=%3d ns/%d clk"
+			"  hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup,
+			pio_config_clk[i].t_setup, pio_config_ns[i].t_length,
+			pio_config_clk[i].t_length, pio_config_ns[i].t_hold,
+			pio_config_clk[i].t_hold);
+	}
+
+	return 0;
+}
+
+int ide_init_postreset(void)
+{
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+	volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+
+	/* PCMCIA / IDE initialization for common mem space */
+	pcmp->pcmc_pgcrb = 0;
+
+	/* start in PIO mode 0 - most relaxed timings */
+	pio_mode = 0;
+	set_pcmcia_timing(pio_mode);
+	return 0;
+}
+#endif /* CONFIG_IDE_8xx_DIRECT */
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+int ide_preinit(void)
+{
+	ide_devices_found = 0;
+	/* initialize the PCMCIA IDE adapter card */
+	pcmcia_on();
+	if (!ide_devices_found)
+		return 1;
+	udelay(1000000);/* 1 s */
+	return 0;
+}
+#endif
diff --git a/arch/arm/include/asm/arch-lpc2292/hardware.h b/arch/powerpc/lib/ide.h
index 5e227e3..9e80702 100644
--- a/arch/arm/include/asm/arch-lpc2292/hardware.h
+++ b/arch/powerpc/lib/ide.h
@@ -1,9 +1,6 @@
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
 /*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -24,10 +21,11 @@
  * MA 02111-1307 USA
  */
 
-#if defined(CONFIG_LPC2292)
-#include <asm/arch-lpc2292/lpc2292_registers.h>
-#else
-#error No hardware file defined for this configuration
-#endif
+#ifndef _MPC8XX_IDE_H_
+#define _MPC8XX_IDE_H_ 1
 
-#endif /* __ASM_ARCH_HARDWARE_H */
+#ifdef CONFIG_IDE_8xx_PCCARD
+int pcmcia_on(void);
+extern int ide_devices_found;
+#endif
+#endif
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index 9960138..1b781eb 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -24,9 +24,11 @@
 
 SECTIONS
 {
-	__u_boot_cmd_start = .;
-	_u_boot_cmd : { *(.u_boot_cmd) }
-	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	__u_boot_sandbox_option_start = .;
 	_u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
diff --git a/arch/sandbox/include/asm/global_data.h b/arch/sandbox/include/asm/global_data.h
index 581fd2f..78a751d 100644
--- a/arch/sandbox/include/asm/global_data.h
+++ b/arch/sandbox/include/asm/global_data.h
@@ -36,7 +36,7 @@
 typedef	struct global_data {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 	unsigned long	env_addr;	/* Address  of Environment struct */
 	unsigned long	env_valid;	/* Checksum of Environment valid? */
diff --git a/arch/sh/cpu/sh2/u-boot.lds b/arch/sh/cpu/sh2/u-boot.lds
index b86a822..17f8091 100644
--- a/arch/sh/cpu/sh2/u-boot.lds
+++ b/arch/sh/cpu/sh2/u-boot.lds
@@ -72,13 +72,10 @@ SECTIONS
 	}
 	PROVIDE (_egot = .);
 
-	PROVIDE (__u_boot_cmd_start = .);
-	.u_boot_cmd :
-	{
-		*(.u_boot_cmd)
-		. = ALIGN(4);
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
-	PROVIDE (__u_boot_cmd_end = .);
 
 	PROVIDE (reloc_dst_end = .);
 
diff --git a/arch/sh/cpu/sh3/u-boot.lds b/arch/sh/cpu/sh3/u-boot.lds
index 9bf8503..c831961 100644
--- a/arch/sh/cpu/sh3/u-boot.lds
+++ b/arch/sh/cpu/sh3/u-boot.lds
@@ -78,13 +78,10 @@ SECTIONS
 	}
 	PROVIDE (_egot = .);
 
-	PROVIDE (__u_boot_cmd_start = .);
-	.u_boot_cmd :
-	{
-		*(.u_boot_cmd)
-		. = ALIGN(4);
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
-	PROVIDE (__u_boot_cmd_end = .);
 
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
diff --git a/arch/sh/cpu/sh4/u-boot.lds b/arch/sh/cpu/sh4/u-boot.lds
index d9c70bc..0ecafcf 100644
--- a/arch/sh/cpu/sh4/u-boot.lds
+++ b/arch/sh/cpu/sh4/u-boot.lds
@@ -75,13 +75,10 @@ SECTIONS
 	}
 	PROVIDE (_egot = .);
 
-	PROVIDE (__u_boot_cmd_start = .);
-	.u_boot_cmd :
-	{
-		*(.u_boot_cmd)
-		. = ALIGN(4);
+
+	.u_boot_list : {
+		#include <u-boot.lst>
 	}
-	PROVIDE (__u_boot_cmd_end = .);
 
 	PROVIDE (reloc_dst_end = .);
 	/* _reloc_dst_end = .; */
diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h
index 6e534ad..9a2c193 100644
--- a/arch/sh/include/asm/global_data.h
+++ b/arch/sh/include/asm/global_data.h
@@ -31,7 +31,7 @@ typedef	struct global_data
 {
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	cpu_clk;	/* CPU clock in Hz! */
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h
index 6c04daf..2c9c463 100644
--- a/arch/sh/include/asm/u-boot.h
+++ b/arch/sh/include/asm/u-boot.h
@@ -33,7 +33,7 @@ typedef struct bd_info {
 	unsigned long   bi_flashoffset; /* reserved area for startup monitor */
 	unsigned long   bi_sramstart;   /* start of SRAM memory */
 	unsigned long   bi_sramsize;    /* size  of SRAM memory */
-	unsigned long   bi_baudrate;    /* Console Baudrate */
+	unsigned int    bi_baudrate;    /* Console Baudrate */
 	unsigned long	bi_boot_params; /* where this board expects params */
 } bd_t;
 
diff --git a/arch/sparc/cpu/leon2/serial.c b/arch/sparc/cpu/leon2/serial.c
index 16fffb6..40d5b01 100644
--- a/arch/sparc/cpu/leon2/serial.c
+++ b/arch/sparc/cpu/leon2/serial.c
@@ -105,13 +105,6 @@ static void leon2_serial_putc(const char c)
 	leon2_serial_putc_raw(c);
 }
 
-static void leon2_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc(*s++);
-	}
-}
-
 static int leon2_serial_getc(void)
 {
 	LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
@@ -172,7 +165,7 @@ static struct serial_device leon2_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= leon2_serial_setbrg,
 	.putc	= leon2_serial_putc,
-	.puts	= leon2_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= leon2_serial_getc,
 	.tstc	= leon2_serial_tstc,
 };
diff --git a/arch/sparc/cpu/leon3/serial.c b/arch/sparc/cpu/leon3/serial.c
index c4f3ee8..838d451 100644
--- a/arch/sparc/cpu/leon3/serial.c
+++ b/arch/sparc/cpu/leon3/serial.c
@@ -99,13 +99,6 @@ static void leon3_serial_putc(const char c)
 	leon3_serial_putc_raw(c);
 }
 
-static void leon3_serial_puts(const char *s)
-{
-	while (*s) {
-		serial_putc(*s++);
-	}
-}
-
 static int leon3_serial_getc(void)
 {
 	if (!leon3_apbuart)
@@ -146,7 +139,7 @@ static struct serial_device leon3_serial_drv = {
 	.stop	= NULL,
 	.setbrg	= leon3_serial_setbrg,
 	.putc	= leon3_serial_putc,
-	.puts	= leon3_serial_puts,
+	.puts	= default_serial_puts,
 	.getc	= leon3_serial_getc,
 	.tstc	= leon3_serial_tstc,
 };
diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h
index 93d3cc0..aa63b35 100644
--- a/arch/sparc/include/asm/global_data.h
+++ b/arch/sparc/include/asm/global_data.h
@@ -40,7 +40,7 @@
 typedef struct global_data {
 	bd_t *bd;
 	unsigned long flags;
-	unsigned long baudrate;
+	unsigned int baudrate;
 	unsigned long cpu_clk;	/* CPU clock in Hz!             */
 	unsigned long bus_clk;
 
diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h
index 8d01118..04c05d4 100644
--- a/arch/sparc/include/asm/u-boot.h
+++ b/arch/sparc/include/asm/u-boot.h
@@ -54,7 +54,7 @@ typedef struct bd_info {
 	unsigned short bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned long bi_baudrate;	/* Console Baudrate */
+	unsigned int bi_baudrate;	/* Console Baudrate */
 } bd_t;
 
 #endif				/* __ASSEMBLY__ */
diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c
index ff0e0f2..32d025a 100644
--- a/arch/sparc/lib/board.c
+++ b/arch/sparc/lib/board.c
@@ -246,8 +246,8 @@ void board_init_f(ulong bootflag)
 	/*
 	 * We have to relocate the command table manually
 	 */
-	fixup_cmdtable(&__u_boot_cmd_start,
-		(ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+	fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+			ll_entry_count(cmd_tbl_t, cmd));
 #endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
 
 #if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds
index fe28030..a1ecefa 100644
--- a/arch/x86/cpu/u-boot.lds
+++ b/arch/x86/cpu/u-boot.lds
@@ -33,10 +33,11 @@ SECTIONS
 	.text  : { *(.text*); }
 
 	. = ALIGN(4);
-	__u_boot_cmd_start = .;
-	.u_boot_cmd : { *(.u_boot_cmd) }
+
 	. = ALIGN(4);
-	__u_boot_cmd_end = .;
+	.u_boot_list : {
+	#include <u-boot.lst>
+	}
 
 	. = ALIGN(4);
 	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 6d29c0b..bce999f 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -38,7 +38,7 @@ typedef	struct global_data {
 	unsigned long	gd_addr;	/* Location of Global Data */
 	bd_t		*bd;
 	unsigned long	flags;
-	unsigned long	baudrate;
+	unsigned int	baudrate;
 	unsigned long	have_console;	/* serial_init() was called */
 #ifdef CONFIG_PRE_CONSOLE_BUFFER
 	unsigned long	precon_buf_idx;	/* Pre-Console buffer index */