diff options
author | Tom Rini <trini@ti.com> | 2014-12-08 16:35:07 -0500 |
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committer | Tom Rini <trini@ti.com> | 2014-12-08 16:35:07 -0500 |
commit | 272a1acf1ef574356e5da51f7d6b3b07ab4e9b83 (patch) | |
tree | b65e7b532ac7beb91cfbf3b16f1df76a3a65d59d /arch | |
parent | 98d2d5e8c473232dc718763dbec284b7349dcc05 (diff) | |
parent | af7219de2c66b64ddae0348b3d3fa5072d800dd2 (diff) | |
download | u-boot-imx-272a1acf1ef574356e5da51f7d6b3b07ab4e9b83.zip u-boot-imx-272a1acf1ef574356e5da51f7d6b3b07ab4e9b83.tar.gz u-boot-imx-272a1acf1ef574356e5da51f7d6b3b07ab4e9b83.tar.bz2 |
Merge git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch')
25 files changed, 355 insertions, 35 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7b42d06..7501eb4 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -110,6 +110,14 @@ config TARGET_P2041RDB config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" +config TARGET_T102XQDS + bool "Support T102xQDS" + select SUPPORT_SPL + +config TARGET_T102XRDB + bool "Support T102xRDB" + select SUPPORT_SPL + config TARGET_T1040QDS bool "Support T1040QDS" @@ -183,6 +191,8 @@ source "board/freescale/p2020come/Kconfig" source "board/freescale/p2020ds/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" +source "board/freescale/t102xqds/Kconfig" +source "board/freescale/t102xrdb/Kconfig" source "board/freescale/t1040qds/Kconfig" source "board/freescale/t104xrdb/Kconfig" source "board/freescale/t208xqds/Kconfig" diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index ad26b43..b93158b 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -51,6 +51,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o obj-$(CONFIG_PPC_T1042) += t1040_ids.o obj-$(CONFIG_PPC_T1020) += t1040_ids.o obj-$(CONFIG_PPC_T1022) += t1040_ids.o +obj-$(CONFIG_PPC_T1023) += t1024_ids.o +obj-$(CONFIG_PPC_T1024) += t1024_ids.o obj-$(CONFIG_PPC_T2080) += t2080_ids.o obj-$(CONFIG_PPC_T2081) += t2080_ids.o @@ -97,6 +99,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o obj-$(CONFIG_PPC_T1042) += t1040_serdes.o obj-$(CONFIG_PPC_T1020) += t1040_serdes.o obj-$(CONFIG_PPC_T1022) += t1040_serdes.o +obj-$(CONFIG_PPC_T1023) += t1024_serdes.o +obj-$(CONFIG_PPC_T1024) += t1024_serdes.o obj-$(CONFIG_PPC_T2080) += t2080_serdes.o obj-$(CONFIG_PPC_T2081) += t2080_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c index 1a30f1c..598f7bd 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -59,8 +59,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), #ifndef CONFIG_PPC_B4420 SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c index cf18be5..63172de 100644 --- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -18,6 +18,8 @@ struct serdes_config { #ifdef CONFIG_PPC_B4860 static struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ + {0x01, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x02, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x04, {AURORA, AURORA, CPRI6, CPRI5, @@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, CPRI2, CPRI1} }, {0x06, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, + {0x07, {AURORA, AURORA, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1} }, {0x08, {AURORA, AURORA, CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} }, {0x09, {AURORA, AURORA, CPRI6, CPRI5, @@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = { CPRI4, CPRI3, NONE, NONE} }, {0x0F, {NONE, NONE, CPRI6, CPRI5, CPRI4, CPRI3, NONE, NONE} }, + {0x17, {NONE, NONE, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x18, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, {0x1B, {NONE, NONE, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x1D, {NONE, NONE, AURORA, AURORA, + NONE, NONE, NONE, NONE} }, {0x1E, {NONE, NONE, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x21, {NONE, NONE, AURORA, AURORA, @@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = { {} }; static struct serdes_config serdes2_cfg_tbl[] = { + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + NONE, NONE, NONE, NONE} }, {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, AURORA, NONE, NONE, NONE, NONE} }, + {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, AURORA, AURORA, NONE, NONE, NONE, NONE} }, + {0x99, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + NONE, NONE, NONE, NONE} }, {0x9A, {PCIE1, PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, NONE, NONE} }, + {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1, + NONE, NONE, NONE, NONE} }, {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE} }, {} diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index fe3eb06..2d5ddf0 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -271,7 +271,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("Work-around for Erratum USB14 enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007186 - puts("Work-around for Erratum A007186 enabled\n"); + if (has_erratum_a007186()) + puts("Work-around for Erratum A007186 enabled\n"); #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 puts("Work-around for Erratum A006593 enabled\n"); @@ -313,6 +314,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A005434 puts("Work-around for Erratum A-005434 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \ + defined(CONFIG_A008044_WORKAROUND) + if (IS_SVR_REV(svr, 1, 0)) + puts("Work-around for Erratum A-008044 enabled\n"); +#endif +#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS) + puts("Work-around for Erratum XFI on B4860QDS enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 8edf5bb..5cfae47 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -11,6 +11,7 @@ #include <asm/processor.h> #include <asm/fsl_law.h> #include <asm/errno.h> +#include <asm/fsl_errata.h> #include "fsl_corenet2_serdes.h" #ifdef CONFIG_SYS_FSL_SRDS_1 @@ -203,7 +204,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK; - if (sel == 0x01 || sel == 0x02) { + if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) { for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) { pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); debug("A007186: pll_num=%x pllcr0=%x\n", diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 488e078..6e3cddd 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -50,8 +50,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7d98870..2b57703 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index b2a23c0..94a5143 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -40,8 +40,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), - SET_DMA_LIODN(1, 196), - SET_DMA_LIODN(2, 197), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 196), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 197), SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index b5d787c..0f292cf 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195), SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196), - SET_DMA_LIODN(1, 197), - SET_DMA_LIODN(2, 198), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 197), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 198), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/p5040_ids.c b/arch/powerpc/cpu/mpc85xx/p5040_ids.c index 990f179..d4343ef 100644 --- a/arch/powerpc/cpu/mpc85xx/p5040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5040_ids.c @@ -42,8 +42,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197), - SET_DMA_LIODN(1, 193), - SET_DMA_LIODN(2, 194), + SET_DMA_LIODN(1, "fsl,eloplus-dma", 193), + SET_DMA_LIODN(2, "fsl,eloplus-dma", 194), }; int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 8426b1a..7e69873 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -37,6 +37,7 @@ void get_sys_info(sys_info_t *sys_info) #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; #endif + __maybe_unused u32 svr; const u8 core_cplx_PLL[16] = { [ 0] = 0, /* CC1 PPL / 1 */ @@ -122,11 +123,27 @@ void get_sys_info(sys_info_t *sys_info) /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. + * T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0 */ #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ - defined(CONFIG_PPC_T4080) - if (SVR_MAJ(get_svr()) >= 2) - mem_pll_rat *= 2; + defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080) + svr = get_svr(); + switch (SVR_SOC_VER(svr)) { + case SVR_T4240: + case SVR_T4160: + case SVR_T4120: + case SVR_T4080: + if (SVR_MAJ(svr) >= 2) + mem_pll_rat *= 2; + break; + case SVR_T2080: + case SVR_T2081: + if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1)) + mem_pll_rat *= 2; + break; + default: + break; + } #endif if (mem_pll_rat > 2) sys_info->freq_ddrbus *= mem_pll_rat; @@ -168,6 +185,9 @@ void get_sys_info(sys_info_t *sys_info) defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FM1_CLK_SEL 0xe0000000 #define FM1_CLK_SHIFT 29 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define FM1_CLK_SEL 0x00000007 +#define FM1_CLK_SHIFT 0 #else #define PME_CLK_SEL 0xe0000000 #define PME_CLK_SHIFT 29 @@ -175,8 +195,12 @@ void get_sys_info(sys_info_t *sys_info) #define FM1_CLK_SHIFT 26 #endif #if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) + rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; +#else rcw_tmp = in_be32(&gur->rcwsr[7]); #endif +#endif #ifdef CONFIG_SYS_DPAA_PME #ifndef CONFIG_PME_PLAT_CLK_DIV @@ -213,7 +237,10 @@ void get_sys_info(sys_info_t *sys_info) #endif #ifdef CONFIG_SYS_DPAA_QBMAN - sys_info->freq_qman = sys_info->freq_systembus / 2; +#ifndef CONFIG_QBMAN_CLK_DIV +#define CONFIG_QBMAN_CLK_DIV 2 +#endif + sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV; #endif #ifdef CONFIG_SYS_DPAA_FMAN diff --git a/arch/powerpc/cpu/mpc85xx/t1024_ids.c b/arch/powerpc/cpu/mpc85xx/t1024_ids.c new file mode 100644 index 0000000..132689b --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t1024_ids.c @@ -0,0 +1,82 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), +}; +#endif + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), + + SET_SATA_LIODN(1, 555), + + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), + /* SET_NEXUS_LIODN(557), -- not yet implemented */ + SET_QE_LIODN(559), + SET_TDM_LIODN(560), +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_10G_LIODN(1, 0, 94), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/t1024_serdes.c b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c new file mode 100644 index 0000000..7dc8385 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/t1024_serdes.c @@ -0,0 +1,52 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/fsl_serdes.h> +#include <asm/processor.h> +#include <asm/io.h> + + +static u8 serdes_cfg_tbl[][4] = { + [0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1}, + [0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1}, + [0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1}, + [0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, + [0x46] = {PCIE1, PCIE1, PCIE2, SATA1}, + [0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1}, + [0x56] = {PCIE1, PCIE3, PCIE2, SATA1}, + [0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1}, + [0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1}, + [0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1}, + [0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC1}, + [0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1}, + [0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2, + SGMII_2500_FM1_DTSEC1}, + [0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1}, + [0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1}, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + return serdes_cfg_tbl[cfg][lane]; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + + if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + for (i = 0; i < 4; i++) { + if (serdes_cfg_tbl[prtcl][i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c index a5dfb81..8091722 100644 --- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c @@ -24,12 +24,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif -struct srio_liodn_id_table srio_liodn_tbl[] = { - SET_SRIO_LIODN_1(1, 307), - SET_SRIO_LIODN_1(2, 387), -}; -int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); - struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(62), @@ -38,12 +32,21 @@ struct liodn_id_table liodn_tbl[] = { SET_SDHC_LIODN(1, 552), + SET_PME_LIODN(117), + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + SET_USB_LIODN(2, "fsl-usb2-dr", 554), - SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148), + SET_SATA_LIODN(1, 555), + SET_SATA_LIODN(2, 556), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), + SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), + + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), /* SET_NEXUS_LIODN(557), -- not yet implemented */ SET_QE_LIODN(559), @@ -74,6 +77,12 @@ struct liodn_id_table sec_liodn_tbl[] = { SET_SEC_RTIC_LIODN_ENTRY(d, 551), SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); @@ -82,4 +91,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_FMAN [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), #endif +#ifdef CONFIG_SYS_DPAA_PME + [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846), +#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/t2080_ids.c b/arch/powerpc/cpu/mpc85xx/t2080_ids.c index 0bfd447..eda7f59 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_ids.c @@ -63,9 +63,9 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), - SET_DMA_LIODN(3, 226), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), + SET_DMA_LIODN(3, "fsl,elo3-dma", 226), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c index 7138bb4..c65f41d 100644 --- a/arch/powerpc/cpu/mpc85xx/t2080_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t2080_serdes.c @@ -169,6 +169,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = { {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} }, {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, + {0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} }, {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} }, {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} }, {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} }, diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index 1a3cb33..470b080 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -93,8 +93,8 @@ struct liodn_id_table liodn_tbl[] = { SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308), SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388), - SET_DMA_LIODN(1, 147), - SET_DMA_LIODN(2, 227), + SET_DMA_LIODN(1, "fsl,elo3-dma", 147), + SET_DMA_LIODN(2, "fsl,elo3-dma", 227), SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 84fec5e..2d28eb2 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -76,6 +76,10 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T1020, T1020, 0), CPU_TYPE_ENTRY(T1021, T1021, 0), CPU_TYPE_ENTRY(T1022, T1022, 0), + CPU_TYPE_ENTRY(T1024, T1024, 0), + CPU_TYPE_ENTRY(T1023, T1023, 0), + CPU_TYPE_ENTRY(T1014, T1014, 0), + CPU_TYPE_ENTRY(T1013, T1013, 0), CPU_TYPE_ENTRY(T2080, T2080, 0), CPU_TYPE_ENTRY(T2081, T2081, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 7860b40..01b0905 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -769,6 +769,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FSL_ERRATUM_A008044 #define CONFIG_SYS_FMAN_V3 #define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV @@ -786,6 +787,52 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\ +defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_E5500 +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_SYS_FMAN_V3 +#ifdef CONFIG_SYS_FSL_DDR4 +#define CONFIG_SYS_FSL_DDRC_GEN4 +#endif +#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define CONFIG_MAX_CPUS 1 +#endif +#define CONFIG_SYS_FSL_NUM_CC_PLL 2 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CONFIG_SYS_SDHC_CLOCK 0 +#define CONFIG_SYS_FSL_NUM_LAWS 16 +#define CONFIG_SYS_FSL_SRDS_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 5 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_FM1_CLK 0 +#define CONFIG_QBMAN_CLK_DIV 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 +#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE +#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE +#define QE_MURAM_SIZE 0x6000UL +#define MAX_QE_RISC 1 +#define QE_NUM_OF_SNUM 28 +#define CONFIG_SYS_FSL_SFP_VER_3_0 + #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index b9e2fb0..61c6d70 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -27,3 +27,27 @@ static inline bool has_erratum_a006379(void) } #endif #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007186 +static inline bool has_erratum_a007186(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + return IS_SVR_REV(svr, 2, 0); + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4860: + return IS_SVR_REV(svr, 2, 0); + case SVR_B4420: + return IS_SVR_REV(svr, 2, 0); + case SVR_T2081: + case SVR_T2080: + return IS_SVR_REV(svr, 1, 0); + } + + return false; +} +#endif diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index adfbb66..811f034 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -91,8 +91,8 @@ extern void fdt_fixup_liodn(void *blob); CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) /* reg nodes for DMA start @ 0x300 */ -#define SET_DMA_LIODN(dmaNum, liodn) \ - SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\ +#define SET_DMA_LIODN(dmaNum, compat, liodn) \ + SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\ CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) #define SET_SDHC_LIODN(sdhcNum, liodn) \ diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 74c5d8f..14c6fc3 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -22,7 +22,9 @@ defined(CONFIG_T2080QDS) || \ defined(CONFIG_T2080RDB) || \ defined(CONFIG_T1040QDS) || \ - defined(CONFIG_T104xRDB) + defined(CONFIG_T104xRDB) || \ + defined(CONFIG_PPC_T1023) || \ + defined(CONFIG_PPC_T1024) #define CONFIG_SYS_CPC_REINIT_F #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 0264523..ace1d12 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1626,10 +1626,15 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 +#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION +#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000 +#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000 +#else #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 +#endif #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 @@ -1787,6 +1792,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define PXCKEN_MASK 0x80000000 #define PXCK_MASK 0x00FF0000 #define PXCK_BITS_START 16 +#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \ + defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23 +#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 +#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28 +#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00 +#define PXCKEN_MASK 0x80000000 +#define PXCK_MASK 0x00FF0000 +#define PXCK_BITS_START 16 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 @@ -2971,6 +2991,8 @@ struct ccsr_sfp_regs { (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \ (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET) +#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \ + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET) #define CONFIG_SYS_FSL_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) #define CONFIG_SYS_FSL_BMAN_ADDR \ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 1b98e0f..2ed51b1 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1133,6 +1133,10 @@ #define SVR_T1020 0x852100 #define SVR_T1021 0x852101 #define SVR_T1022 0x852102 +#define SVR_T1024 0x854000 +#define SVR_T1023 0x854100 +#define SVR_T1014 0x854400 +#define SVR_T1013 0x854500 #define SVR_T2080 0x853000 #define SVR_T2081 0x853100 |