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| author | Bai Ping <ping.bai@nxp.com> | 2017-01-19 18:27:34 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:24:32 +0800 |
| commit | 0e6bbe0b01a4f7142c8d740b163265cd92499539 (patch) | |
| tree | 99b4dfcc850d4438803c5bc31aa0f84ab3d7d6f7 /arch | |
| parent | aef40dc916c57b06efe9c5e900e6be81a33af59a (diff) | |
| download | u-boot-imx-0e6bbe0b01a4f7142c8d740b163265cd92499539.zip u-boot-imx-0e6bbe0b01a4f7142c8d740b163265cd92499539.tar.gz u-boot-imx-0e6bbe0b01a4f7142c8d740b163265cd92499539.tar.bz2 | |
MLK-13761 board: imx7ulp: Fix system reset after a7 rtc alarm expired.
The board will reboot if A7 core enter mem mode by rtc, then M4 core
enter VLLS mode after the RTC alarm expired. Enable the dumb PMIC mode
to fix this issue.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 5aa5974f487e0b4c2e963a86203161c5f05e2fdf)
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/soc.c | 3 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c index a6118af..cba65b5 100644 --- a/arch/arm/cpu/armv7/mx7ulp/soc.c +++ b/arch/arm/cpu/armv7/mx7ulp/soc.c @@ -146,6 +146,9 @@ void s_init(void) /* clock configuration. */ clock_init(); + /* enable dumb pmic */ + writel((readl(SNVS_LP_LPCR) | 0x20), SNVS_LP_LPCR); + return; } diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index dd9db73..a9b7c87 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -55,6 +55,7 @@ #define USDHC1_AIPS2_SLOT (56) #define RGPIO2P0_AIPS0_SLOT (15) #define RGPIO2P1_AIPS2_SLOT (15) +#define SNVS_AIPS2_SLOT (35) #define IOMUXC0_AIPS0_SLOT (61) #define OCOTP_CTRL_AIPS1_SLOT (38) #define OCOTP_CTRL_PCC1_SLOT (38) @@ -174,6 +175,9 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) +#define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) +#define SNVS_LP_LPCR (SNVS_BASE + 0x38) + #define RGPIO2P0_RBASE ((AIPS0_BASE + (AIPS0_SLOT_SIZE * RGPIO2P0_AIPS0_SLOT))) #define RGPIO2P1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * RGPIO2P1_AIPS2_SLOT))) |