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authorTom Rini <trini@ti.com>2014-04-25 14:53:51 -0400
committerTom Rini <trini@ti.com>2014-04-25 14:53:51 -0400
commit080d897585428d0fd42c237abfb6746908f4effc (patch)
treedc65d6d4bbbf1a7f06bbb045a981270a7624ec67 /arch
parentadcdeacc3eda1e5949e54062aa99c299e12483be (diff)
parent08ad9b068afb8842df4cd559c327f54a42811a8d (diff)
downloadu-boot-imx-080d897585428d0fd42c237abfb6746908f4effc.zip
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c23
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c10
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c161
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_early.c8
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c41
-rw-r--r--arch/powerpc/cpu/mpc85xx/fixed_ivor.S63
-rw-r--r--arch/powerpc/cpu/mpc85xx/qe_io.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S3
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c36
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S34
-rw-r--r--arch/powerpc/cpu/mpc85xx/t1040_ids.c1
-rw-r--r--arch/powerpc/cpu/mpc85xx/tlb.c49
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand.lds8
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-spl.lds19
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds7
-rw-r--r--arch/powerpc/cpu/mpc8xxx/law.c52
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h29
-rw-r--r--arch/powerpc/include/asm/fsl_errata.h16
-rw-r--r--arch/powerpc/include/asm/fsl_liodn.h4
-rw-r--r--arch/powerpc/include/asm/fsl_secure_boot.h12
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h35
-rw-r--r--arch/powerpc/include/asm/mmu.h8
-rw-r--r--arch/powerpc/lib/board.c16
24 files changed, 484 insertions, 155 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index ef7637a..4094785 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -102,7 +102,9 @@ obj-y += cpu.o
obj-y += cpu_init.o
obj-y += cpu_init_early.o
obj-y += interrupts.o
+ifneq ($(CONFIG_QEMU_E500),y)
obj-y += speed.o
+endif
obj-y += tlb.o
obj-y += traps.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 8b79c05..9d8acd0 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -113,6 +113,21 @@ static void check_erratum_a4580(uint32_t svr)
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+/*
+ * This workaround can be implemented in PBI, or by u-boot.
+ */
+static void check_erratum_a007212(void)
+{
+ u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+
+ if (in_be32(plldgdcr) & 0x1fe) {
+ /* check if PLL ratio is set by workaround */
+ puts("Work-around for Erratum A007212 enabled\n");
+ }
+}
+#endif
+
static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
@@ -268,6 +283,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A005125
puts("Work-around for Erratum A005125 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007075
+ if (has_erratum_a007075())
+ puts("Work-around for Erratum A007075 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
(SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
@@ -277,6 +296,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if (has_erratum_a006261())
puts("Work-around for Erratum A006261 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+ check_erratum_a007212();
+#endif
+
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3e99b07..12e8e10 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -130,6 +130,11 @@ int checkcpu (void)
get_sys_info(&sysinfo);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ if (sysinfo.diff_sysclk == 1)
+ puts("Single Source Clock Configuration\n");
+#endif
+
puts("Clock Configuration:");
for_each_cpu(i, core, nr_cores, mask) {
if (!(i & 3))
@@ -272,7 +277,7 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
#define CONFIG_SYS_FSL_TBCLK_DIV 8
#endif
-unsigned long get_tbclk (void)
+__weak unsigned long get_tbclk (void)
{
unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV;
@@ -338,7 +343,8 @@ void mpc85xx_reginfo(void)
!defined(CONFIG_SYS_INIT_L2_ADDR)
phys_size_t initdram(int board_type)
{
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) || \
+ defined(CONFIG_QEMU_E500)
return fsl_ddr_sdram_size();
#else
return (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 81aeadd..36ef232 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -33,9 +33,35 @@
#endif
#include "../../../../drivers/block/fsl_sata.h"
+#ifdef CONFIG_U_QE
+#include "../../../../drivers/qe/qe.h"
+#endif
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+/*
+ * For deriving usb clock from 100MHz sysclk, reference divisor is set
+ * to a value of 5, which gives an intermediate value 20(100/5). The
+ * multiplication factor integer is set to 24, which when multiplied to
+ * above intermediate value provides clock for usb ip.
+ */
+void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
+{
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ if (sysinfo.diff_sysclk == 1) {
+ clrbits_be32(&usb_phy->pllprg[1],
+ CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
+ setbits_be32(&usb_phy->pllprg[1],
+ CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
+ CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
+ CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
+ }
+}
+#endif
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
{
@@ -84,7 +110,7 @@ void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
#endif
-#ifdef CONFIG_QE
+#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
extern qe_iop_conf_t qe_iop_conf_tab[];
extern void qe_config_iopin(u8 port, u8 pin, int dir,
int open_drain, int assign);
@@ -173,17 +199,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
#endif
#ifdef CONFIG_SYS_FSL_CPC
-static void enable_cpc(void)
+#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
+static void disable_cpc_sram(void)
{
int i;
- u32 size = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
- u32 cpccfg0 = in_be32(&cpc->cpccfg0);
- size += CPC_CFG0_SZ_K(cpccfg0);
-#ifdef CONFIG_RAMBOOT_PBL
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
/* find and disable LAW of SRAM */
struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
@@ -198,8 +221,21 @@ static void enable_cpc(void)
out_be32(&cpc->cpccsr0, 0);
out_be32(&cpc->cpcsrcr0, 0);
}
+ }
+}
#endif
+static void enable_cpc(void)
+{
+ int i;
+ u32 size = 0;
+
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+ for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+ u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+ size += CPC_CFG0_SZ_K(cpccfg0);
+
#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
#endif
@@ -267,11 +303,77 @@ static void corenet_tb_init(void)
}
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+void fsl_erratum_a007212_workaround(void)
+{
+ ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 ddr_pll_ratio;
+ u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
+ u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
+ u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
+ u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
+ u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
+#endif
+#endif
+ /*
+ * Even this workaround applies to selected version of SoCs, it is
+ * safe to apply to all versions, with the limitation of odd ratios.
+ * If RCW has disabled DDR PLL, we have to apply this workaround,
+ * otherwise DDR will not work.
+ */
+ ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ /* check if RCW sets ratio to 0, required by this workaround */
+ if (ddr_pll_ratio != 0)
+ return;
+ ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ /* check if reserved bits have the desired ratio */
+ if (ddr_pll_ratio == 0) {
+ printf("Error: Unknown DDR PLL ratio!\n");
+ return;
+ }
+ ddr_pll_ratio >>= 1;
+
+ setbits_be32(plldadcr1, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ setbits_be32(plldadcr2, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ setbits_be32(plldadcr3, 0x02000001);
+#endif
+#endif
+ setbits_be32(dpdovrcr4, 0xe0000000);
+ out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
+#endif
+#endif
+ udelay(100);
+ clrbits_be32(plldadcr1, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 2)
+ clrbits_be32(plldadcr2, 0x02000001);
+#if (CONFIG_NUM_DDR_CONTROLLERS >= 3)
+ clrbits_be32(plldadcr3, 0x02000001);
+#endif
+#endif
+ clrbits_be32(dpdovrcr4, 0xe0000000);
+}
+#endif
+
void cpu_init_f (void)
{
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
@@ -298,6 +400,10 @@ void cpu_init_f (void)
law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
if (law.index != -1)
disable_law(law.index);
+
+#if defined(CONFIG_SYS_CPC_REINIT_F)
+ disable_cpc_sram();
+#endif
#endif
#ifdef CONFIG_CPM2
@@ -309,10 +415,12 @@ void cpu_init_f (void)
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
-#ifdef CONFIG_QE
+
+#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
/* Config QE ioports */
config_qe_ioports();
#endif
+
#if defined(CONFIG_FSL_DMA)
dma_init();
#endif
@@ -330,6 +438,17 @@ void cpu_init_f (void)
in_be32(&gur->dcsrcr);
#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#ifdef CONFIG_DEEP_SLEEP
+ /* disable the console if boot from deep sleep */
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3))
+ gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+#endif
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+ fsl_erratum_a007212_workaround();
+#endif
+
}
/* Implement a dummy function for those platforms w/o SERDES */
@@ -598,6 +717,9 @@ skip_l2:
puts("disabled\n");
#endif
+#if defined(CONFIG_RAMBOOT_PBL)
+ disable_cpc_sram();
+#endif
enable_cpc();
#ifndef CONFIG_SYS_FSL_NO_SERDES
@@ -716,6 +838,9 @@ skip_l2:
CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ usb_single_source_clk_configure(usb_phy);
+#endif
setbits_be32(&usb_phy->port1.ctrl,
CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
setbits_be32(&usb_phy->port1.drvvbuscfg,
@@ -767,8 +892,6 @@ skip_l2:
return 0;
}
-extern void setup_ivors(void);
-
void arch_preboot_os(void)
{
u32 msr;
@@ -781,8 +904,6 @@ void arch_preboot_os(void)
msr = mfmsr();
msr &= ~(MSR_ME|MSR_CE);
mtmsr(msr);
-
- setup_ivors();
}
#if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
@@ -797,21 +918,13 @@ int sata_initialize(void)
void cpu_secondary_init_r(void)
{
-#ifdef CONFIG_QE
+#ifdef CONFIG_U_QE
+ uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
+#elif defined CONFIG_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
-#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
- int ret;
- size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
-
- /* load QE firmware from NAND flash to DDR first */
- ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
- &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
-
- if (ret && ret == -EUCLEAN) {
- printf ("NAND read for QE firmware at offset %x failed %d\n",
- CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
- }
#endif
+
+#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 993b8b8..998781b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -79,7 +79,7 @@ void setup_ifc(void)
#endif
/* We run cpu_init_early_f in AS = 1 */
-void cpu_init_early_f(void)
+void cpu_init_early_f(void *fdt)
{
u32 mas0, mas1, mas2, mas3, mas7;
int i;
@@ -102,6 +102,12 @@ void cpu_init_early_f(void)
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
+ /*
+ * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
+ * so we need to populate it before it accesses it.
+ */
+ gd->fdt_blob = fdt;
+
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 33bc900..0cc21c7 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -275,12 +275,16 @@ static inline void ft_fixup_l2cache(void *blob)
u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
/* Only initialize every eighth thread */
- if (reg && !((*reg) % 8))
+ if (reg && !((*reg) % 8)) {
+ fdt_setprop_cell(blob, l2_off, "cache-stash-id",
+ (*reg / 4) + 32 + 1);
+ }
#else
- if (reg)
-#endif
+ if (reg) {
fdt_setprop_cell(blob, l2_off, "cache-stash-id",
- (*reg * 2) + 32 + 1);
+ (*reg * 2) + 32 + 1);
+ }
+#endif
#endif
fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
@@ -582,6 +586,33 @@ static void fdt_fixup_usb(void *fdt)
#define fdt_fixup_usb(x)
#endif
+#if defined(CONFIG_PPC_T1040)
+static void fdt_fixup_l2_switch(void *blob)
+{
+ uchar l2swaddr[6];
+ int node;
+
+ /* The l2switch node from device-tree has
+ * compatible string "vitesse-9953" */
+ node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
+ if (node == -FDT_ERR_NOTFOUND)
+ /* no l2switch node has been found */
+ return;
+
+ /* Get MAC address for the l2switch from "l2switchaddr"*/
+ if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) {
+ printf("Warning: MAC address for l2switch not found\n");
+ memset(l2swaddr, 0, sizeof(l2swaddr));
+ }
+
+ /* Add MAC address to l2switch node */
+ fdt_setprop(blob, node, "local-mac-address", l2swaddr,
+ sizeof(l2swaddr));
+}
+#else
+#define fdt_fixup_l2_switch(x)
+#endif
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
int off;
@@ -719,6 +750,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
"clock-frequency", gd->bus_clk/2, 1);
fdt_fixup_usb(blob);
+
+ fdt_fixup_l2_switch(blob);
}
/*
diff --git a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S b/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
deleted file mode 100644
index ebbb8c0..0000000
--- a/arch/powerpc/cpu/mpc85xx/fixed_ivor.S
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * Kumar Gala <kumar.gala@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* This file is intended to be included by other asm code since
- * we will want to execute this on both the primary core when
- * it does a bootm and the secondary core's that get released
- * out of the spin table */
-
-#define SET_IVOR(vector_number, vector_offset) \
- li r3,vector_offset@l; \
- mtspr SPRN_IVOR##vector_number,r3;
-
-#define SET_GIVOR(vector_number, vector_offset) \
- li r3,vector_offset@l; \
- mtspr SPRN_GIVOR##vector_number,r3;
-
- SET_IVOR(0, 0x020) /* Critical Input */
- SET_IVOR(1, 0x000) /* Machine Check */
- SET_IVOR(2, 0x060) /* Data Storage */
- SET_IVOR(3, 0x080) /* Instruction Storage */
- SET_IVOR(4, 0x0a0) /* External Input */
- SET_IVOR(5, 0x0c0) /* Alignment */
- SET_IVOR(6, 0x0e0) /* Program */
- SET_IVOR(7, 0x100) /* FP Unavailable */
- SET_IVOR(8, 0x120) /* System Call */
- SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */
- SET_IVOR(10, 0x160) /* Decrementer */
- SET_IVOR(11, 0x180) /* Fixed Interval Timer */
- SET_IVOR(12, 0x1a0) /* Watchdog Timer */
- SET_IVOR(13, 0x1c0) /* Data TLB Error */
- SET_IVOR(14, 0x1e0) /* Instruction TLB Error */
- SET_IVOR(15, 0x040) /* Debug */
-
-/* e500v1 & e500v2 only */
-#ifndef CONFIG_E500MC
- SET_IVOR(32, 0x200) /* SPE Unavailable */
- SET_IVOR(33, 0x220) /* Embedded FP Data */
- SET_IVOR(34, 0x240) /* Embedded FP Round */
-#endif
-
- SET_IVOR(35, 0x260) /* Performance monitor */
-
-/* e500mc only */
-#ifdef CONFIG_E500MC
- SET_IVOR(36, 0x280) /* Processor doorbell */
- SET_IVOR(37, 0x2a0) /* Processor doorbell critical */
- SET_IVOR(38, 0x2c0) /* Guest Processor doorbell */
- SET_IVOR(39, 0x2e0) /* Guest Processor critical & machine check */
- SET_IVOR(40, 0x300) /* Hypervisor system call */
- SET_IVOR(41, 0x320) /* Hypervisor Priviledge */
-
- SET_GIVOR(2, 0x060) /* Guest Data Storage */
- SET_GIVOR(3, 0x080) /* Guest Instruction Storage */
- SET_GIVOR(4, 0x0a0) /* Guest External Input */
- SET_GIVOR(8, 0x120) /* Guest System Call */
- SET_GIVOR(13, 0x1c0) /* Guest Data TLB Error */
- SET_GIVOR(14, 0x1e0) /* Guest Instruction TLB Error */
-#endif
diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c
index 76c60da..d2825ec 100644
--- a/arch/powerpc/cpu/mpc85xx/qe_io.c
+++ b/arch/powerpc/cpu/mpc85xx/qe_io.c
@@ -12,7 +12,7 @@
#include "asm/io.h"
#include "asm/immap_85xx.h"
-#if defined(CONFIG_QE)
+#if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
#define NUM_OF_PINS 32
void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
{
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index fcfba7e..a2c0ad4 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -405,9 +405,6 @@ __second_half_boot_page:
bne 3b
isync
- /* setup IVORs to match fixed offsets */
-#include "fixed_ivor.S"
-
/* get the upper bits of the addr */
lwz r11,ENTRY_ADDR_UPPER(r10)
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index adf09ef..d516d4e 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -74,28 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
-#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
- uint single_src;
-#endif
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+ uint ddr_refclk_sel;
+ unsigned int porsr1_sys_clk;
+ porsr1_sys_clk = in_be32(&gur->porsr1) >> FSL_DCFG_PORSR1_SYSCLK_SHIFT
+ & FSL_DCFG_PORSR1_SYSCLK_MASK;
+ if (porsr1_sys_clk == FSL_DCFG_PORSR1_SYSCLK_DIFF)
+ sys_info->diff_sysclk = 1;
+ else
+ sys_info->diff_sysclk = 0;
+
/*
* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
* are driven by separate DDR Refclock or single source
* differential clock.
*/
- single_src = (in_be32(&gur->rcwsr[5]) >>
+ ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >>
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
/*
- * For single source clocking, both ddrclock and syclock
+ * For single source clocking, both ddrclock and sysclock
* are driven by differential sysclock.
*/
- if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
- printf("Single Source Clock Configuration\n");
+ if (ddr_refclk_sel == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK)
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
- } else
+ else
#endif
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
@@ -107,6 +112,13 @@ void get_sys_info(sys_info_t *sys_info)
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
& FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
+ if (mem_pll_rat == 0) {
+ mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
+ FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
+ }
+#endif
/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
@@ -151,8 +163,8 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
-#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
- defined(CONFIG_PPC_T2081)
+#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) || \
+ defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#else
@@ -336,6 +348,10 @@ void get_sys_info(sys_info_t *sys_info)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#ifdef CONFIG_U_QE
+ sys_info->freq_qe = sys_info->freq_systembus / 2;
+#endif
+
#else /* CONFIG_FSL_CORENET */
uint plat_ratio, e500_ratio, half_freq_systembus;
int i;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index dbbd8e5..0e3c86a 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -26,6 +26,8 @@
#undef MSR_KERNEL
#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+#define LAW_EN 0x80000000
+
#if defined(CONFIG_NAND_SPL) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL))
#define MINIMAL_SPL
@@ -78,6 +80,13 @@ _start_e500:
li r1,MSR_DE
mtmsr r1
+ /*
+ * If we got an ePAPR device tree pointer passed in as r3, we need that
+ * later in cpu_init_early_f(). Save it to a safe register before we
+ * clobber it so that we can fetch it from there later.
+ */
+ mr r24, r3
+
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
mfspr r3,SPRN_SVR
rlwinm r3,r3,0,0xff
@@ -115,7 +124,8 @@ _start_e500:
#endif
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+ !defined(CONFIG_E6500)
/* ISBC uses L2 as stack.
* Disable L2 cache here so that u-boot can enable it later
* as part of it's normal flow
@@ -460,7 +470,8 @@ nexti: mflr r1 /* R1 = our PC */
2: cmpw r3, r4
blt 1b
-#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL)
+#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && !defined(MINIMAL_SPL) && \
+ !defined(CONFIG_SECURE_BOOT)
/*
* TLB entry for debuggging in AS1
* Create temporary TLB entry in AS0 to handle debug exception
@@ -481,12 +492,6 @@ nexti: mflr r1 /* R1 = our PC */
0xffc00000, MAS3_SX|MAS3_SW|MAS3_SR, \
0, r6
-#elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT)
- create_tlb1_entry CONFIG_SYS_PPC_E500_DEBUG_TLB, \
- 0, BOOKE_PAGESZ_1M, \
- CONFIG_SYS_MONITOR_BASE, MAS2_I|MAS2_G, \
- CONFIG_SYS_PBI_FLASH_WINDOW, MAS3_SX|MAS3_SW|MAS3_SR, \
- 0, r6
#else
/*
* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
@@ -574,7 +579,6 @@ infinite_debug_loop:
#ifdef CONFIG_FSL_CORENET
#define CCSR_LAWBARH0 (CONFIG_SYS_CCSRBAR + 0x1000)
-#define LAW_EN 0x80000000
#define LAW_SIZE_4K 0xb
#define CCSRBAR_LAWAR (LAW_EN | (0x1e << 20) | LAW_SIZE_4K)
#define CCSRAR_C 0x80000000 /* Commit */
@@ -1142,6 +1146,10 @@ _start_cont:
mr r1,r3 /* Transfer to SP(r1) */
GET_GOT
+
+ /* Pass our potential ePAPR device tree pointer to cpu_init_early_f */
+ mr r3, r24
+
bl cpu_init_early_f
/* switch back to AS = 0 */
@@ -1644,6 +1652,7 @@ relocate_code:
mr r10,r5 /* Save copy of Destination Address */
GET_GOT
+#ifndef CONFIG_SPL_SKIP_RELOCATE
mr r3,r5 /* Destination Address */
lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
@@ -1734,6 +1743,7 @@ relocate_code:
mtlr r0
blr /* NEVER RETURNS! */
+#endif
.globl in_ram
in_ram:
@@ -1965,10 +1975,4 @@ flush_dcache:
isync
blr
-
-.globl setup_ivors
-setup_ivors:
-
-#include "fixed_ivor.S"
- blr
#endif /* !MINIMAL_SPL */
diff --git a/arch/powerpc/cpu/mpc85xx/t1040_ids.c b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
index 68160a9..1034cd4 100644
--- a/arch/powerpc/cpu/mpc85xx/t1040_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t1040_ids.c
@@ -46,6 +46,7 @@ struct liodn_id_table liodn_tbl[] = {
SET_DMA_LIODN(2, 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
+ SET_QE_LIODN(559),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 8748ecd..129ec66 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -24,7 +24,7 @@ void invalidate_tlb(u8 tlb)
mtspr(MMUCSR0, 0x2);
}
-void init_tlbs(void)
+__weak void init_tlbs(void)
{
int i;
@@ -236,20 +236,26 @@ void init_addr_map(void)
}
#endif
-unsigned int
-setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
+uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+ enum tlb_map_type map_type)
{
int i;
unsigned int tlb_size;
- unsigned int wimge = MAS2_M;
- unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ unsigned int wimge;
+ unsigned int perm;
unsigned int max_cam, tsize_mask;
- u64 size, memsize = (u64)memsize_in_meg << 20;
+ if (map_type == TLB_MAP_RAM) {
+ perm = MAS3_SX|MAS3_SW|MAS3_SR;
+ wimge = MAS2_M;
#ifdef CONFIG_SYS_PPC_DDR_WIMGE
- wimge = CONFIG_SYS_PPC_DDR_WIMGE;
+ wimge = CONFIG_SYS_PPC_DDR_WIMGE;
#endif
- size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+ } else {
+ perm = MAS3_SW|MAS3_SR;
+ wimge = MAS2_I|MAS2_G;
+ }
+
if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
/* Convert (4^max) kB to (2^max) bytes */
max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
@@ -261,11 +267,11 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
}
for (i = 0; size && i < 8; i++) {
- int ram_tlb_index = find_free_tlbcam();
+ int tlb_index = find_free_tlbcam();
u32 camsize = __ilog2_u64(size) & tsize_mask;
- u32 align = __ilog2(ram_tlb_address) & tsize_mask;
+ u32 align = __ilog2(v_addr) & tsize_mask;
- if (ram_tlb_index == -1)
+ if (tlb_index == -1)
break;
if (align == -2) align = max_cam;
@@ -277,18 +283,29 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
tlb_size = camsize - 10;
- set_tlb(1, ram_tlb_address, p_addr,
- MAS3_SX|MAS3_SW|MAS3_SR, wimge,
- 0, ram_tlb_index, tlb_size, 1);
+ set_tlb(1, v_addr, p_addr, perm, wimge,
+ 0, tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
- memsize -= 1ULL << camsize;
- ram_tlb_address += 1UL << camsize;
+ v_addr += 1UL << camsize;
p_addr += 1UL << camsize;
}
+ return size;
+}
+
+unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
+ unsigned int memsize_in_meg)
+{
+ unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+ u64 memsize = (u64)memsize_in_meg << 20;
+
+ memsize = min(memsize, CONFIG_MAX_MEM_MAPPED);
+ memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
+
if (memsize)
print_size(memsize, " left unmapped\n");
+
return memsize_in_meg;
}
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index df3b0f9..d77a6dc 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -4,6 +4,12 @@
* SPDX-License-Identifier: GPL-2.0+
*/
+#include "config.h" /* CONFIG_BOARDDIR */
+
+#ifndef CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
+
OUTPUT_ARCH(powerpc)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
@@ -76,7 +82,7 @@ SECTIONS
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
- . = ADDR(.text) + 0x80000;
+ . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
__bss_start = .;
.bss (NOLOAD) :
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index acaa093..8453f3a 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,6 +57,16 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
+#ifdef CONFIG_SPL_SKIP_RELOCATE
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : {
+ *(.sbss*)
+ *(.bss*)
+ }
+ . = ALIGN(4);
+ __bss_end = .;
+#endif
/* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
@@ -66,11 +76,16 @@ SECTIONS
} :text = 0xffff
#else
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
- .bootpg ADDR(.text) + 0x1000 :
+#ifndef BOOT_PAGE_OFFSET
+#define BOOT_PAGE_OFFSET 0x1000
+#endif
+ .bootpg ADDR(.text) + BOOT_PAGE_OFFSET :
{
arch/powerpc/cpu/mpc85xx/start.o (.bootpg)
}
+#ifndef RESET_VECTOR_OFFSET
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#endif
#elif defined(CONFIG_FSL_ELBC)
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
#else
@@ -81,6 +96,7 @@ SECTIONS
} = 0xffff
#endif
+#ifndef CONFIG_SPL_SKIP_RELOCATE
/*
* Make sure that the bss segment isn't linked at 0x0, otherwise its
* address won't be updated during relocation fixups.
@@ -95,4 +111,5 @@ SECTIONS
}
. = ALIGN(4);
__bss_end = .;
+#endif
}
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 2af4c80..0b9086d 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -12,7 +12,12 @@
#define RESET_VECTOR_ADDRESS 0xfffffffc
#endif
+#ifndef CONFIG_SYS_MONITOR_LEN
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#endif
+
OUTPUT_ARCH(powerpc)
+ENTRY(_start_e500)
PHDRS
{
@@ -84,7 +89,7 @@ SECTIONS
{
KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
} :text = 0xffff
- . = ADDR(.text) + 0x80000;
+ . = ADDR(.text) + CONFIG_SYS_MONITOR_LEN;
#else
.bootpg RESET_VECTOR_ADDRESS - 0xffc :
{
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index a401083..33d53a8 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -221,6 +221,32 @@ int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
}
#endif /* not SPL */
+void disable_non_ddr_laws(void)
+{
+ int i;
+ int id;
+ for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
+ u32 lawar = in_be32(LAWAR_ADDR(i));
+
+ if (lawar & LAW_EN) {
+ id = (lawar & ~LAW_EN) >> 20;
+ switch (id) {
+ case LAW_TRGT_IF_DDR_1:
+ case LAW_TRGT_IF_DDR_2:
+ case LAW_TRGT_IF_DDR_3:
+ case LAW_TRGT_IF_DDR_4:
+ case LAW_TRGT_IF_DDR_INTRLV:
+ case LAW_TRGT_IF_DDR_INTLV_34:
+ case LAW_TRGT_IF_DDR_INTLV_123:
+ case LAW_TRGT_IF_DDR_INTLV_1234:
+ continue;
+ default:
+ disable_law(i);
+ }
+ }
+ }
+}
+
void init_laws(void)
{
int i;
@@ -233,6 +259,23 @@ void init_laws(void)
#error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
#endif
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500) && \
+ !defined(CONFIG_E500MC)
+ /* ISBC (Boot ROM) creates a LAW 0 entry for non PBL platforms,
+ * which is not disabled before transferring the control to uboot.
+ * Disable the LAW 0 entry here.
+ */
+ disable_law(0);
+#endif
+
+#if !defined(CONFIG_SECURE_BOOT)
+ /*
+ * if any non DDR LAWs has been created earlier, remove them before
+ * LAW table is parsed.
+ */
+ disable_non_ddr_laws();
+#endif
+
/*
* Any LAWs that were set up before we booted assume they are meant to
* be around and mark them used.
@@ -244,15 +287,6 @@ void init_laws(void)
gd->arch.used_laws |= (1 << i);
}
-#if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
- (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
- /*
- * in SPL boot we've already parsed the law_table and setup those LAWs
- * so don't do it again.
- */
- return;
-#endif
-
for (i = 0; i < num_law_entries; i++) {
if (law_table[i].index == -1)
set_next_law(law_table[i].addr, law_table[i].size,
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index df44451..864e74c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -19,8 +19,8 @@
*/
#define CONFIG_PPC_SPINTABLE_COMPATIBLE
-#define FSL_DDR_VER_4_7 47
-#define FSL_DDR_VER_5_0 50
+#include <fsl_ddrc_version.h>
+#define CONFIG_SYS_FSL_DDR_BE
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
@@ -154,6 +154,7 @@
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_ESDHC_HC_BLK_ADDR
@@ -401,6 +402,7 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_5
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
@@ -442,6 +444,7 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -476,6 +479,7 @@
#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
#define CONFIG_SYS_FSL_ERRATUM_A005812
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
@@ -490,6 +494,7 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 32
@@ -527,6 +532,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_TBCLK_DIV 16
@@ -553,6 +559,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_4
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
@@ -571,6 +578,7 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
#define CONFIG_NUM_DDR_CONTROLLERS 2
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
@@ -668,8 +676,10 @@
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
+#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#ifdef CONFIG_PPC_B4860
@@ -704,6 +714,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#endif
#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
#define CONFIG_MAX_CPUS 4
#elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
@@ -736,6 +749,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define QE_MURAM_SIZE 0x6000UL
+#define MAX_QE_RISC 1
+#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
@@ -777,6 +793,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
+#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_ISBC_VER 2
@@ -793,10 +810,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_FSL_SEC_COMPAT 6
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_6
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#elif defined(CONFIG_QEMU_E500)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xe0000000
+
#else
#error Processor type not defined for this platform
#endif
@@ -813,7 +835,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
- !defined(CONFIG_SYS_FSL_DDRC_GEN3)
+ !defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
+ !defined(CONFIG_SYS_FSL_DDRC_GEN4)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index c9982cc..4eba85c 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -60,4 +60,20 @@ static inline bool has_erratum_a006261(void)
}
#endif
+static inline bool has_erratum_a007075(void)
+{
+ u32 svr = get_svr();
+ u32 soc = SVR_SOC_VER(svr);
+
+ switch (soc) {
+ case SVR_B4860:
+ case SVR_B4420:
+ return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+ case SVR_P1010:
+ return IS_SVR_REV(svr, 1, 0);
+ case SVR_P4080:
+ return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+ }
+ return false;
+}
#endif
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index 44bc88d..f658bcb 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -99,6 +99,10 @@ extern void fdt_fixup_liodn(void *blob);
SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
+#define SET_QE_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
+ CONFIG_SYS_MPC85xx_QE_OFFSET)
+
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 4c7f0b1..29bef91 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -10,10 +10,22 @@
#ifdef CONFIG_SECURE_BOOT
#if defined(CONFIG_FSL_CORENET)
#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
+#elif defined(CONFIG_BSC9132QDS)
+#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
#else
#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
#endif
#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
+#if defined(CONFIG_B4860QDS) || \
+ defined(CONFIG_T4240QDS) || \
+ defined(CONFIG_T2080QDS) || \
+ defined(CONFIG_T1040QDS) || \
+ defined(CONFIG_T1040RDB)
+#define CONFIG_SYS_CPC_REINIT_F
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
+#endif
+
#endif
#endif
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 4b6f9d0..741b861 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1583,6 +1583,12 @@ typedef struct cpc_corenet {
typedef struct ccsr_gur {
u32 porsr1; /* POR status 1 */
u32 porsr2; /* POR status 2 */
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+#define FSL_DCFG_PORSR1_SYSCLK_SHIFT 15
+#define FSL_DCFG_PORSR1_SYSCLK_MASK 0x1
+#define FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED 0x1
+#define FSL_DCFG_PORSR1_SYSCLK_DIFF 0x0
+#endif
u8 res_008[0x20-0x8];
u32 gpporcr1; /* General-purpose POR configuration */
u32 gpporcr2; /* General-purpose POR configuration 2 */
@@ -1739,6 +1745,8 @@ typedef struct ccsr_gur {
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
+/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
+#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
@@ -1889,7 +1897,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
u32 sata2liodnr; /* SATA 2 LIODN */
u32 sata3liodnr; /* SATA 3 LIODN */
u32 sata4liodnr; /* SATA 4 LIODN */
- u8 res22[32];
+ u8 res22[24];
+ u32 qeliodnr; /* QE LIODN */
+ u8 res_57c[4];
u32 dma1liodnr; /* DMA 1 LIODN */
u32 dma2liodnr; /* DMA 2 LIODN */
u32 dma3liodnr; /* DMA 3 LIODN */
@@ -2877,6 +2887,7 @@ struct ccsr_pman {
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
&& !defined(CONFIG_PPC_B4420)
@@ -3151,4 +3162,26 @@ struct dcsr_dcfg_regs {
#define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
};
+
+#define CONFIG_SYS_MPC85xx_SCFG \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
+#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000
+/* The supplement configuration unit register */
+struct ccsr_scfg {
+ u32 dpslpcr; /* 0x000 Deep Sleep Control register */
+ u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
+ u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
+ u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
+ u32 res1[4];
+ u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
+ u32 res2;
+ u32 pixclkcr; /* 0x028 Pixel Clock Control register */
+ u32 res3[245];
+ u32 qeioclkcr; /* 0x400 QUICC Engine IO Clock Control register */
+ u32 emiiocr; /* 0x404 EMI MDIO Control Register */
+ u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
+ u32 qmifrstcr; /* 0x40c QMAN Interface Reset Control register */
+ u32 res4[60];
+ u32 sparecr[8]; /* 0x500 Spare Control register(0-7) */
+};
#endif /*__IMMAP_85xx__*/
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h
index cadaeef..5aa916f 100644
--- a/arch/powerpc/include/asm/mmu.h
+++ b/arch/powerpc/include/asm/mmu.h
@@ -509,6 +509,14 @@ extern void print_tlbcam(void);
extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
extern void clear_ddr_tlbs(unsigned int memsize_in_meg);
+enum tlb_map_type {
+ TLB_MAP_RAM,
+ TLB_MAP_IO,
+};
+
+extern uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
+ enum tlb_map_type map_type);
+
extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7);
#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index f86c6f3..8b03d3a 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -343,6 +343,13 @@ void board_init_f(ulong bootflag)
#ifdef CONFIG_PRAM
ulong reg;
#endif
+#ifdef CONFIG_DEEP_SLEEP
+ const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct ccsr_scfg *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
+ u32 start_addr;
+ typedef void (*func_t)(void);
+ func_t kernel_resume;
+#endif
/* Pointer is writable since we allocated a register for it */
gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
@@ -360,6 +367,15 @@ void board_init_f(ulong bootflag)
if ((*init_fnc_ptr) () != 0)
hang();
+#ifdef CONFIG_DEEP_SLEEP
+ /* Jump to kernel in deep sleep case */
+ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) {
+ start_addr = in_be32(&scfg->sparecr[1]);
+ kernel_resume = (func_t)start_addr;
+ kernel_resume();
+ }
+#endif
+
#ifdef CONFIG_POST
post_bootmode_init();
post_run(NULL, POST_ROM | post_bootmode_get(NULL));