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authorShaveta Leekha <shaveta@freescale.com>2014-02-26 16:06:56 +0530
committerYork Sun <yorksun@freescale.com>2014-03-07 14:49:45 -0800
commitfb07c0a16dce007208d58c673aacc649703f18fd (patch)
tree6710f80c1001be28ba1f9be0dfd054d600282ce3 /arch
parent5e5097c110ab5d6bda7f18b7a795d17f27ac3d36 (diff)
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board/b4860qds: Add support to make PCIe SATA work on B4860QDS
1) SerDes2 Refclks have been set properly to make PCIe SATA to work as it work on SerDes refclk of 100MHz 2) Mask the SerDes's device reset request before changing the Refclks for SerDes1 and SerDes2 for PLL locks to happen properly, device reset request bit unmasked after SerDes refclks configuration Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9d08321..e0efc7e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1722,6 +1722,9 @@ typedef struct ccsr_gur {
u32 rstrqpblsr; /* Reset request preboot loader status */
u8 res11[8];
u32 rstrqmr1; /* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
+#endif
u8 res12[4];
u32 rstrqsr1; /* Reset request status */
u8 res13[4];