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| author | Paul Burton <paul.burton@imgtec.com> | 2015-01-29 10:04:10 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | 2015-01-30 14:19:58 +0100 |
| commit | f1c64a08106db5ce87b6afe76785e2d4fddcff63 (patch) | |
| tree | f24a7289de9dec7d5136918cf0e9fc96fa452bad /arch | |
| parent | ab0d002677185e6a1bcaf92f507d140b96bb1053 (diff) | |
| download | u-boot-imx-f1c64a08106db5ce87b6afe76785e2d4fddcff63.zip u-boot-imx-f1c64a08106db5ce87b6afe76785e2d4fddcff63.tar.gz u-boot-imx-f1c64a08106db5ce87b6afe76785e2d4fddcff63.tar.bz2 | |
MIPS: handle mips64 ST0_KX bit in mips32 start.S
In preparation for sharing a single copy of start.S between mips32 &
mips64, handle setting the KX bit of the cop0 Status register when the
mips32 start.S is built for mips64.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/cpu/mips32/start.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S index 699c59a..3b5b622 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S @@ -23,6 +23,7 @@ #ifdef CONFIG_32BIT # define MIPS_RELOC 3 +# define STATUS_SET 0 #endif #ifdef CONFIG_64BIT @@ -34,6 +35,7 @@ ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24) # endif # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03) +# define STATUS_SET ST0_KX #endif /* @@ -120,7 +122,7 @@ reset: /* WP(Watch Pending), SW0/1 should be cleared */ mtc0 zero, CP0_CAUSE - setup_c0_status 0 0 + setup_c0_status STATUS_SET 0 /* Init Timer */ mtc0 zero, CP0_COUNT |