Merge branch 'u-boot/master' into 'u-boot-arm/master'

author: Albert ARIBAUD <albert.u.boot@aribaud.net> 2015-05-05 10:09:06 +0200
committer: Albert ARIBAUD <albert.u.boot@aribaud.net> 2015-05-05 10:09:06 +0200
commit: b939689c7b87773c44275a578ffc8674a867e39d (patch)
tree: 785d71eb0bbc707385e4456a14b21706223d99a3 /arch
parent: 97840b5d1fe0960134c3553a9d9d1c1cd1be784d (diff)
parent: ace97d26176a3ebc9ec07738450de93eea35975c (diff)
download: u-boot-imx-b939689c7b87773c44275a578ffc8674a867e39d.zip
u-boot-imx-b939689c7b87773c44275a578ffc8674a867e39d.tar.gz
u-boot-imx-b939689c7b87773c44275a578ffc8674a867e39d.tar.bz2
214 files changed, 6161 insertions, 1524 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index 2ca5305..1102346 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -70,6 +70,12 @@ config SANDBOX
 	select HAVE_GENERIC_BOARD
 	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
+	select DM
+	select DM_SPI_FLASH
+	select DM_SERIAL
+	select DM_I2C
+	select DM_SPI
+	select DM_GPIO
 
 config SH
 	bool "SuperH architecture"
@@ -84,6 +90,9 @@ config X86
 	select HAVE_GENERIC_BOARD
 	select SYS_GENERIC_BOARD
 	select SUPPORT_OF_CONTROL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 endchoice
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7ed0e20..00be305 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -33,6 +33,9 @@ config CPU_V7
         bool
         select HAS_VBAR
 
+config CPU_V7M
+	bool
+
 config CPU_PXA
         bool
 
@@ -47,6 +50,7 @@ config SYS_CPU
         default "arm1136" if CPU_ARM1136
         default "arm1176" if CPU_ARM1176
         default "armv7" if CPU_V7
+        default "armv7m" if CPU_V7M
         default "pxa" if CPU_PXA
         default "sa1100" if CPU_SA1100
 	default "armv8" if ARM64
@@ -61,18 +65,6 @@ config SEMIHOSTING
 choice
 	prompt "Target select"
 
-config TARGET_INTEGRATORAP_CM720T
-	bool "Support integratorap_cm720t"
-	select CPU_ARM720T
-
-config TARGET_INTEGRATORAP_CM920T
-	bool "Support integratorap_cm920t"
-	select CPU_ARM920T
-
-config TARGET_INTEGRATORCP_CM920T
-	bool "Support integratorcp_cm920t"
-	select CPU_ARM920T
-
 config ARCH_AT91
 	bool "Atmel AT91"
 
@@ -92,14 +84,6 @@ config TARGET_SMDK2410
 	bool "Support smdk2410"
 	select CPU_ARM920T
 
-config TARGET_INTEGRATORAP_CM926EJS
-	bool "Support integratorap_cm926ejs"
-	select CPU_ARM926EJS
-
-config TARGET_INTEGRATORCP_CM926EJS
-	bool "Support integratorcp_cm926ejs"
-	select CPU_ARM926EJS
-
 config TARGET_ASPENITE
 	bool "Support aspenite"
 	select CPU_ARM926EJS
@@ -235,6 +219,8 @@ config TARGET_SPEAR600
 config TARGET_STV0991
 	bool "Support stv0991"
 	select CPU_V7
+	select DM
+	select DM_SERIAL
 
 config TARGET_X600
 	bool "Support x600"
@@ -245,10 +231,6 @@ config ARCH_VERSATILE
 	bool "ARM Ltd. Versatile family"
 	select CPU_ARM926EJS
 
-config TARGET_INTEGRATORCP_CM1136
-	bool "Support integratorcp_cm1136"
-	select CPU_ARM1136
-
 config TARGET_IMX31_PHYCORE
 	bool "Support imx31_phycore"
 	select CPU_ARM1136
@@ -293,14 +275,9 @@ config TARGET_MX35PDK
 
 config ARCH_BCM283X
 	bool "Broadcom BCM283X family"
-
-config TARGET_INTEGRATORAP_CM946ES
-	bool "Support integratorap_cm946es"
-	select CPU_ARM946ES
-
-config TARGET_INTEGRATORCP_CM946ES
-	bool "Support integratorcp_cm946es"
-	select CPU_ARM946ES
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_VEXPRESS_CA15_TC2
 	bool "Support vexpress_ca15_tc2"
@@ -330,21 +307,33 @@ config TARGET_CM_T335
 	bool "Support cm_t335"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_PEPPER
 	bool "Support pepper"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_AM335X_IGEP0033
 	bool "Support am335x_igep0033"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_PCM051
 	bool "Support pcm051"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_DRACO
 	bool "Support draco"
@@ -370,11 +359,17 @@ config TARGET_PENGWYN
 	bool "Support pengwyn"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_AM335X_EVM
 	bool "Support am335x_evm"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_AM43XX_EVM
 	bool "Support am43xx_evm"
@@ -385,6 +380,8 @@ config TARGET_BAV335X
 	bool "Support bav335x"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
 	help
 	  The BAV335x OEM Network Processor integrates all the functions of an
 	  embedded network computer in a small, easy to use SODIMM module which
@@ -419,15 +416,26 @@ config TARGET_BCMNSP
 config ARCH_EXYNOS
 	bool "Samsung EXYNOS"
 	select CPU_V7
+	select DM
+	select DM_SPI_FLASH
+	select DM_SERIAL
+	select DM_SPI
+	select DM_GPIO
 
 config ARCH_S5PC1XX
 	bool "Samsung S5PC1XX"
 	select CPU_V7
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config ARCH_HIGHBANK
 	bool "Calxeda Highbank"
 	select CPU_V7
 
+config ARCH_INTEGRATOR
+	bool "ARM Ltd. Integrator family"
+
 config ARCH_KEYSTONE
 	bool "TI Keystone"
 	select CPU_V7
@@ -517,11 +525,20 @@ config TARGET_MX6QARM2
 config TARGET_MX6QSABREAUTO
 	bool "Support mx6qsabreauto"
 	select CPU_V7
+	select DM
+	select DM_THERMAL
 
 config TARGET_MX6SABRESD
 	bool "Support mx6sabresd"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_THERMAL
+
+config TARGET_MX6CUBOXI
+	bool "Support Solid-run mx6 boards"
+	select CPU_V7
+	select SUPPORT_SPL
 
 config TARGET_MX6SLEVK
 	bool "Support mx6slevk"
@@ -531,6 +548,8 @@ config TARGET_MX6SXSABRESD
 	bool "Support mx6sxsabresd"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_THERMAL
 
 config TARGET_GW_VENTANA
 	bool "Support gw_ventana"
@@ -591,16 +610,25 @@ config TARGET_CM_FX6
 	bool "Support cm_fx6"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_SOCFPGA_ARRIA5
 	bool "Support socfpga_arria5"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SPI_FLASH
+	select DM_SPI
 
 config TARGET_SOCFPGA_CYCLONE5
 	bool "Support socfpga_cyclone5"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
+	select DM_SPI_FLASH
+	select DM_SPI
 
 config ARCH_SUNXI
 	bool "Support sunxi (Allwinner) SoCs"
@@ -617,10 +645,15 @@ config TARGET_VF610TWR
 	bool "Support vf610twr"
 	select CPU_V7
 
-config ZYNQ
+config TARGET_COLIBRI_VF
+	bool "Support Colibri VF50/61"
+	select CPU_V7
+
+config ARCH_ZYNQ
 	bool "Xilinx Zynq Platform"
 	select CPU_V7
 	select SUPPORT_SPL
+	select DM
 
 config TARGET_XILINX_ZYNQMP
 	bool "Support Xilinx ZynqMP Platform"
@@ -632,6 +665,12 @@ config TEGRA
 	select SPL
 	select OF_CONTROL
 	select CPU_V7
+	select DM
+	select DM_SPI_FLASH
+	select DM_SERIAL
+	select DM_I2C
+	select DM_SPI
+	select DM_GPIO
 
 config TARGET_VEXPRESS64_AEMV8A
 	bool "Support vexpress_aemv8a"
@@ -656,6 +695,28 @@ config TARGET_LS2085A_SIMU
 	select ARM64
 	select ARMV8_MULTIENTRY
 
+config TARGET_LS2085AQDS
+	bool "Support ls2085aqds"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
+	help
+	  Support for Freescale LS2085AQDS platform
+	  The LS2085A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS2085A
+	  Layerscape Architecture processor.
+
+config TARGET_LS2085ARDB
+	bool "Support ls2085ardb"
+	select ARM64
+	select ARMV8_MULTIENTRY
+	select SUPPORT_SPL
+	help
+	  Support for Freescale LS2085ARDB platform.
+	  The LS2085A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS2085A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -726,6 +787,13 @@ config ARCH_UNIPHIER
 	select SUPPORT_SPL
 	select SPL
 	select OF_CONTROL
+	select DM
+	select DM_SERIAL
+	select DM_I2C
+
+config TARGET_STM32F429_DISCOVERY
+	bool "Support STM32F429 Discovery"
+	select CPU_V7M
 
 endchoice
 
@@ -739,6 +807,8 @@ source "arch/arm/cpu/armv7/exynos/Kconfig"
 
 source "arch/arm/mach-highbank/Kconfig"
 
+source "arch/arm/mach-integrator/Kconfig"
+
 source "arch/arm/mach-keystone/Kconfig"
 
 source "arch/arm/mach-kirkwood/Kconfig"
@@ -767,7 +837,7 @@ source "arch/arm/mach-uniphier/Kconfig"
 
 source "arch/arm/mach-versatile/Kconfig"
 
-source "arch/arm/cpu/armv7/zynq/Kconfig"
+source "arch/arm/mach-zynq/Kconfig"
 
 source "arch/arm/cpu/armv7/Kconfig"
 
@@ -784,7 +854,6 @@ source "board/Marvell/db-mv784mp-gp/Kconfig"
 source "board/Marvell/gplugd/Kconfig"
 source "board/altera/socfpga/Kconfig"
 source "board/armadeus/apf27/Kconfig"
-source "board/armltd/integrator/Kconfig"
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/bachmann/ot1200/Kconfig"
@@ -807,6 +876,8 @@ source "board/denx/m53evk/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls2085aqds/Kconfig"
+source "board/freescale/ls2085ardb/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
@@ -856,6 +927,7 @@ source "board/siemens/draco/Kconfig"
 source "board/siemens/pxm2/Kconfig"
 source "board/siemens/rut/Kconfig"
 source "board/silica/pengwyn/Kconfig"
+source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/solidrun/hummingboard/Kconfig"
 source "board/spear/spear300/Kconfig"
 source "board/spear/spear310/Kconfig"
@@ -864,6 +936,7 @@ source "board/spear/spear600/Kconfig"
 source "board/spear/x600/Kconfig"
 source "board/st-ericsson/snowball/Kconfig"
 source "board/st-ericsson/u8500/Kconfig"
+source "board/st/stm32f429-discovery/Kconfig"
 source "board/st/stv0991/Kconfig"
 source "board/sunxi/Kconfig"
 source "board/syteco/zmx25/Kconfig"
@@ -875,6 +948,7 @@ source "board/ti/ti814x/Kconfig"
 source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
+source "board/toradex/colibri_vf/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/trizepsiv/Kconfig"
 source "board/ttcontrol/vision2/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bd4749c..2a5620d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -55,6 +55,7 @@ machine-$(CONFIG_ORION5X)		+= orion5x
 machine-$(CONFIG_TEGRA)			+= tegra
 machine-$(CONFIG_ARCH_UNIPHIER)		+= uniphier
 machine-$(CONFIG_ARCH_VERSATILE)	+= versatile
+machine-$(CONFIG_ARCH_ZYNQ)		+= zynq
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 
diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S
index ec8e88d..0bb3441 100644
--- a/arch/arm/cpu/arm720t/start.S
+++ b/arch/arm/cpu/arm720t/start.S
@@ -9,7 +9,6 @@
 
 #include <asm-offsets.h>
 #include <config.h>
-#include <asm/hardware.h>
 
 /*
  *************************************************************************
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index d7956e5..eb8669b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -49,13 +49,6 @@ static const iomux_cfg_t iomux_boot[] = {
 	MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
 	MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
-#elif defined(CONFIG_MX28)
-	MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
-	MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
-	MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
-	MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
-	MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
-	MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
 #endif
 };
 
@@ -65,10 +58,10 @@ static uint8_t mxs_get_bootmode_index(void)
 	int i;
 	uint8_t masked;
 
+#if defined(CONFIG_MX23)
 	/* Setup IOMUX of bootmode pads to GPIO */
 	mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
 
-#if defined(CONFIG_MX23)
 	/* Setup bootmode pins as GPIO input */
 	gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
 	gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
@@ -83,21 +76,11 @@ static uint8_t mxs_get_bootmode_index(void)
 	bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
 	bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
 #elif defined(CONFIG_MX28)
-	/* Setup bootmode pins as GPIO input */
-	gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
-	gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
-	gpio_direction_input(MX28_PAD_LCD_D02__GPIO_1_2);
-	gpio_direction_input(MX28_PAD_LCD_D03__GPIO_1_3);
-	gpio_direction_input(MX28_PAD_LCD_D04__GPIO_1_4);
-	gpio_direction_input(MX28_PAD_LCD_D05__GPIO_1_5);
-
-	/* Read bootmode pads */
-	bootmode |= (gpio_get_value(MX28_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
-	bootmode |= (gpio_get_value(MX28_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
-	bootmode |= (gpio_get_value(MX28_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
-	bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
-	bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
-	bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
+	/* The global boot mode will be detected by ROM code and its value
+	 * is stored at the fixed address 0x00019BF0 in OCRAM.
+	 */
+#define GLOBAL_BOOT_MODE_ADDR 0x00019BF0
+	bootmode = __raw_readl(GLOBAL_BOOT_MODE_ADDR);
 #endif
 
 	for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
diff --git a/arch/arm/cpu/arm926ejs/spear/cpu.c b/arch/arm/cpu/arm926ejs/spear/cpu.c
index 697e094..1ce9db7 100644
--- a/arch/arm/cpu/arm926ejs/spear/cpu.c
+++ b/arch/arm/cpu/arm926ejs/spear/cpu.c
@@ -32,7 +32,7 @@ int arch_cpu_init(void)
 	periph_clk_cfg |= CONFIG_SPEAR_UART48M;
 	writel(periph_clk_cfg, &misc_p->periph_clk_cfg);
 #endif
-#if defined(CONFIG_DESIGNWARE_ETH)
+#if defined(CONFIG_ETH_DESIGNWARE)
 	periph1_clken |= MISC_ETHENB;
 #endif
 #if defined(CONFIG_DW_UDC)
diff --git a/arch/arm/cpu/arm946es/cpu.c b/arch/arm/cpu/arm946es/cpu.c
index e20e5a8..5d864b9 100644
--- a/arch/arm/cpu/arm946es/cpu.c
+++ b/arch/arm/cpu/arm946es/cpu.c
@@ -53,7 +53,7 @@ static void cache_flush (void)
 	asm ("mcr p15, 0, %0, c7, c6, 0": :"r" (i));
 }
 
-#ifndef CONFIG_INTEGRATOR
+#ifndef CONFIG_ARCH_INTEGRATOR
 
 __attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
 {
@@ -63,4 +63,4 @@ __attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
 		;
 }
 
-#endif	/* #ifdef CONFIG_INTEGRATOR */
+#endif	/* #ifdef CONFIG_ARCH_INTEGRATOR */
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 21fc03b..fcccd0c 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y	+= cache_v7.o
 obj-y	+= cpu.o cp15.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_SOCFPGA),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
@@ -56,4 +56,3 @@ obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
 obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_U8500) += u8500/
 obj-$(CONFIG_VF610) += vf610/
-obj-$(CONFIG_ZYNQ) += zynq/
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig
index bd7540a..f6084ac 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -65,19 +65,7 @@ endchoice
 config SYS_SOC
 	default "exynos"
 
-config DM
-	default y
-
-config DM_SERIAL
-	default y
-
-config DM_SPI
-	default y
-
-config DM_SPI_FLASH
-	default y
-
-config DM_GPIO
+config DM_USB
 	default y
 
 source "board/samsung/smdkv310/Kconfig"
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 8f80c61..7a337e1 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -20,7 +20,7 @@ void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
@@ -74,7 +74,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_be32(&ifc_regs->ifc_ccr);
+	ccr = in_be32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index fef2231..653d58e 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -514,17 +514,21 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		/* MR2 */
 		val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
 		      ((tcwl - 3) & 3) << 3;
+		debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
 		mmdc0->mdscr = MR(val, 2, 3, cs);
 		/* MR3 */
+		debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
 		mmdc0->mdscr = MR(0, 3, 3, cs);
 		/* MR1 */
 		val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
 		      ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
+		debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
 		mmdc0->mdscr = MR(val, 1, 3, cs);
 		/* MR0 */
 		val = ((tcl - 1) << 4) |	/* CAS */
 		      (1 << 8)   |		/* DLL Reset */
 		      ((twr - 3) << 9);		/* Write Recovery */
+		debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
 		mmdc0->mdscr = MR(val, 0, 3, cs);
 		/* ZQ calibration */
 		val = (1 << 10);
@@ -535,10 +539,11 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mmdc0->mdpdc = (tcke & 0x7) << 16 |
 			5            << 12 |  /* PWDT_1: 256 cycles */
 			5            <<  8 |  /* PWDT_0: 256 cycles */
-			1            <<  7 |  /* SLOW_PD */
 			1            <<  6 |  /* BOTH_CS_PD */
 			(tcksrx & 0x7) << 3 |
 			(tcksre & 0x7);
+	if (!sysinfo->pd_fast_exit)
+		mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
 	mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
 
 	/* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c
index 17500f2..bbc6bed 100644
--- a/arch/arm/cpu/armv7/omap-common/boot-common.c
+++ b/arch/arm/cpu/armv7/omap-common/boot-common.c
@@ -159,6 +159,16 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 void arch_preboot_os(void)
 {
-	ahci_reset(DWC_AHSATA_BASE);
+	ahci_reset((void __iomem *)DWC_AHSATA_BASE);
+}
+#endif
+
+#if defined(CONFIG_CMD_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE)
+int fb_set_reboot_flag(void)
+{
+	printf("Setting reboot to fastboot flag ...\n");
+	setenv("dofastboot", "1");
+	saveenv();
+	return 0;
 }
 #endif
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
index d18bc50..2c2d1bc 100644
--- a/arch/arm/cpu/armv7/omap-common/sata.c
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -69,7 +69,7 @@ int init_sata(int dev)
 	val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
 	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
 
-	ret = ahci_init(DWC_AHSATA_BASE);
+	ret = ahci_init((void __iomem *)DWC_AHSATA_BASE);
 
 	return ret;
 }
@@ -88,6 +88,6 @@ void scsi_init(void)
 
 void scsi_bus_reset(void)
 {
-	ahci_reset(DWC_AHSATA_BASE);
-	ahci_init(DWC_AHSATA_BASE);
+	ahci_reset((void __iomem *)DWC_AHSATA_BASE);
+	ahci_init((void __iomem *)DWC_AHSATA_BASE);
 }
diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c
index 1696c2d..df5f817 100644
--- a/arch/arm/cpu/armv7/omap-common/utils.c
+++ b/arch/arm/cpu/armv7/omap-common/utils.c
@@ -60,3 +60,16 @@ void __weak usb_fake_mac_from_die_id(u32 *id)
 		eth_setenv_enetaddr("usbethaddr", device_mac);
 	}
 }
+
+void __weak usb_set_serial_num_from_die_id(u32 *id)
+{
+	char serialno[72];
+	uint32_t serialno_lo, serialno_hi;
+
+	if (!getenv("serial#")) {
+		serialno_hi = id[0];
+		serialno_lo = id[1];
+		sprintf(serialno, "%08x%08x", serialno_hi, serialno_lo);
+		setenv("serial#", serialno);
+	}
+}
diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig
index 1f96498..cc82c50 100644
--- a/arch/arm/cpu/armv7/omap3/Kconfig
+++ b/arch/arm/cpu/armv7/omap3/Kconfig
@@ -17,6 +17,9 @@ config TARGET_OMAP3_SDP3430
 config TARGET_OMAP3_BEAGLE
 	bool "TI OMAP3 BeagleBoard"
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_CM_T35
 	bool "CompuLab CM-T3530 and CM-T3730 boards"
@@ -28,6 +31,9 @@ config TARGET_CM_T3517
 config TARGET_DEVKIT8000
 	bool "TimLL OMAP3 Devkit8000"
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_OMAP3_EVM
 	bool "TI OMAP3 EVM"
@@ -44,13 +50,22 @@ config TARGET_OMAP3_EVM_QUICK_NAND
 config TARGET_OMAP3_IGEP00X0
 	bool "IGEP"
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_OMAP3_OVERO
 	bool "OMAP35xx Gumstix Overo"
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_OMAP3_ZOOM1
 	bool "TI Zoom1"
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_AM3517_CRANE
 	bool "am3517_crane"
@@ -94,18 +109,12 @@ config TARGET_TWISTER
 config TARGET_OMAP3_CAIRO
 	bool "QUIPOS CAIRO"
 	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 endchoice
 
-config DM
-	default y
-
-config DM_GPIO
-	default y if DM
-
-config DM_SERIAL
-	default y if DM
-
 config SYS_SOC
 	default "omap3"
 
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index e4abb25..868415d 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -460,7 +460,7 @@ void enable_basic_clocks(void)
 		(*prcm)->cm_l4per_gpio6_clkctrl,
 		(*prcm)->cm_l4per_gpio7_clkctrl,
 		(*prcm)->cm_l4per_gpio8_clkctrl,
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 		(*prcm)->cm_l3init_ocp2scp1_clkctrl,
 		(*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 #endif
@@ -495,7 +495,7 @@ void enable_basic_clocks(void)
 	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
-#ifdef CONFIG_USB_DWC3
+#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
 	/* Enable 960 MHz clock for dwc3 */
 	setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
 		     OPTFCLKEN_REFCLK960M);
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 440bb40..f80d36d 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -440,6 +440,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C158,
+	.control_std_fuse_die_id_0		= 0x4AE0C200,
+	.control_std_fuse_die_id_1		= 0x4AE0C208,
+	.control_std_fuse_die_id_2		= 0x4AE0C20C,
+	.control_std_fuse_die_id_3		= 0x4AE0C210,
 	.control_padconf_mode			= 0x4AE0C5A0,
 	.control_xtal_oscillator		= 0x4AE0C5A4,
 	.control_i2c_2				= 0x4AE0C5A8,
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig
index 2b333a3..57dccec 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -8,24 +8,36 @@ config TARGET_ARMADILLO_800EVA
 
 config TARGET_GOSE
 	bool "Gose board"
+	select DM
+	select DM_SERIAL
 
 config TARGET_KOELSCH
 	bool "Koelsch board"
+	select DM
+	select DM_SERIAL
 
 config TARGET_LAGER
 	bool "Lager board"
+	select DM
+	select DM_SERIAL
 
 config TARGET_KZM9G
 	bool "KZM9D board"
 
 config TARGET_ALT
 	bool "Alt board"
+	select DM
+	select DM_SERIAL
 
 config TARGET_SILK
 	bool "Silk board"
+	select DM
+	select DM_SERIAL
 
 config TARGET_PORTER
 	bool "Porter board"
+	select DM
+	select DM_SERIAL
 
 endchoice
 
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index 8b6e108..7524ef9 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -7,7 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	:= lowlevel_init.o
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
 	   fpga_manager.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o scan_manager.o
diff --git a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S b/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
deleted file mode 100644
index b4d0627..0000000
--- a/arch/arm/cpu/armv7/socfpga/lowlevel_init.S
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-
-/* Set up the platform, once the cpu has been initialized */
-.globl lowlevel_init
-lowlevel_init:
-
-	/* Remap */
-#ifdef CONFIG_SPL_BUILD
-	/*
-	 * SPL : configure the remap (L3 NIC-301 GPV)
-	 * so the on-chip RAM at lower memory instead ROM.
-	 */
-	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
-	mov	r1, #0x19
-	str	r1, [r0]
-#else
-	/*
-	 * U-Boot : configure the remap (L3 NIC-301 GPV)
-	 * so the SDRAM at lower memory instead on-chip RAM.
-	 */
-	ldr	r0, =SOCFPGA_L3REGS_ADDRESS
-	mov	r1, #0x2
-	str	r1, [r0]
-
-	/* Private components security */
-
-	/*
-	 * U-Boot : configure private timer, global timer and cpu
-	 * component access as non secure for kernel stage (as required
-	 * by kernel)
-	 */
-	mrc	p15,4,r0,c15,c0,0
-	add	r1, r0, #0x54
-	ldr	r2, [r1]
-	orr	r2, r2, #0xff
-	orr	r2, r2, #0xf00
-	str	r2, [r1]
-#endif	/* #ifdef CONFIG_SPL_BUILD */
-	mov	pc, lr
diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index 7873c38..0f8b4d0 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -49,7 +49,7 @@ void enable_caches(void)
 /*
  * DesignWare Ethernet initialization
  */
-#ifdef CONFIG_DESIGNWARE_ETH
+#ifdef CONFIG_ETH_DESIGNWARE
 int cpu_eth_init(bd_t *bis)
 {
 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
diff --git a/arch/arm/cpu/armv7/socfpga/reset_manager.c b/arch/arm/cpu/armv7/socfpga/reset_manager.c
index 25921e7..45b352b 100644
--- a/arch/arm/cpu/armv7/socfpga/reset_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/reset_manager.c
@@ -113,3 +113,27 @@ void socfpga_spim_enable(void)
 	clrbits_le32(reset, (1 << RSTMGR_PERMODRST_SPIM0_LSB) |
 		     (1 << RSTMGR_PERMODRST_SPIM1_LSB));
 }
+
+/* Bring UART0 out of reset. */
+void socfpga_uart0_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_UART0_LSB);
+}
+
+/* Bring SDRAM controller out of reset. */
+void socfpga_sdram_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_SDR_LSB);
+}
+
+/* Bring OSC1 timer out of reset. */
+void socfpga_osc1timer_enable(void)
+{
+	const void *reset = &reset_manager_base->per_mod_reset;
+
+	clrbits_le32(reset, 1 << RSTMGR_PERMODRST_OSC1TIMER0_LSB);
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 6a8c15d..f994658 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -6,6 +6,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -15,9 +16,13 @@
 #include <asm/arch/freeze_controller.h>
 #include <asm/arch/clock_manager.h>
 #include <asm/arch/scan_manager.h>
+#include <asm/arch/sdram.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static struct pl310_regs *const pl310 =
+	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
 #define MAIN_VCO_BASE (					\
 	(CONFIG_HPS_MAINPLLGRP_VCO_DENOM <<		\
 		CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) |	\
@@ -43,6 +48,31 @@ DECLARE_GLOBAL_DATA_PTR;
 		CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET)	\
 	)
 
+void board_init_f(ulong dummy)
+{
+	struct socfpga_system_manager *sysmgr_regs =
+		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+	unsigned long reg;
+	/*
+	 * First C code to run. Clear fake OCRAM ECC first as SBE
+	 * and DBE might triggered during power on
+	 */
+	reg = readl(&sysmgr_regs->eccgrp_ocram);
+	if (reg & SYSMGR_ECC_OCRAM_SERR)
+		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
+		       &sysmgr_regs->eccgrp_ocram);
+	if (reg & SYSMGR_ECC_OCRAM_DERR)
+		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
+		       &sysmgr_regs->eccgrp_ocram);
+
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* Remap SDRAM to 0x0 */
+	writel(0x1, &pl310->pl310_addr_filter_start);
+
+	board_init_r(NULL, 0);
+}
+
 u32 spl_boot_device(void)
 {
 	return BOOT_DEVICE_RAM;
@@ -53,6 +83,7 @@ u32 spl_boot_device(void)
  */
 void spl_board_init(void)
 {
+	unsigned long sdram_size;
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
 	cm_config_t cm_default_cfg = {
 		/* main group */
@@ -144,10 +175,19 @@ void spl_board_init(void)
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
+	socfpga_sdram_enable();
+	socfpga_uart0_enable();
+	socfpga_osc1timer_enable();
+
+	timer_init();
+
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);
 
+	/* Enable bootrom to configure IOs. */
+	sysmgr_enable_warmrstcfgio();
+
 	/* configure the IOCSR / IO buffer settings */
 	if (scan_mgr_configure_iocsr())
 		hang();
@@ -165,4 +205,25 @@ void spl_board_init(void)
 
 	/* enable console uart printing */
 	preloader_console_init();
+
+	if (sdram_mmr_init_full(0xffffffff) != 0) {
+		puts("SDRAM init failed.\n");
+		hang();
+	}
+
+	debug("SDRAM: Calibrating PHY\n");
+	/* SDRAM calibration */
+	if (sdram_calibration_full() == 0) {
+		puts("SDRAM calibration failed.\n");
+		hang();
+	}
+
+	sdram_size = sdram_calculate_size();
+	debug("SDRAM: %ld MiB\n", sdram_size >> 20);
+
+	/* Sanity check ensure correct SDRAM size specified */
+	if (get_ram_size(0, sdram_size) != sdram_size) {
+		puts("SDRAM size check failed!\n");
+		hang();
+	}
 }
diff --git a/arch/arm/cpu/armv7/socfpga/system_manager.c b/arch/arm/cpu/armv7/socfpga/system_manager.c
index 11f7bad..8126e0d 100644
--- a/arch/arm/cpu/armv7/socfpga/system_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/system_manager.c
@@ -66,3 +66,12 @@ void sysmgr_pinmux_init(void)
 
 	populate_sysmgr_fpgaintf_module();
 }
+
+/*
+ * This bit allows the bootrom to configure the IOs after a warm reset.
+ */
+void sysmgr_enable_warmrstcfgio(void)
+{
+	setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
+		     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
+}
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index c02c015..c1b4cf5 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,28 +46,33 @@ static int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
 	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
+#if defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
+#else
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX);
+#endif
 	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
 	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
 	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
 #else
 #error Unsupported console port number. Please fix pin mux settings in board.c
diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c
index b00befb..f115a9c 100644
--- a/arch/arm/cpu/armv7/sunxi/rsb.c
+++ b/arch/arm/cpu/armv7/sunxi/rsb.c
@@ -21,15 +21,15 @@ static int rsb_set_device_mode(void);
 static void rsb_cfg_io(void)
 {
 #ifdef CONFIG_MACH_SUN8I
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
+	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
 	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
 	sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
 	sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
 	sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
 #elif defined CONFIG_MACH_SUN9I
-	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
-	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
+	sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN_R_RSB);
+	sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN_R_RSB);
 	sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
 	sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
 	sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
diff --git a/arch/arm/cpu/armv7/sunxi/usbc.c b/arch/arm/cpu/armv7/sunxi/usbc.c
index 524f25c..a0e9604 100644
--- a/arch/arm/cpu/armv7/sunxi/usbc.c
+++ b/arch/arm/cpu/armv7/sunxi/usbc.c
@@ -41,6 +41,7 @@ static struct sunxi_usbc_hcd {
 	int usb_rst_mask;
 	int ahb_clk_mask;
 	int gpio_vbus;
+	int gpio_vbus_det;
 	int irq;
 	int id;
 } sunxi_usbc_hcd[] = {
@@ -80,12 +81,6 @@ static struct sunxi_usbc_hcd {
 
 static int enabled_hcd_count;
 
-static bool use_axp_drivebus(int index)
-{
-	return index == 0 &&
-	       strcmp(CONFIG_USB0_VBUS_PIN, "axp_drivebus") == 0;
-}
-
 void *sunxi_usbc_get_io_base(int index)
 {
 	switch (index) {
@@ -102,9 +97,6 @@ void *sunxi_usbc_get_io_base(int index)
 
 static int get_vbus_gpio(int index)
 {
-	if (use_axp_drivebus(index))
-		return -1;
-
 	switch (index) {
 	case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
 	case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
@@ -113,6 +105,14 @@ static int get_vbus_gpio(int index)
 	return -1;
 }
 
+static int get_vbus_detect_gpio(int index)
+{
+	switch (index) {
+	case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
+	}
+	return -1;
+}
+
 static void usb_phy_write(struct sunxi_usbc_hcd *sunxi_usbc, int addr,
 			  int data, int len)
 {
@@ -192,22 +192,35 @@ void sunxi_usbc_enable_squelch_detect(int index, int enable)
 int sunxi_usbc_request_resources(int index)
 {
 	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+	int ret = 0;
 
 	sunxi_usbc->gpio_vbus = get_vbus_gpio(index);
-	if (sunxi_usbc->gpio_vbus != -1)
-		return gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
+	if (sunxi_usbc->gpio_vbus != -1) {
+		ret |= gpio_request(sunxi_usbc->gpio_vbus, "usbc_vbus");
+		ret |= gpio_direction_output(sunxi_usbc->gpio_vbus, 0);
+	}
+
+	sunxi_usbc->gpio_vbus_det = get_vbus_detect_gpio(index);
+	if (sunxi_usbc->gpio_vbus_det != -1) {
+		ret |= gpio_request(sunxi_usbc->gpio_vbus_det, "usbc_vbus_det");
+		ret |= gpio_direction_input(sunxi_usbc->gpio_vbus_det);
+	}
 
-	return 0;
+	return ret;
 }
 
 int sunxi_usbc_free_resources(int index)
 {
 	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+	int ret = 0;
 
 	if (sunxi_usbc->gpio_vbus != -1)
-		return gpio_free(sunxi_usbc->gpio_vbus);
+		ret |= gpio_free(sunxi_usbc->gpio_vbus);
 
-	return 0;
+	if (sunxi_usbc->gpio_vbus_det != -1)
+		ret |= gpio_free(sunxi_usbc->gpio_vbus_det);
+
+	return ret;
 }
 
 void sunxi_usbc_enable(int index)
@@ -258,22 +271,38 @@ void sunxi_usbc_vbus_enable(int index)
 {
 	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
 
-#ifdef AXP_DRIVEBUS
-	if (use_axp_drivebus(index))
-		axp_drivebus_enable();
-#endif
 	if (sunxi_usbc->gpio_vbus != -1)
-		gpio_direction_output(sunxi_usbc->gpio_vbus, 1);
+		gpio_set_value(sunxi_usbc->gpio_vbus, 1);
 }
 
 void sunxi_usbc_vbus_disable(int index)
 {
 	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
 
-#ifdef AXP_DRIVEBUS
-	if (use_axp_drivebus(index))
-		axp_drivebus_disable();
-#endif
 	if (sunxi_usbc->gpio_vbus != -1)
-		gpio_direction_output(sunxi_usbc->gpio_vbus, 0);
+		gpio_set_value(sunxi_usbc->gpio_vbus, 0);
+}
+
+int sunxi_usbc_vbus_detect(int index)
+{
+	struct sunxi_usbc_hcd *sunxi_usbc = &sunxi_usbc_hcd[index];
+	int err, retries = 3;
+
+	if (sunxi_usbc->gpio_vbus_det == -1) {
+		eprintf("Error: invalid vbus detection pin\n");
+		return -1;
+	}
+
+	err = gpio_get_value(sunxi_usbc->gpio_vbus_det);
+	/*
+	 * Vbus may have been provided by the board and just been turned of
+	 * some milliseconds ago on reset, what we're measuring then is a
+	 * residual charge on Vbus, sleep a bit and try again.
+	 */
+	while (err > 0 && retries--) {
+		mdelay(100);
+		err = gpio_get_value(sunxi_usbc->gpio_vbus_det);
+	}
+
+	return err;
 }
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index 92aaad9..1bb9b8e 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -18,6 +18,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
+static char soc_type[] = "xx0";
+
 #ifdef CONFIG_MXC_OCOTP
 void enable_ocotp_clk(unsigned char enable)
 {
@@ -284,14 +286,37 @@ static char *get_reset_cause(void)
 
 int print_cpuinfo(void)
 {
-	printf("CPU:   Freescale Vybrid VF610 at %d MHz\n",
-		mxc_get_clock(MXC_ARM_CLK) / 1000000);
+	printf("CPU: Freescale Vybrid VF%s at %d MHz\n",
+	       soc_type, mxc_get_clock(MXC_ARM_CLK) / 1000000);
 	printf("Reset cause: %s\n", get_reset_cause());
 
 	return 0;
 }
 #endif
 
+int arch_cpu_init(void)
+{
+	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
+
+	soc_type[0] = mscm->cpxcount ? '6' : '5'; /*Dual Core => VF6x0 */
+	soc_type[1] = mscm->cpxcfg1 ? '1' : '0'; /* L2 Cache => VFx10 */
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+	char soc[6];
+
+	strcat(soc, "vf");
+	strcat(soc, soc_type);
+	setenv("soc", soc);
+
+	return 0;
+}
+#endif
+
 int cpu_eth_init(bd_t *bis)
 {
 	int rc = -ENODEV;
@@ -317,3 +342,19 @@ int get_clocks(void)
 #endif
 	return 0;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+	enum dcache_option option = DCACHE_WRITETHROUGH;
+#else
+	enum dcache_option option = DCACHE_WRITEBACK;
+#endif
+	dcache_enable();
+	icache_enable();
+
+    /* Enable caching on OCRAM */
+	mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option);
+}
+#endif
diff --git a/arch/arm/cpu/armv7/zynq/config.mk b/arch/arm/cpu/armv7/zynq/config.mk
deleted file mode 100644
index 778a377..0000000
--- a/arch/arm/cpu/armv7/zynq/config.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
-#
-# SPDX-License-Identifier:      GPL-2.0
-#
-# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain)
-PLATFORM_RELFLAGS += -mfpu=neon
diff --git a/arch/arm/cpu/armv7m/Makefile b/arch/arm/cpu/armv7m/Makefile
new file mode 100644
index 0000000..b662e03
--- /dev/null
+++ b/arch/arm/cpu/armv7m/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+extra-y := start.o
+obj-y += cpu.o
+
+obj-$(CONFIG_STM32F4) += stm32f4/
diff --git a/arch/arm/cpu/armv7m/config.mk b/arch/arm/cpu/armv7m/config.mk
new file mode 100644
index 0000000..0b31e44
--- /dev/null
+++ b/arch/arm/cpu/armv7m/config.mk
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2015
+# Kamil Lulko, <rev13@wp.pl>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+PLATFORM_CPPFLAGS += -march=armv7-m -mthumb
diff --git a/arch/arm/cpu/armv7m/cpu.c b/arch/arm/cpu/armv7m/cpu.c
new file mode 100644
index 0000000..d3ab862
--- /dev/null
+++ b/arch/arm/cpu/armv7m/cpu.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010,2011
+ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+/*
+ * This is called right before passing control to
+ * the Linux kernel point.
+ */
+int cleanup_before_linux(void)
+{
+	return 0;
+}
+
+/*
+ * Perform the low-level reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/*
+	 * Perform reset but keep priority group unchanged.
+	 */
+	writel((V7M_AIRCR_VECTKEY << V7M_AIRCR_VECTKEY_SHIFT)
+		| (V7M_SCB->aircr & V7M_AIRCR_PRIGROUP_MSK)
+		| V7M_AIRCR_SYSRESET, &V7M_SCB->aircr);
+}
diff --git a/arch/arm/cpu/armv7m/start.S b/arch/arm/cpu/armv7m/start.S
new file mode 100644
index 0000000..e05e984
--- /dev/null
+++ b/arch/arm/cpu/armv7m/start.S
@@ -0,0 +1,15 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl	reset
+.type reset, %function
+reset:
+	b	_main
+
+.globl	c_runtime_cpu_setup
+c_runtime_cpu_setup:
+	mov	pc, lr
diff --git a/arch/arm/cpu/armv7m/stm32f4/Makefile b/arch/arm/cpu/armv7m/stm32f4/Makefile
new file mode 100644
index 0000000..e982830
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f4/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2015
+# Kamil Lulko, <rev13@wp.pl>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += soc.o clock.o timer.o flash.o
diff --git a/arch/arm/cpu/armv7m/stm32f4/clock.c b/arch/arm/cpu/armv7m/stm32f4/clock.c
new file mode 100644
index 0000000..2eded1f
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f4/clock.c
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * (C) Copyright 2014
+ * STMicroelectronics
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+#define RCC_CR_HSION		(1 << 0)
+#define RCC_CR_HSEON		(1 << 16)
+#define RCC_CR_HSERDY		(1 << 17)
+#define RCC_CR_HSEBYP		(1 << 18)
+#define RCC_CR_CSSON		(1 << 19)
+#define RCC_CR_PLLON		(1 << 24)
+#define RCC_CR_PLLRDY		(1 << 25)
+
+#define RCC_PLLCFGR_PLLM_MASK	0x3F
+#define RCC_PLLCFGR_PLLN_MASK	0x7FC0
+#define RCC_PLLCFGR_PLLP_MASK	0x30000
+#define RCC_PLLCFGR_PLLQ_MASK	0xF000000
+#define RCC_PLLCFGR_PLLSRC	(1 << 22)
+#define RCC_PLLCFGR_PLLN_SHIFT	6
+#define RCC_PLLCFGR_PLLP_SHIFT	16
+#define RCC_PLLCFGR_PLLQ_SHIFT	24
+
+#define RCC_CFGR_AHB_PSC_MASK	0xF0
+#define RCC_CFGR_APB1_PSC_MASK	0x1C00
+#define RCC_CFGR_APB2_PSC_MASK	0xE000
+#define RCC_CFGR_SW0		(1 << 0)
+#define RCC_CFGR_SW1		(1 << 1)
+#define RCC_CFGR_SW_MASK	0x3
+#define RCC_CFGR_SW_HSI		0
+#define RCC_CFGR_SW_HSE		RCC_CFGR_SW0
+#define RCC_CFGR_SW_PLL		RCC_CFGR_SW1
+#define RCC_CFGR_SWS0		(1 << 2)
+#define RCC_CFGR_SWS1		(1 << 3)
+#define RCC_CFGR_SWS_MASK	0xC
+#define RCC_CFGR_SWS_HSI	0
+#define RCC_CFGR_SWS_HSE	RCC_CFGR_SWS0
+#define RCC_CFGR_SWS_PLL	RCC_CFGR_SWS1
+#define RCC_CFGR_HPRE_SHIFT	4
+#define RCC_CFGR_PPRE1_SHIFT	10
+#define RCC_CFGR_PPRE2_SHIFT	13
+
+#define RCC_APB1ENR_PWREN	(1 << 28)
+
+#define PWR_CR_VOS0		(1 << 14)
+#define PWR_CR_VOS1		(1 << 15)
+#define PWR_CR_VOS_MASK		0xC000
+#define PWR_CR_VOS_SCALE_MODE_1	(PWR_CR_VOS0 | PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_2	(PWR_CR_VOS1)
+#define PWR_CR_VOS_SCALE_MODE_3	(PWR_CR_VOS0)
+
+#define FLASH_ACR_WS(n)		n
+#define FLASH_ACR_PRFTEN	(1 << 8)
+#define FLASH_ACR_ICEN		(1 << 9)
+#define FLASH_ACR_DCEN		(1 << 10)
+
+struct pll_psc {
+	u8	pll_m;
+	u16	pll_n;
+	u8	pll_p;
+	u8	pll_q;
+	u8	ahb_psc;
+	u8	apb1_psc;
+	u8	apb2_psc;
+};
+
+#define AHB_PSC_1		0
+#define AHB_PSC_2		0x8
+#define AHB_PSC_4		0x9
+#define AHB_PSC_8		0xA
+#define AHB_PSC_16		0xB
+#define AHB_PSC_64		0xC
+#define AHB_PSC_128		0xD
+#define AHB_PSC_256		0xE
+#define AHB_PSC_512		0xF
+
+#define APB_PSC_1		0
+#define APB_PSC_2		0x4
+#define APB_PSC_4		0x5
+#define APB_PSC_8		0x6
+#define APB_PSC_16		0x7
+
+#if !defined(CONFIG_STM32_HSE_HZ)
+#error "CONFIG_STM32_HSE_HZ not defined!"
+#else
+#if (CONFIG_STM32_HSE_HZ == 8000000)
+struct pll_psc pll_psc_168 = {
+	.pll_m = 8,
+	.pll_n = 336,
+	.pll_p = 2,
+	.pll_q = 7,
+	.ahb_psc = AHB_PSC_1,
+	.apb1_psc = APB_PSC_4,
+	.apb2_psc = APB_PSC_2
+};
+#else
+#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
+#endif
+#endif
+
+int configure_clocks(void)
+{
+	/* Reset RCC configuration */
+	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
+	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
+	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
+		| RCC_CR_PLLON));
+	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
+	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
+	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
+
+	/* Configure for HSE+PLL operation */
+	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
+	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
+		;
+
+	/* Enable high performance mode, System frequency up to 168 MHz */
+	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
+	writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
+
+	setbits_le32(&STM32_RCC->cfgr, ((
+		pll_psc_168.ahb_psc << RCC_CFGR_HPRE_SHIFT)
+		| (pll_psc_168.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
+		| (pll_psc_168.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
+
+	writel(pll_psc_168.pll_m
+		| (pll_psc_168.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
+		| (((pll_psc_168.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
+		| (pll_psc_168.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
+		&STM32_RCC->pllcfgr);
+	setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
+
+	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
+
+	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
+		;
+
+	/* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */
+	writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN
+		| FLASH_ACR_DCEN, &STM32_FLASH->acr);
+
+	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
+	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
+
+	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
+			RCC_CFGR_SWS_PLL)
+		;
+
+	return 0;
+}
+
+unsigned long clock_get(enum clock clck)
+{
+	u32 sysclk = 0;
+	u32 shift = 0;
+	/* Prescaler table lookups for clock computation */
+	u8 ahb_psc_table[16] = {
+		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
+	};
+	u8 apb_psc_table[8] = {
+		0, 0, 0, 0, 1, 2, 3, 4
+	};
+
+	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
+			RCC_CFGR_SWS_PLL) {
+		u16 pllm, plln, pllp;
+		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
+		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
+			>> RCC_PLLCFGR_PLLN_SHIFT);
+		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
+			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
+		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
+	}
+
+	switch (clck) {
+	case CLOCK_CORE:
+		return sysclk;
+		break;
+	case CLOCK_AHB:
+		shift = ahb_psc_table[(
+			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
+			>> RCC_CFGR_HPRE_SHIFT)];
+		return sysclk >>= shift;
+		break;
+	case CLOCK_APB1:
+		shift = apb_psc_table[(
+			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
+			>> RCC_CFGR_PPRE1_SHIFT)];
+		return sysclk >>= shift;
+		break;
+	case CLOCK_APB2:
+		shift = apb_psc_table[(
+			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
+			>> RCC_CFGR_PPRE2_SHIFT)];
+		return sysclk >>= shift;
+		break;
+	default:
+		return 0;
+		break;
+	}
+}
diff --git a/arch/arm/cpu/armv7m/stm32f4/flash.c b/arch/arm/cpu/armv7m/stm32f4/flash.c
new file mode 100644
index 0000000..e5c6111
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f4/flash.c
@@ -0,0 +1,143 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/stm32.h>
+
+#define STM32_FLASH_KEY1	0x45670123
+#define STM32_FLASH_KEY2	0xCDEF89AB
+
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+
+const u32 sect_sz_kb[CONFIG_SYS_MAX_FLASH_SECT] = {
+	[0 ... 3] =	16 * 1024,
+	[4] =		64 * 1024,
+	[5 ... 11] =	128 * 1024
+};
+
+static void stm32f4_flash_lock(u8 lock)
+{
+	if (lock) {
+		setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_LOCK);
+	} else {
+		writel(STM32_FLASH_KEY1, &STM32_FLASH->key);
+		writel(STM32_FLASH_KEY2, &STM32_FLASH->key);
+	}
+}
+
+unsigned long flash_init(void)
+{
+	unsigned long total_size = 0;
+	u8 i, j;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		flash_info[i].flash_id = FLASH_STM32F4;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+		flash_info[i].size = sect_sz_kb[0];
+		for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
+			flash_info[i].start[j] = flash_info[i].start[j - 1]
+				+ (sect_sz_kb[j - 1]);
+			flash_info[i].size += sect_sz_kb[j];
+		}
+		total_size += flash_info[i].size;
+	}
+
+	return total_size;
+}
+
+void flash_print_info(flash_info_t *info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	} else if (info->flash_id == FLASH_STM32F4) {
+		printf("STM32F4 Embedded Flash\n");
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n",
+	       info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s",
+		       info->start[i],
+			info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+	return;
+}
+
+int flash_erase(flash_info_t *info, int first, int last)
+{
+	u8 bank = 0xFF;
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		if (info == &flash_info[i]) {
+			bank = i;
+			break;
+		}
+	}
+	if (bank == 0xFF)
+		return -1;
+
+	stm32f4_flash_lock(0);
+
+	for (i = first; i <= last; i++) {
+		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+			;
+
+		if (bank == 0) {
+			setbits_le32(&STM32_FLASH->cr,
+				     (i << STM32_FLASH_CR_SNB_OFFSET));
+		} else if (bank == 1) {
+			setbits_le32(&STM32_FLASH->cr,
+				     ((0x10 | i) << STM32_FLASH_CR_SNB_OFFSET));
+		} else {
+			stm32f4_flash_lock(1);
+			return -1;
+		}
+		setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
+		setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_STRT);
+
+		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+			;
+
+		clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
+		stm32f4_flash_lock(1);
+	}
+
+	return 0;
+}
+
+int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+	ulong i;
+
+	while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+		;
+
+	stm32f4_flash_lock(0);
+
+	setbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
+	/* To make things simple use byte writes only */
+	for (i = 0; i < cnt; i++) {
+		*(uchar *)(addr + i) = src[i];
+		while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
+			;
+	}
+	clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_PG);
+	stm32f4_flash_lock(1);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7m/stm32f4/soc.c b/arch/arm/cpu/armv7m/stm32f4/soc.c
new file mode 100644
index 0000000..202a126
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f4/soc.c
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+
+u32 get_cpu_rev(void)
+{
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	configure_clocks();
+
+	/*
+	 * Configure the memory protection unit (MPU) to allow full access to
+	 * the whole 4GB address space.
+	 */
+	writel(0, &V7M_MPU->rnr);
+	writel(0, &V7M_MPU->rbar);
+	writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB
+		| V7M_MPU_RASR_EN), &V7M_MPU->rasr);
+	writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl);
+
+	return 0;
+}
+
+void s_init(void)
+{
+}
diff --git a/arch/arm/cpu/armv7m/stm32f4/timer.c b/arch/arm/cpu/armv7m/stm32f4/timer.c
new file mode 100644
index 0000000..102ae6d
--- /dev/null
+++ b/arch/arm/cpu/armv7m/stm32f4/timer.c
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+#include <asm/arch/stm32.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define STM32_TIM2_BASE	(STM32_APB1PERIPH_BASE + 0x0000)
+
+#define RCC_APB1ENR_TIM2EN	(1 << 0)
+
+struct stm32_tim2_5 {
+	u32 cr1;
+	u32 cr2;
+	u32 smcr;
+	u32 dier;
+	u32 sr;
+	u32 egr;
+	u32 ccmr1;
+	u32 ccmr2;
+	u32 ccer;
+	u32 cnt;
+	u32 psc;
+	u32 arr;
+	u32 reserved1;
+	u32 ccr1;
+	u32 ccr2;
+	u32 ccr3;
+	u32 ccr4;
+	u32 reserved2;
+	u32 dcr;
+	u32 dmar;
+	u32 or;
+};
+
+#define TIM_CR1_CEN	(1 << 0)
+
+#define TIM_EGR_UG	(1 << 0)
+
+int timer_init(void)
+{
+	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
+
+	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
+
+	if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1))
+		writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1,
+		       &tim->psc);
+	else
+		writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1,
+		       &tim->psc);
+
+	writel(0xFFFFFFFF, &tim->arr);
+	writel(TIM_CR1_CEN, &tim->cr1);
+	setbits_le32(&tim->egr, TIM_EGR_UG);
+
+	gd->arch.tbl = 0;
+	gd->arch.tbu = 0;
+	gd->arch.lastinc = 0;
+
+	return 0;
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base;
+}
+
+unsigned long long get_ticks(void)
+{
+	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
+	u32 now;
+
+	now = readl(&tim->cnt);
+
+	if (now >= gd->arch.lastinc)
+		gd->arch.tbl += (now - gd->arch.lastinc);
+	else
+		gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now;
+
+	gd->arch.lastinc = now;
+
+	return gd->arch.tbl;
+}
+
+void reset_timer(void)
+{
+	struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE;
+
+	gd->arch.lastinc = readl(&tim->cnt);
+	gd->arch.tbl = 0;
+}
+
+/* delay x useconds */
+void __udelay(ulong usec)
+{
+	unsigned long long start;
+
+	start = get_ticks();		/* get current timestamp */
+	while ((get_ticks() - start) < usec)
+		;			/* loop till time has passed */
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ_CLOCK;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/Makefile b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
index f920eeb..9f7815b 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch3/Makefile
@@ -6,6 +6,8 @@
 
 obj-y += cpu.o
 obj-y += lowlevel.o
+obj-y += soc.o
 obj-y += speed.o
+obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch3_serdes.o ls2085a_serdes.o
 obj-$(CONFIG_MP) += mp.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/README b/arch/arm/cpu/armv8/fsl-lsch3/README
index cc47466..37f07fb 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/README
+++ b/arch/arm/cpu/armv8/fsl-lsch3/README
@@ -8,3 +8,141 @@ Freescale LayerScape with Chassis Generation 3
 
 This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
 for example LS2085A.
+
+Flash Layout
+============
+
+(1) A typical layout of various images (including Linux and other firmware images)
+   is shown below considering a 32MB NOR flash device present on most
+   pre-silicon platforms (simulator and emulator):
+
+	-------------------------
+	| 	FIT Image	|
+	| (linux + DTB + RFS)	|
+	------------------------- ----> 0x0120_0000
+	| 	Debug Server FW |
+	------------------------- ----> 0x00C0_0000
+	|	AIOP FW 	|
+	------------------------- ----> 0x0070_0000
+	|	MC FW 		|
+	------------------------- ----> 0x006C_0000
+	| 	MC DPL Blob 	|
+	------------------------- ----> 0x0020_0000
+	| 	BootLoader + Env|
+	------------------------- ----> 0x0000_1000
+	|	PBI 		|
+	------------------------- ----> 0x0000_0080
+	|	RCW 		|
+	------------------------- ----> 0x0000_0000
+
+	32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
+
+(2) A typical layout of various images (including Linux and other firmware images)
+    is shown below considering a 128MB NOR flash device present on QDS and RDB
+    boards:
+	----------------------------------------- ----> 0x5_8800_0000 ---
+	|	.. Unused .. (7M)		|			|
+	----------------------------------------- ----> 0x5_8790_0000	|
+	| FIT Image (linux + DTB + RFS)	(40M)	|			|
+	----------------------------------------- ----> 0x5_8510_0000	|
+	|	PHY firmware (2M)	 	|			|
+	----------------------------------------- ----> 0x5_84F0_0000	| 64K
+	|	Debug Server FW (2M)		|			| Alt
+	----------------------------------------- ----> 0x5_84D0_0000	| Bank
+	|	AIOP FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8490_0000 (vbank4)
+	|	MC DPC Blob (1M) 		|			|
+	----------------------------------------- ----> 0x5_8480_0000	|
+	|	MC DPL Blob (1M)		|			|
+	----------------------------------------- ----> 0x5_8470_0000	|
+	| 	MC FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8430_0000	|
+	|	BootLoader Environment (1M) 	|			|
+	----------------------------------------- ----> 0x5_8420_0000	|
+	|	BootLoader (1M)			|			|
+	----------------------------------------- ----> 0x5_8410_0000	|
+	|	RCW and PBI (1M) 		|			|
+	----------------------------------------- ----> 0x5_8400_0000 ---
+	|	.. Unused .. (7M)		|			|
+	----------------------------------------- ----> 0x5_8390_0000	|
+	| FIT Image (linux + DTB + RFS)	(40M)	|			|
+	----------------------------------------- ----> 0x5_8110_0000	|
+	|	PHY firmware (2M)	 	|			|
+	----------------------------------------- ----> 0x5_80F0_0000	| 64K
+	|	Debug Server FW (2M)		|			| Bank
+	----------------------------------------- ----> 0x5_80D0_0000	|
+	|	AIOP FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8090_0000 (vbank0)
+	|	MC DPC Blob (1M) 		|			|
+	----------------------------------------- ----> 0x5_8080_0000	|
+	|	MC DPL Blob (1M)		|			|
+	----------------------------------------- ----> 0x5_8070_0000	|
+	| 	MC FW (4M)			|			|
+	----------------------------------------- ----> 0x5_8030_0000	|
+	|	BootLoader Environment (1M) 	|			|
+	----------------------------------------- ----> 0x5_8020_0000	|
+	|	BootLoader (1M)			|			|
+	----------------------------------------- ----> 0x5_8010_0000	|
+	|	RCW and PBI (1M) 		|			|
+	----------------------------------------- ----> 0x5_8000_0000 ---
+
+	128-MB NOR flash layout for QDS and RDB boards
+
+Environment Variables
+=====================
+mcboottimeout:	MC boot timeout in milliseconds. If this variable is not defined
+		the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
+
+mcmemsize:	MC DRAM block size. If this variable is not defined, the value
+		CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
+
+Booting from NAND
+-------------------
+Booting from NAND requires two images, RCW and u-boot-with-spl.bin.
+The difference between NAND boot RCW image and NOR boot image is the PBI
+command sequence. Below is one example for PBI commands for QDS which uses
+NAND device with 2KB/page, block size 128KB.
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+The above two commands set bootloc register to 0x00000000_1800a000 where
+the u-boot code will be running in OCRAM.
+
+3) Block Copy: SRC=0x0107, SRC_ADDR=0x00020000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+This command copies u-boot image from NAND device into OCRAM. The values need
+to adjust accordingly.
+
+SRC		should match the cfg_rcw_src, the reset config pins. It depends
+		on the NAND device. See reference manual for cfg_rcw_src.
+SRC_ADDR	is the offset of u-boot-with-spl.bin image in NAND device. In
+		the example above, 128KB. For easy maintenance, we put it at
+		the beginning of next block from RCW.
+DEST_ADDR	is fixed at 0x1800a000, matching bootloc set above.
+BLOCK_SIZE	is the size to be copied by PBI.
+
+RCW image should be written to the beginning of NAND device. Example of using
+u-boot command
+
+nand write <rcw image in memory> 0 <size of rcw image>
+
+To form the NAND image, build u-boot with NAND config, for example,
+ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
+The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
+
+nand write <u-boot image in memory> 200000 <size of u-boot image>
+
+With these two images in NAND device, the board can boot from NAND.
+
+Another example for RDB boards,
+
+1) CCSR 4-byte write to 0x00e00404, data=0x00000000
+2) CCSR 4-byte write to 0x00e00400, data=0x1800a000
+3) Block Copy: SRC=0x0119, SRC_ADDR=0x00080000, DEST_ADDR=0x1800a000,
+BLOCK_SIZE=0x00014000
+
+nand write <rcw image in memory> 0 <size of rcw image>
+nand write <u-boot image in memory> 80000 <size of u-boot image>
+
+Notice the difference from QDS is SRC, SRC_ADDR and the offset of u-boot image
+to match board NAND device with 4KB/page, block size 512KB.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
index 4997487..6714577 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c
@@ -10,7 +10,12 @@
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
+#include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "cpu.h"
 #include "mp.h"
 #include "speed.h"
@@ -24,8 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
  * levels of translation tables here to cover 40-bit address space.
  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  * Level 0 IA[39], table address @0
- * Level 1 IA[31:30], table address @01000, 0x2000
- * Level 2 IA[29:21], table address @0x3000
+ * Level 1 IA[31:30], table address @0x1000, 0x2000
+ * Level 2 IA[29:21], table address @0x3000, 0x4000
+ * Address above 0x5000 is free for other purpose.
  */
 
 #define SECTION_SHIFT_L0	39UL
@@ -60,12 +66,12 @@ static inline void early_mmu_setup(void)
 {
 	int el;
 	u64 i;
-	u64 section_l1t0, section_l1t1, section_l2;
+	u64 section_l1t0, section_l1t1, section_l2t0, section_l2t1;
 	u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE;
 	u64 *level1_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000);
 	u64 *level1_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000);
-	u64 *level2_table = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
-
+	u64 *level2_table_0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000);
+	u64 *level2_table_1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000);
 
 	level0_table[0] =
 		(u64)level1_table_0 | PMD_TYPE_TABLE;
@@ -79,21 +85,25 @@ static inline void early_mmu_setup(void)
 	 */
 	section_l1t0 = 0;
 	section_l1t1 = BLOCK_SIZE_L0;
-	section_l2 = 0;
+	section_l2t0 = 0;
+	section_l2t1 = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < 512; i++) {
 		set_pgtable_section(level1_table_0, i, section_l1t0,
 				    MT_DEVICE_NGNRNE);
 		set_pgtable_section(level1_table_1, i, section_l1t1,
 				    MT_NORMAL);
-		set_pgtable_section(level2_table, i, section_l2,
+		set_pgtable_section(level2_table_0, i, section_l2t0,
+				    MT_DEVICE_NGNRNE);
+		set_pgtable_section(level2_table_1, i, section_l2t1,
 				    MT_DEVICE_NGNRNE);
 		section_l1t0 += BLOCK_SIZE_L1;
 		section_l1t1 += BLOCK_SIZE_L1;
-		section_l2 += BLOCK_SIZE_L2;
+		section_l2t0 += BLOCK_SIZE_L2;
+		section_l2t1 += BLOCK_SIZE_L2;
 	}
 
 	level1_table_0[0] =
-		(u64)level2_table | PMD_TYPE_TABLE;
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
 	level1_table_0[1] =
 		0x40000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 		PMD_ATTRINDX(MT_DEVICE_NGNRNE);
@@ -104,17 +114,34 @@ static inline void early_mmu_setup(void)
 		0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT |
 		PMD_ATTRINDX(MT_NORMAL);
 
-	/* Rewrite table to enable cache */
-	set_pgtable_section(level2_table,
+	/* Rewerite table to enable cache for OCRAM */
+	set_pgtable_section(level2_table_0,
 			    CONFIG_SYS_FSL_OCRAM_BASE >> SECTION_SHIFT_L2,
 			    CONFIG_SYS_FSL_OCRAM_BASE,
 			    MT_NORMAL);
-	for (i = CONFIG_SYS_IFC_BASE >> SECTION_SHIFT_L2;
-	     i < (CONFIG_SYS_IFC_BASE + CONFIG_SYS_IFC_SIZE)
-	     >> SECTION_SHIFT_L2; i++) {
-		section_l2 = i << SECTION_SHIFT_L2;
-		set_pgtable_section(level2_table, i,
-				    section_l2, MT_NORMAL);
+
+#if defined(CONFIG_SYS_NOR0_CSPR_EARLY) && defined(CONFIG_SYS_NOR_AMASK_EARLY)
+	/* Rewrite table to enable cache for two entries (4MB) */
+	section_l2t1 = CONFIG_SYS_IFC_BASE;
+	set_pgtable_section(level2_table_0,
+			    section_l2t1 >> SECTION_SHIFT_L2,
+			    section_l2t1,
+			    MT_NORMAL);
+	section_l2t1 += BLOCK_SIZE_L2;
+	set_pgtable_section(level2_table_0,
+			    section_l2t1 >> SECTION_SHIFT_L2,
+			    section_l2t1,
+			    MT_NORMAL);
+#endif
+
+	/* Create a mapping for 256MB IFC region to final flash location */
+	level1_table_0[CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1] =
+		(u64)level2_table_1 | PMD_TYPE_TABLE;
+	section_l2t1 = CONFIG_SYS_IFC_BASE;
+	for (i = 0; i < 0x10000000 >> SECTION_SHIFT_L2; i++) {
+		set_pgtable_section(level2_table_1, i,
+				    section_l2t1, MT_DEVICE_NGNRNE);
+		section_l2t1 += BLOCK_SIZE_L2;
 	}
 
 	el = current_el();
@@ -347,6 +374,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
@@ -370,21 +398,40 @@ int print_cpuinfo(void)
 	printf("     DP-DDR:   %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2));
 	puts("\n");
 
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_le32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %02x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
 	return 0;
 }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+	return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
 int cpu_eth_init(bd_t *bis)
 {
 	int error = 0;
 
 #ifdef CONFIG_FSL_MC_ENET
-	error = mc_init(bis);
+	error = fsl_mc_ldpaa_init(bis);
 #endif
 	return error;
 }
 
-
 int arch_early_init_r(void)
 {
 	int rv;
@@ -393,5 +440,43 @@ int arch_early_init_r(void)
 	if (rv)
 		printf("Did not wake secondary cores\n");
 
+#ifdef CONFIG_SYS_HAS_SERDES
+	fsl_serdes_init();
+#endif
+	return 0;
+}
+
+int timer_init(void)
+{
+	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+#ifdef COUNTER_FREQUENCY_REAL
+	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
+
+	/* Update with accurate clock frequency */
+	asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+#endif
+
+	/* Enable timebase for all clusters.
+	 * It is safe to do so even some clusters are not enabled.
+	 */
+	out_le32(cltbenr, 0xf);
+
+	/* Enable clock for timer
+	 * This is a global setting.
+	 */
+	out_le32(cntcr, 0x1);
+
 	return 0;
 }
+
+void reset_cpu(ulong addr)
+{
+	u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+	u32 val;
+
+	/* Raise RESET_REQ_B */
+	val = in_le32(rstcr);
+	val |= 0x02;
+	out_le32(rstcr, val);
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
index 7eb9b6a..d370023 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fdt.c
@@ -7,6 +7,9 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "mp.h"
 
 #ifdef CONFIG_MP
@@ -62,7 +65,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 
 #ifdef CONFIG_SYS_NS16550
-	do_fixup_by_compat_u32(blob, "ns16550",
+	do_fixup_by_compat_u32(blob, "fsl,ns16550",
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
+
+#if defined(CONFIG_FSL_ESDHC)
+	fdt_fixup_esdhc(blob, bd);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
new file mode 100644
index 0000000..02ca126
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/fsl_lsch3_serdes.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+#include <fsl-mc/ldpaa_wriop.h>
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
+
+int is_serdes_configured(enum srds_prtcl device)
+{
+	int ret = 0;
+
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	ret |= serdes1_prtcl_map[device];
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	ret |= serdes2_prtcl_map[device];
+#endif
+
+	return !!ret;
+}
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg = in_le32(&gur->rcwsr[28]);
+	int i;
+
+	switch (sd) {
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	case FSL_SRDS_1:
+		cfg &= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
+		break;
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	case FSL_SRDS_2:
+		cfg &= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
+		cfg >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
+		break;
+#endif
+	default:
+		printf("invalid SerDes%d\n", sd);
+		break;
+	}
+	/* Is serdes enabled at all? */
+	if (cfg == 0)
+		return -ENODEV;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (serdes_get_prtcl(sd, cfg, i) == device)
+			return i;
+	}
+
+	return -ENODEV;
+}
+
+void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
+		u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
+{
+	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+	u32 cfg;
+	int lane;
+
+	memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
+
+	cfg = in_le32(&gur->rcwsr[28]) & sd_prctl_mask;
+	cfg >>= sd_prctl_shift;
+	printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
+
+	if (!is_serdes_prtcl_valid(sd, cfg))
+		printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
+
+	for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+		enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
+		if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
+			debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
+		else {
+			serdes_prtcl_map[lane_prtcl] = 1;
+#ifdef CONFIG_FSL_MC_ENET
+			wriop_init_dpmac(sd, lane + 1, (int)lane_prtcl);
+#endif
+		}
+	}
+}
+
+void fsl_serdes_init(void)
+{
+#ifdef CONFIG_SYS_FSL_SRDS_1
+	serdes_init(FSL_SRDS_1,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
+		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK,
+		    FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT,
+		    serdes1_prtcl_map);
+#endif
+#ifdef CONFIG_SYS_FSL_SRDS_2
+	serdes_init(FSL_SRDS_2,
+		    CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK,
+		    FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT,
+		    serdes2_prtcl_map);
+#endif
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
index 886576e..018c617 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S
@@ -15,6 +15,15 @@
 ENTRY(lowlevel_init)
 	mov	x29, lr			/* Save LR */
 
+	/* Add fully-coherent masters to DVM domain */
+	ldr	x1, =CCI_MN_BASE
+	ldr	x2, [x1, #CCI_MN_RNF_NODEID_LIST]
+	str	x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+1:	ldr	x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET]
+	mvn	x0, x3
+	tst	x0, x3		/* Wait for domain addition to complete */
+	b.ne	1b
+
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
 	ldr	w0, [x1, #0x10]
@@ -224,6 +233,9 @@ ENTRY(secondary_boot_func)
 	/* physical address of this cpus spin table element */
 	add	x11, x1, x0
 
+	ldr	x0, =__real_cntfrq
+	ldr	x0, [x0]
+	msr	cntfrq_el0, x0	/* set with real frequency */
 	str	x9, [x11, #16]	/* LPID */
 	mov	x4, #1
 	str	x4, [x11, #8]	/* STATUS */
@@ -275,6 +287,9 @@ ENDPROC(secondary_switch_to_el1)
 
 	/* 64 bit alignment for elements accessed as data */
 	.align 4
+	.global __real_cntfrq
+__real_cntfrq:
+	.quad COUNTER_FREQUENCY
 	.globl __secondary_boot_code_size
 	.type __secondary_boot_code_size, %object
 	/* Secondary Boot Code ends here */
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
new file mode 100644
index 0000000..098745b
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/ls2085a_serdes.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch-fsl-lsch3/immap_lsch3.h>
+
+struct serdes_config {
+	u8 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	/* SerDes 1 */
+	{0x03, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2 } },
+	{0x05, {PCIE2, PCIE2, PCIE2, PCIE2, SGMII4, SGMII3, SGMII2, SGMII1 } },
+	{0x07, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x09, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x0A, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x0C, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x0E, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, SGMII2,
+		SGMII1 } },
+	{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
+	{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
+	{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
+	{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1  } },
+	{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1  } },
+	{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_D, QSGMII_C, QSGMII_B,
+		QSGMII_A} },
+	{0x35, {QSGMII_D, QSGMII_C, QSGMII_B, PCIE2, XFI4, XFI3, XFI2, XFI1 } },
+		{}
+};
+static struct serdes_config serdes2_cfg_tbl[] = {
+	/* SerDes 2 */
+	{0x07, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x09, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x0A, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x0C, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x0E, {SGMII9, SGMII10, SGMII11, SGMII12, SGMII13, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x3D, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+	{0x3E, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3 } },
+	{0x3F, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+	{0x40, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4 } },
+	{0x41, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+	{0x42, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2 } },
+	{0x43, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+	{0x44, {PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE, SATA1, SATA2 } },
+	{0x45, {PCIE3, SGMII10, SGMII11, SGMII12, PCIE4, SGMII14, SGMII15,
+		SGMII16 } },
+	{0x47, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, PCIE4,
+		PCIE4 } },
+	{0x49, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
+		SATA2 } },
+	{0x4A, {SGMII9, SGMII10, SGMII11, SGMII12, PCIE4, PCIE4, SATA1,
+		SATA2 } },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+	serdes2_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
index ce9c0c1..da7853a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
@@ -31,6 +31,13 @@ int fsl_lsch3_wake_seconday_cores(void)
 	int i, timeout = 10;
 	u64 *table = get_spin_tbl_addr();
 
+#ifdef COUNTER_FREQUENCY_REAL
+	/* update for secondary cores */
+	__real_cntfrq = COUNTER_FREQUENCY_REAL;
+	flush_dcache_range((unsigned long)&__real_cntfrq,
+			   (unsigned long)&__real_cntfrq + 8);
+#endif
+
 	cores = cpu_mask();
 	/* Clear spin table so that secondary processors
 	 * observe the correct value after waking up from wfe.
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.h b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
index 66144d6..c985d6a 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/mp.h
+++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.h
@@ -26,6 +26,7 @@
 #define id_to_core(x)	((x & 3) | (x >> 6))
 #ifndef __ASSEMBLY__
 extern u64 __spin_table[];
+extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
 int fsl_lsch3_wake_seconday_cores(void);
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/soc.c b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
new file mode 100644
index 0000000..2538001
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch3/soc.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ifc.h>
+#include <nand.h>
+#include <spl.h>
+#include <asm/arch-fsl-lsch3/soc.h>
+#include <asm/io.h>
+#include <asm/global_data.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void erratum_a008751(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
+	u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+
+	writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
+#endif
+}
+
+static void erratum_rcw_src(void)
+{
+#if defined(CONFIG_SPL)
+	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+	u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
+	u32 val;
+
+	val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
+	val &= ~DCFG_PORSR1_RCW_SRC;
+	val |= DCFG_PORSR1_RCW_SRC_NOR;
+	out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
+#endif
+}
+
+#define I2C_DEBUG_REG 0x6
+#define I2C_GLITCH_EN 0x8
+/*
+ * This erratum requires setting glitch_en bit to enable
+ * digital glitch filter to improve clock stability.
+ */
+static void erratum_a009203(void)
+{
+	u8 __iomem *ptr;
+#ifdef CONFIG_SYS_I2C
+#ifdef I2C1_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C2_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C3_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#ifdef I2C4_BASE_ADDR
+	ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
+
+	writeb(I2C_GLITCH_EN, ptr);
+#endif
+#endif
+}
+
+void fsl_lsch3_early_init_f(void)
+{
+	erratum_a008751();
+	erratum_rcw_src();
+	init_early_memctl_regs();	/* tighten IFC timing */
+	erratum_a009203();
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+	board_early_init_f();
+	timer_init();
+	env_init();
+	gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE);
+
+	serial_init();
+	console_init_f();
+	dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	board_init_r(NULL, 0);
+}
+
+u32 spl_boot_device(void)
+{
+	return BOOT_DEVICE_NAND;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-lsch3/speed.c b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
index 72cd999..cac4f92 100644
--- a/arch/arm/cpu/armv8/fsl-lsch3/speed.c
+++ b/arch/arm/cpu/armv8/fsl-lsch3/speed.c
@@ -26,7 +26,7 @@ void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 	struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
@@ -86,6 +86,8 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_systembus *= (in_le32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
+	/* Platform clock is half of platform PLL */
+	sys_info->freq_systembus /= 2;
 	sys_info->freq_ddrbus *= (in_le32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
@@ -102,10 +104,7 @@ void get_sys_info(struct sys_info *sys_info)
 			 offsetof(struct ccsr_clk_cluster_group,
 				  pllngsr[i%3].gsr));
 		ratio[i] = (in_le32(offset) >> 1) & 0x3f;
-		if (ratio[i] > 4)
-			freq_c_pll[i] = sysclk * ratio[i];
-		else
-			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
+		freq_c_pll[i] = sysclk * ratio[i];
 	}
 
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
@@ -119,7 +118,7 @@ void get_sys_info(struct sys_info *sys_info)
 	}
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = in_le32(&ifc_regs->ifc_ccr);
+	ccr = in_le32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/arm/cpu/armv8/generic_timer.c b/arch/arm/cpu/armv8/generic_timer.c
index 223b95e..8e60bae 100644
--- a/arch/arm/cpu/armv8/generic_timer.c
+++ b/arch/arm/cpu/armv8/generic_timer.c
@@ -25,7 +25,18 @@ unsigned long get_tbclk(void)
 unsigned long timer_read_counter(void)
 {
 	unsigned long cntpct;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+	/* This erratum number needs to be confirmed to match ARM document */
+	unsigned long temp;
+#endif
 	isb();
 	asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008585
+	asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
+	while (temp != cntpct) {
+		asm volatile("mrs %0, cntpct_el0" : "=r" (cntpct));
+		asm volatile("mrs %0, cntpct_el0" : "=r" (temp));
+	}
+#endif
 	return cntpct;
 }
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
new file mode 100644
index 0000000..4df339c
--- /dev/null
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR,
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(_start)
+SECTIONS
+{
+	.text : {
+		. = ALIGN(8);
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		*(.text*)
+	} >.sram
+
+	.rodata : {
+		. = ALIGN(8);
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	} >.sram
+
+	.data : {
+		. = ALIGN(8);
+		*(.data*)
+	} >.sram
+
+	.u_boot_list : {
+		. = ALIGN(8);
+		KEEP(*(SORT(.u_boot_list*)));
+	} >.sram
+
+	.image_copy_end : {
+		. = ALIGN(8);
+		*(.__image_copy_end)
+	} >.sram
+
+	.end : {
+		. = ALIGN(8);
+		*(.__end)
+	} >.sram
+
+	.bss_start : {
+		. = ALIGN(8);
+		KEEP(*(.__bss_start));
+	} >.sdram
+
+	.bss : {
+		*(.bss*)
+		 . = ALIGN(8);
+	} >.sdram
+
+	.bss_end : {
+		KEEP(*(.__bss_end));
+	} >.sdram
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/arch/arm/cpu/armv8/zynqmp/Makefile b/arch/arm/cpu/armv8/zynqmp/Makefile
index a997e04..efab5ea 100644
--- a/arch/arm/cpu/armv8/zynqmp/Makefile
+++ b/arch/arm/cpu/armv8/zynqmp/Makefile
@@ -7,3 +7,4 @@
 
 obj-y	+= clk.o
 obj-y	+= cpu.o
+obj-$(CONFIG_MP)	+= mp.o
diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c
index 0af619d..9218586 100644
--- a/arch/arm/cpu/armv8/zynqmp/clk.c
+++ b/arch/arm/cpu/armv8/zynqmp/clk.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 
@@ -16,6 +17,8 @@ unsigned long get_uart_clk(int dev_id)
 	u32 ver = zynqmp_get_silicon_version();
 
 	switch (ver) {
+	case ZYNQMP_CSU_VERSION_VELOCE:
+		return 48000;
 	case ZYNQMP_CSU_VERSION_EP108:
 		return 25000000;
 	}
diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c
index 6fae03c..60d7d20 100644
--- a/arch/arm/cpu/armv8/zynqmp/cpu.c
+++ b/arch/arm/cpu/armv8/zynqmp/cpu.c
@@ -20,9 +20,175 @@ unsigned int zynqmp_get_silicon_version(void)
 	gd->cpu_clk = get_tbclk();
 
 	switch (gd->cpu_clk) {
+	case 0 ... 1000000:
+		return ZYNQMP_CSU_VERSION_VELOCE;
 	case 50000000:
 		return ZYNQMP_CSU_VERSION_QEMU;
 	}
 
 	return ZYNQMP_CSU_VERSION_EP108;
 }
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#include <asm/armv8/mmu.h>
+
+#define SECTION_SHIFT_L1	30UL
+#define SECTION_SHIFT_L2	21UL
+#define BLOCK_SIZE_L0		0x8000000000UL
+#define BLOCK_SIZE_L1		(1 << SECTION_SHIFT_L1)
+#define BLOCK_SIZE_L2		(1 << SECTION_SHIFT_L2)
+
+#define TCR_TG1_4K		(1 << 31)
+#define TCR_EPD1_DISABLE	(1 << 23)
+#define ZYNQMO_VA_BITS		40
+#define ZYNQMP_TCR		TCR_TG1_4K | \
+				TCR_EPD1_DISABLE | \
+				TCR_SHARED_OUTER | \
+				TCR_SHARED_INNER | \
+				TCR_IRGN_WBWA | \
+				TCR_ORGN_WBWA | \
+				TCR_T0SZ(ZYNQMO_VA_BITS)
+
+#define MEMORY_ATTR	PMD_SECT_AF | PMD_SECT_INNER_SHARE |	\
+			PMD_ATTRINDX(MT_NORMAL) |	\
+			PMD_TYPE_SECT
+#define DEVICE_ATTR	PMD_SECT_AF | PMD_SECT_PXN |	\
+			PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) |	\
+			PMD_TYPE_SECT
+
+/* 4K size is required to place 512 entries in each level */
+#define TLB_TABLE_SIZE	0x1000
+
+struct attr_tbl {
+	u32 num;
+	u64 attr;
+};
+
+static struct attr_tbl attr_tbll1t0[4] = { {16, 0x0},
+					   {8, DEVICE_ATTR},
+					   {32, MEMORY_ATTR},
+					   {456, DEVICE_ATTR}
+					 };
+static struct attr_tbl attr_tbll2t3[4] = { {0x180, DEVICE_ATTR},
+					   {0x40, 0x0},
+					   {0x3F, DEVICE_ATTR},
+					   {0x1, MEMORY_ATTR}
+					 };
+
+/*
+ * This mmu table looks as below
+ * Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
+ * and other Level1 Table1.
+ * Level1 Table0 contains entries for each 1GB from 0 to 511GB.
+ * Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
+ * Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
+ * entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
+ */
+static void zynqmp_mmu_setup(void)
+{
+	int el;
+	u32 index_attr;
+	u64 i, section_l1t0, section_l1t1;
+	u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
+	u64 *level0_table = (u64 *)gd->arch.tlb_addr;
+	u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
+	u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
+	u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
+	u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
+	u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
+	u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
+
+	level0_table[0] =
+		(u64)level1_table_0 | PMD_TYPE_TABLE;
+	level0_table[1] =
+		(u64)level1_table_1 | PMD_TYPE_TABLE;
+
+	/*
+	 * set level 1 table 0, covering 0 to 512GB
+	 * set level 1 table 1, covering 512GB to 1TB
+	 */
+	section_l1t0 = 0;
+	section_l1t1 = BLOCK_SIZE_L0;
+
+	index_attr = 0;
+	for (i = 0; i < 512; i++) {
+		level1_table_0[i] = section_l1t0;
+		level1_table_0[i] |= attr_tbll1t0[index_attr].attr;
+		attr_tbll1t0[index_attr].num--;
+		if (attr_tbll1t0[index_attr].num == 0)
+			index_attr++;
+		level1_table_1[i] = section_l1t1;
+		level1_table_1[i] |= DEVICE_ATTR;
+		section_l1t0 += BLOCK_SIZE_L1;
+		section_l1t1 += BLOCK_SIZE_L1;
+	}
+
+	level1_table_0[0] =
+		(u64)level2_table_0 | PMD_TYPE_TABLE;
+	level1_table_0[1] =
+		(u64)level2_table_1 | PMD_TYPE_TABLE;
+	level1_table_0[2] =
+		(u64)level2_table_2 | PMD_TYPE_TABLE;
+	level1_table_0[3] =
+		(u64)level2_table_3 | PMD_TYPE_TABLE;
+
+	section_l2t0 = 0;
+	section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
+	section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
+	section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
+
+	index_attr = 0;
+
+	for (i = 0; i < 512; i++) {
+		level2_table_0[i] = section_l2t0 | MEMORY_ATTR;
+		level2_table_1[i] = section_l2t1 | MEMORY_ATTR;
+		level2_table_2[i] = section_l2t2 | DEVICE_ATTR;
+		level2_table_3[i] = section_l2t3 |
+				    attr_tbll2t3[index_attr].attr;
+		attr_tbll2t3[index_attr].num--;
+		if (attr_tbll2t3[index_attr].num == 0)
+			index_attr++;
+		section_l2t0 += BLOCK_SIZE_L2;
+		section_l2t1 += BLOCK_SIZE_L2;
+		section_l2t2 += BLOCK_SIZE_L2;
+		section_l2t3 += BLOCK_SIZE_L2;
+	}
+
+	/* flush new MMU table */
+	flush_dcache_range(gd->arch.tlb_addr,
+			   gd->arch.tlb_addr + gd->arch.tlb_size);
+
+	/* point TTBR to the new table */
+	el = current_el();
+	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
+			  ZYNQMP_TCR, MEMORY_ATTRIBUTES);
+
+	set_sctlr(get_sctlr() | CR_M);
+}
+
+int arch_cpu_init(void)
+{
+	icache_enable();
+	__asm_invalidate_dcache_all();
+	__asm_invalidate_tlb_all();
+	return 0;
+}
+
+/*
+ * This function is called from lib/board.c.
+ * It recreates MMU table in main memory. MMU and d-cache are enabled earlier.
+ * There is no need to disable d-cache for this operation.
+ */
+void enable_caches(void)
+{
+	/* The data cache is not active unless the mmu is enabled */
+	if (!(get_sctlr() & CR_M)) {
+		invalidate_dcache_all();
+		__asm_invalidate_tlb_all();
+		zynqmp_mmu_setup();
+	}
+	puts("Enabling Caches...\n");
+
+	set_sctlr(get_sctlr() | CR_C);
+}
+#endif
diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c
new file mode 100644
index 0000000..17e32a7
--- /dev/null
+++ b/arch/arm/cpu/armv8/zynqmp/mp.c
@@ -0,0 +1,242 @@
+/*
+ * (C) Copyright 2014 - 2015 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+#define LOCK		0
+#define SPLIT		1
+
+#define HALT		0
+#define RELEASE		1
+
+#define ZYNQMP_BOOTADDR_HIGH_MASK		0xFFFFFFFF
+#define ZYNQMP_R5_HIVEC_ADDR			0xFFFF0000
+#define ZYNQMP_R5_LOVEC_ADDR			0x0
+#define ZYNQMP_RPU_CFG_CPU_HALT_MASK		0x01
+#define ZYNQMP_RPU_CFG_HIVEC_MASK		0x04
+#define ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK	0x08
+#define ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK	0x40
+#define ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK	0x10
+
+#define ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK	0x04
+#define ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK	0x01
+#define ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK	0x02
+#define ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK	0x1000000
+
+#define ZYNQMP_TCM_START_ADDRESS		0xFFE00000
+#define ZYNQMP_TCM_BOTH_SIZE			0x40000
+
+#define ZYNQMP_CORE_APU0	0
+#define ZYNQMP_CORE_APU3	3
+
+#define ZYNQMP_MAX_CORES	6
+
+int is_core_valid(unsigned int core)
+{
+	if (core < ZYNQMP_MAX_CORES)
+		return 1;
+
+	return 0;
+}
+
+int cpu_reset(int nr)
+{
+	puts("Feature is not implemented.\n");
+	return 0;
+}
+
+static void set_r5_halt_mode(u8 halt, u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&rpu_base->rpu0_cfg);
+	if (halt == HALT)
+		tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
+	else
+		tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
+	writel(tmp, &rpu_base->rpu0_cfg);
+
+	if (mode == LOCK) {
+		tmp = readl(&rpu_base->rpu1_cfg);
+		if (halt == HALT)
+			tmp &= ~ZYNQMP_RPU_CFG_CPU_HALT_MASK;
+		else
+			tmp |= ZYNQMP_RPU_CFG_CPU_HALT_MASK;
+		writel(tmp, &rpu_base->rpu1_cfg);
+	}
+}
+
+static void set_r5_tcm_mode(u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&rpu_base->rpu_glbl_ctrl);
+	if (mode == LOCK) {
+		tmp &= ~ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
+		tmp |= ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
+		       ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK;
+	} else {
+		tmp |= ZYNQMP_RPU_GLBL_CTRL_SPLIT_LOCK_MASK;
+		tmp &= ~(ZYNQMP_RPU_GLBL_CTRL_TCM_COMB_MASK |
+		       ZYNQMP_RPU_GLBL_CTRL_SLCLAMP_MASK);
+	}
+
+	writel(tmp, &rpu_base->rpu_glbl_ctrl);
+}
+
+static void set_r5_reset(u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&crlapb_base->rst_lpd_top);
+	tmp |= (ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+	       ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
+
+	if (mode == LOCK)
+		tmp |= ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
+
+	writel(tmp, &crlapb_base->rst_lpd_top);
+}
+
+static void release_r5_reset(u8 mode)
+{
+	u32 tmp;
+
+	tmp = readl(&crlapb_base->rst_lpd_top);
+	tmp &= ~(ZYNQMP_CRLAPB_RST_LPD_AMBA_RST_MASK |
+	       ZYNQMP_CRLAPB_RST_LPD_R50_RST_MASK);
+
+	if (mode == LOCK)
+		tmp &= ~ZYNQMP_CRLAPB_RST_LPD_R51_RST_MASK;
+
+	writel(tmp, &crlapb_base->rst_lpd_top);
+}
+
+static void enable_clock_r5(void)
+{
+	u32 tmp;
+
+	tmp = readl(&crlapb_base->cpu_r5_ctrl);
+	tmp |= ZYNQMP_CRLAPB_CPU_R5_CTRL_CLKACT_MASK;
+	writel(tmp, &crlapb_base->cpu_r5_ctrl);
+
+	/* Give some delay for clock
+	 * to propogate */
+	udelay(0x500);
+}
+
+int cpu_disable(int nr)
+{
+	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
+		u32 val = readl(&crfapb_base->rst_fpd_apu);
+		val |= 1 << nr;
+		writel(val, &crfapb_base->rst_fpd_apu);
+	} else {
+		set_r5_reset(LOCK);
+	}
+
+	return 0;
+}
+
+int cpu_status(int nr)
+{
+	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
+		u32 addr_low = readl(((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
+		u32 addr_high = readl(((u8 *)&apu_base->rvbar_addr0_h) +
+				      nr * 8);
+		u32 val = readl(&crfapb_base->rst_fpd_apu);
+		val &= 1 << nr;
+		printf("APU CPU%d %s - starting address HI: %x, LOW: %x\n",
+		       nr, val ? "OFF" : "ON" , addr_high, addr_low);
+	} else {
+		u32 val = readl(&crlapb_base->rst_lpd_top);
+		val &= 1 << (nr - 4);
+		printf("RPU CPU%d %s\n", nr - 4, val ? "OFF" : "ON");
+	}
+
+	return 0;
+}
+
+static void set_r5_start(u8 high)
+{
+	u32 tmp;
+
+	tmp = readl(&rpu_base->rpu0_cfg);
+	if (high)
+		tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
+	else
+		tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
+	writel(tmp, &rpu_base->rpu0_cfg);
+
+	tmp = readl(&rpu_base->rpu1_cfg);
+	if (high)
+		tmp |= ZYNQMP_RPU_CFG_HIVEC_MASK;
+	else
+		tmp &= ~ZYNQMP_RPU_CFG_HIVEC_MASK;
+	writel(tmp, &rpu_base->rpu1_cfg);
+}
+
+int cpu_release(int nr, int argc, char * const argv[])
+{
+	if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) {
+		u64 boot_addr = simple_strtoull(argv[0], NULL, 16);
+		/* HIGH */
+		writel((u32)(boot_addr >> 32),
+		       ((u8 *)&apu_base->rvbar_addr0_h) + nr * 8);
+		/* LOW */
+		writel((u32)(boot_addr & ZYNQMP_BOOTADDR_HIGH_MASK),
+		       ((u8 *)&apu_base->rvbar_addr0_l) + nr * 8);
+
+		u32 val = readl(&crfapb_base->rst_fpd_apu);
+		val &= ~(1 << nr);
+		writel(val, &crfapb_base->rst_fpd_apu);
+	} else {
+		if (argc != 2) {
+			printf("Invalid number of arguments to release.\n");
+			printf("<addr> <mode>-Start addr lockstep or split\n");
+			return 1;
+		}
+
+		u32 boot_addr = simple_strtoul(argv[0], NULL, 16);
+		if (!(boot_addr == ZYNQMP_R5_LOVEC_ADDR ||
+		      boot_addr == ZYNQMP_R5_HIVEC_ADDR)) {
+			printf("Invalid starting address 0x%x\n", boot_addr);
+			printf("0 or 0xffff0000 are permitted\n");
+			return 1;
+		}
+
+		if (!strncmp(argv[1], "lockstep", 8)) {
+			printf("R5 lockstep mode\n");
+			set_r5_tcm_mode(LOCK);
+			set_r5_halt_mode(HALT, LOCK);
+
+			if (boot_addr == 0)
+				set_r5_start(0);
+			else
+				set_r5_start(1);
+
+			enable_clock_r5();
+			release_r5_reset(LOCK);
+			set_r5_halt_mode(RELEASE, LOCK);
+		} else if (!strncmp(argv[1], "split", 5)) {
+			printf("R5 split mode\n");
+			set_r5_tcm_mode(SPLIT);
+			set_r5_halt_mode(HALT, SPLIT);
+			enable_clock_r5();
+			release_r5_reset(SPLIT);
+			set_r5_halt_mode(RELEASE, SPLIT);
+		} else {
+			printf("Unsupported mode\n");
+			return 1;
+		}
+	}
+
+	return 0;
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f897e6d..46a6171 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -39,11 +39,12 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-pro4-ref.dtb \
 	uniphier-ph1-ld4-ref.dtb \
 	uniphier-ph1-sld8-ref.dtb
-dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
 	zynq-zc706.dtb \
 	zynq-zed.dtb \
 	zynq-zybo.dtb \
 	zynq-microzed.dtb \
+	zynq-picozed.dtb \
 	zynq-zc770-xm010.dtb \
 	zynq-zc770-xm012.dtb \
 	zynq-zc770-xm013.dtb
@@ -54,6 +55,9 @@ dtb-$(CONFIG_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_socrates.dtb
 
+dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
+	ls1021a-twr.dtb
+
 targets += $(dtb-y)
 
 DTC_FLAGS += -R 4 -p 0x1000
diff --git a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
index f9b61ba..0ff41d0 100644
--- a/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4210-pinctrl-uboot.dtsi
@@ -2,6 +2,8 @@
  * U-Boot additions to enable a generic Exynos GPIO driver
  *
  * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /{
diff --git a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
index c41d07b..8e5a6c6 100644
--- a/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos4x12-pinctrl-uboot.dtsi
@@ -2,6 +2,8 @@
  * U-Boot additions to enable a generic Exynos GPIO driver
  *
  * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /{
diff --git a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
index 7edb0ca..068c5f6 100644
--- a/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos5250-pinctrl-uboot.dtsi
@@ -2,6 +2,8 @@
  * U-Boot additions to enable a generic Exynos GPIO driver
  *
  * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /{
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
index 7d8be69..e89a94f 100644
--- a/arch/arm/dts/exynos5250-snow.dts
+++ b/arch/arm/dts/exynos5250-snow.dts
@@ -40,9 +40,9 @@
 	};
 
 	i2c4: i2c@12ca0000 {
-		cros-ec@1e {
+		cros_ec: cros-ec@1e {
 			reg = <0x1e>;
-			compatible = "google,cros-ec";
+			compatible = "google,cros-ec-i2c";
 			i2c-max-frequency = <100000>;
 			u-boot,i2c-offset-len = <0>;
 			ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
@@ -65,9 +65,10 @@
 	spi@131b0000 {
 		spi-max-frequency = <1000000>;
 		spi-deactivate-delay = <100>;
-		cros_ec: cros-ec@0 {
-			reg = <0>;
-			compatible = "google,cros-ec";
+
+		embedded-controller {
+			compatible = "google,cros-ec-i2c";
+			reg = <0x1e>;
 			spi-max-frequency = <5000000>;
 			ec-interrupt = <&gpx1 6 GPIO_ACTIVE_LOW>;
 			optimise-flash-write;
@@ -133,6 +134,7 @@
 
 	ehci@12110000 {
 		samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>;
+		status = "okay";
 	};
 
 	xhci@12000000 {
diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 3ad4728..7d8fa28 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -104,12 +104,12 @@
 	spi@12d40000 { /* spi2 */
 		spi-max-frequency = <4000000>;
 		spi-deactivate-delay = <200>;
+
 		cros_ec: cros-ec@0 {
+			compatible = "google,cros-ec-spi";
 			reg = <0>;
-			compatible = "google,cros-ec";
 			spi-half-duplex;
 			spi-max-timeout-ms = <1100>;
-			spi-frame-header = <0xec>;
 			ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
 
 			/*
diff --git a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
index 5a86211..635a1b0 100644
--- a/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
+++ b/arch/arm/dts/exynos54xx-pinctrl-uboot.dtsi
@@ -2,6 +2,8 @@
  * U-Boot additions to enable a generic Exynos GPIO driver
  *
  * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /{
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts b/arch/arm/dts/exynos5800-peach-pi.dts
index 494f764..8c1f616 100644
--- a/arch/arm/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -97,11 +97,10 @@
 		spi-max-frequency = <4000000>;
 		spi-deactivate-delay = <200>;
 		cros_ec: cros-ec@0 {
+			compatible = "google,cros-ec-spi";
 			reg = <0>;
-			compatible = "google,cros-ec";
 			spi-half-duplex;
 			spi-max-timeout-ms = <1100>;
-			spi-frame-header = <0xec>;
 			ec-interrupt = <&gpx1 5 GPIO_ACTIVE_LOW>;
 
 			/*
diff --git a/arch/arm/dts/ls1021a-qds.dts b/arch/arm/dts/ls1021a-qds.dts
new file mode 100644
index 0000000..8367811
--- /dev/null
+++ b/arch/arm/dts/ls1021a-qds.dts
@@ -0,0 +1,216 @@
+/*
+ * Freescale ls1021a QDS board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+	model = "LS1021A QDS Board";
+
+	aliases {
+		enet0_rgmii_phy = &rgmii_phy1;
+		enet1_rgmii_phy = &rgmii_phy2;
+		enet2_rgmii_phy = &rgmii_phy3;
+		enet0_sgmii_phy = &sgmii_phy1c;
+		enet1_sgmii_phy = &sgmii_phy1d;
+		spi0 = &qspi;
+		spi1 = &dspi0;
+	};
+};
+
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	dspiflash: at45db021d@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <16000000>;
+		spi-cpol;
+		spi-cpha;
+		reg = <0>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+
+	pca9547: mux@77 {
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			ds3232: rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			ina220@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+
+			ina220@41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			eeprom@56 {
+				compatible = "atmel,24c512";
+				reg = <0x56>;
+			};
+
+			eeprom@57 {
+				compatible = "atmel,24c512";
+				reg = <0x57>;
+			};
+
+			adt7461a@4c {
+				compatible = "adi,adt7461a";
+				reg = <0x4c>;
+			};
+		};
+	};
+};
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR, NAND Flashes and FPGA on board */
+	ranges = <0x0 0x0 0x60000000 0x08000000
+		  0x2 0x0 0x7e800000 0x00010000
+		  0x3 0x0 0x7fb00000 0x00000100>;
+	status = "okay";
+
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x8000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+
+	fpga: board-control@3,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		reg = <0x3 0x0 0x0000100>;
+		bank-width = <1>;
+		device-width = <1>;
+		ranges = <0 3 0 0x100>;
+
+		mdio-mux-emi1 {
+			compatible = "mdio-mux-mmioreg";
+			mdio-parent-bus = <&mdio0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x54 1>; /* BRDCFG4 */
+			mux-mask = <0xe0>; /* EMI1[2:0] */
+
+			/* Onboard PHYs */
+			ls1021amdio0: mdio@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				rgmii_phy1: ethernet-phy@1 {
+					reg = <0x1>;
+				};
+			};
+
+			ls1021amdio1: mdio@20 {
+				reg = <0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				rgmii_phy2: ethernet-phy@2 {
+					reg = <0x2>;
+				};
+			};
+
+			ls1021amdio2: mdio@40 {
+				reg = <0x40>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				rgmii_phy3: ethernet-phy@3 {
+					reg = <0x3>;
+				};
+			};
+
+			ls1021amdio3: mdio@60 {
+				reg = <0x60>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				sgmii_phy1c: ethernet-phy@1c {
+					reg = <0x1c>;
+				};
+			};
+
+			ls1021amdio4: mdio@80 {
+				reg = <0x80>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				sgmii_phy1d: ethernet-phy@1d {
+					reg = <0x1d>;
+				};
+			};
+		};
+	};
+};
+
+&lpuart0 {
+	status = "okay";
+};
+
+&mdio0 {
+	tbi0: tbi-phy@8 {
+		reg = <0x8>;
+		device_type = "tbi-phy";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a-twr.dts b/arch/arm/dts/ls1021a-twr.dts
new file mode 100644
index 0000000..0e61c07
--- /dev/null
+++ b/arch/arm/dts/ls1021a-twr.dts
@@ -0,0 +1,87 @@
+/*
+ * Freescale ls1021a TWR board device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "ls1021a.dtsi"
+
+/ {
+	model = "LS1021A TWR Board";
+
+	aliases {
+		enet2_rgmii_phy = &rgmii_phy1;
+		enet0_sgmii_phy = &sgmii_phy2;
+		enet1_sgmii_phy = &sgmii_phy0;
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: n25q128a13@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&ifc {
+	#address-cells = <2>;
+	#size-cells = <1>;
+	/* NOR Flash on board */
+	ranges = <0x0 0x0 0x60000000 0x08000000>;
+	status = "okay";
+
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x8000000>;
+		bank-width = <2>;
+		device-width = <1>;
+	};
+};
+
+&lpuart0 {
+	status = "okay";
+};
+
+&mdio0 {
+	sgmii_phy0: ethernet-phy@0 {
+		reg = <0x0>;
+	};
+	rgmii_phy1: ethernet-phy@1 {
+		reg = <0x1>;
+	};
+	sgmii_phy2: ethernet-phy@2 {
+		reg = <0x2>;
+	};
+	tbi1: tbi-phy@1f {
+		reg = <0x1f>;
+		device_type = "tbi-phy";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
new file mode 100644
index 0000000..7fadd7c
--- /dev/null
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -0,0 +1,381 @@
+/*
+ * Freescale ls1021a SOC common device tree source
+ *
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "fsl,ls1021a";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+		serial4 = &lpuart4;
+		serial5 = &lpuart5;
+		sysclk = &sysclk;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@f00 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf00>;
+			clocks = <&cluster1_clk>;
+		};
+
+		cpu@f01 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0xf01>;
+			clocks = <&cluster1_clk>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		device_type = "soc";
+		interrupt-parent = <&gic>;
+		ranges;
+
+		gic: interrupt-controller@1400000 {
+			compatible = "arm,cortex-a7-gic";
+			#interrupt-cells = <3>;
+			interrupt-controller;
+			reg = <0x1401000 0x1000>,
+			      <0x1402000 0x1000>,
+			      <0x1404000 0x2000>,
+			      <0x1406000 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+
+		};
+
+		ifc: ifc@1530000 {
+			compatible = "fsl,ifc", "simple-bus";
+			reg = <0x1530000 0x10000>;
+			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		dcfg: dcfg@1ee0000 {
+			compatible = "fsl,ls1021a-dcfg", "syscon";
+			reg = <0x1ee0000 0x10000>;
+			big-endian;
+		};
+
+		esdhc: esdhc@1560000 {
+			compatible = "fsl,esdhc";
+			reg = <0x1560000 0x10000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			voltage-ranges = <1800 1800 3300 3300>;
+			sdhci,auto-cmd12;
+			big-endian;
+			bus-width = <4>;
+			status = "disabled";
+		};
+
+		scfg: scfg@1570000 {
+			compatible = "fsl,ls1021a-scfg", "syscon";
+			reg = <0x1570000 0x10000>;
+			big-endian;
+		};
+
+		clockgen: clocking@1ee1000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x1ee1000 0x10000>;
+
+			sysclk: sysclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+				clock-output-names = "sysclk";
+			};
+
+			cga_pll1: pll@800 {
+				compatible = "fsl,qoriq-core-pll-2.0";
+				#clock-cells = <1>;
+				reg = <0x800 0x10>;
+				clocks = <&sysclk>;
+				clock-output-names = "cga-pll1", "cga-pll1-div2",
+						     "cga-pll1-div4";
+			};
+
+			platform_clk: pll@c00 {
+				compatible = "fsl,qoriq-core-pll-2.0";
+				#clock-cells = <1>;
+				reg = <0xc00 0x10>;
+				clocks = <&sysclk>;
+				clock-output-names = "platform-clk", "platform-clk-div2";
+			};
+
+			cluster1_clk: clk0c0@0 {
+				compatible = "fsl,qoriq-core-mux-2.0";
+				#clock-cells = <0>;
+				reg = <0x0 0x10>;
+				clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+				clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+				clock-output-names = "cluster1-clk";
+			};
+		};
+
+		dspi0: dspi@2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2100000 0x10000>;
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&platform_clk 1>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
+		dspi1: dspi@2110000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2110000 0x10000>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "dspi";
+			clocks = <&platform_clk 1>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
+		qspi: quadspi@1550000 {
+			compatible = "fsl,vf610-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1550000 0x10000>,
+				<0x40000000 0x4000000>;
+			num-cs = <2>;
+			big-endian;
+			status = "disabled";
+		};
+
+		i2c0: i2c@2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2180000 0x10000>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2190000 0x10000>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@21a0000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x21a0000 0x10000>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "i2c";
+			clocks = <&platform_clk 1>;
+			status = "disabled";
+		};
+
+		uart0: serial@21c0500 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x21c0500 0x100>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart1: serial@21c0600 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x21c0600 0x100>;
+			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart2: serial@21d0500 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x21d0500 0x100>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		uart3: serial@21d0600 {
+			compatible = "fsl,16550-FIFO64", "ns16550a";
+			reg = <0x21d0600 0x100>;
+			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <0>;
+			fifo-size = <15>;
+			status = "disabled";
+		};
+
+		lpuart0: serial@2950000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x2950000 0x1000>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&sysclk>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart1: serial@2960000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x2960000 0x1000>;
+			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart2: serial@2970000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x2970000 0x1000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart3: serial@2980000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x2980000 0x1000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart4: serial@2990000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x2990000 0x1000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		lpuart5: serial@29a0000 {
+			compatible = "fsl,ls1021a-lpuart";
+			reg = <0x29a0000 0x1000>;
+			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "ipg";
+			status = "disabled";
+		};
+
+		wdog0: watchdog@2ad0000 {
+			compatible = "fsl,imx21-wdt";
+			reg = <0x2ad0000 0x10000>;
+			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "wdog-en";
+			big-endian;
+		};
+
+		sai1: sai@2b50000 {
+			compatible = "fsl,vf610-sai";
+			reg = <0x2b50000 0x10000>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "sai";
+			dma-names = "tx", "rx";
+			dmas = <&edma0 1 47>,
+			       <&edma0 1 46>;
+			big-endian;
+			status = "disabled";
+		};
+
+		sai2: sai@2b60000 {
+			compatible = "fsl,vf610-sai";
+			reg = <0x2b60000 0x10000>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&platform_clk 1>;
+			clock-names = "sai";
+			dma-names = "tx", "rx";
+			dmas = <&edma0 1 45>,
+			       <&edma0 1 44>;
+			big-endian;
+			status = "disabled";
+		};
+
+		edma0: edma@2c00000 {
+			#dma-cells = <2>;
+			compatible = "fsl,vf610-edma";
+			reg = <0x2c00000 0x10000>,
+			      <0x2c10000 0x10000>,
+			      <0x2c20000 0x10000>;
+			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "edma-tx", "edma-err";
+			dma-channels = <32>;
+			big-endian;
+			clock-names = "dmamux0", "dmamux1";
+			clocks = <&platform_clk 1>,
+				 <&platform_clk 1>;
+		};
+
+		mdio0: mdio@2d24000 {
+			compatible = "gianfar";
+			device_type = "mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2d24000 0x4000>;
+		};
+
+		usb@8600000 {
+			compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
+			reg = <0x8600000 0x1000>;
+			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+			phy_type = "ulpi";
+		};
+
+		usb3@3100000 {
+			compatible = "snps,dwc3";
+			reg = <0x3100000 0x10000>;
+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "host";
+		};
+	};
+};
diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi
index bd9f97c..9753869 100644
--- a/arch/arm/dts/s5pc100-pinctrl.dtsi
+++ b/arch/arm/dts/s5pc100-pinctrl.dtsi
@@ -2,6 +2,8 @@
  * U-Boot additions to enable a generic Exynos GPIO driver
  *
  * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 / {
diff --git a/arch/arm/dts/s5pc110-pinctrl.dtsi b/arch/arm/dts/s5pc110-pinctrl.dtsi
index d21b6ab..2e9d552 100644
--- a/arch/arm/dts/s5pc110-pinctrl.dtsi
+++ b/arch/arm/dts/s5pc110-pinctrl.dtsi
@@ -2,6 +2,8 @@
  * U-Boot additions to enable a generic Exynos GPIO driver
  *
  * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 / {
diff --git a/arch/arm/dts/skeleton64.dtsi b/arch/arm/dts/skeleton64.dtsi
new file mode 100644
index 0000000..b5d7f36
--- /dev/null
+++ b/arch/arm/dts/skeleton64.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree in the 64 bits version; the bare minimum
+ * needed to boot; just include and add a compatible value.  The
+ * bootloader will typically populate the memory node.
+ */
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0 0 0>; };
+};
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 4e529a1..1b86897 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -25,6 +25,10 @@
 		* to be added to the gmac1 device tree blob.
 		*/
 		ethernet0 = &gmac1;
+
+		spi0 = "/spi@ff705000";		/* QSPI */
+		spi1 = "/spi@fff00000";
+		spi2 = "/spi@fff01000";
 	};
 
 	regulator_3_3v: 3-3-v-regulator {
@@ -72,3 +76,23 @@
 &usb1 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+
+	flash0: n25q00@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 8e1f88c..0b300b9 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -25,6 +25,10 @@
 		 * to be added to the gmac1 device tree blob.
 		 */
 		ethernet0 = &gmac1;
+
+		spi0 = "/spi@ff705000";		/* QSPI */
+		spi1 = "/spi@fff00000";
+		spi2 = "/spi@fff01000";
 	};
 
 	regulator_3_3v: 3-3-v-regulator {
@@ -77,3 +81,23 @@
 &usb1 {
 	status = "okay";
 };
+
+&qspi {
+	status = "okay";
+
+	flash0: n25q00@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts
index c1f35a0..9367193 100644
--- a/arch/arm/dts/tegra124-nyan-big.dts
+++ b/arch/arm/dts/tegra124-nyan-big.dts
@@ -230,6 +230,7 @@
 
 	usb@7d000000 { /* Rear external USB port. */
 		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy@7d000000 {
@@ -246,6 +247,7 @@
 
 	usb@7d008000 { /* Left external USB port. */
 		status = "okay";
+		nvidia,vbus-gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
 	};
 
 	usb-phy@7d008000 {
diff --git a/arch/arm/dts/zynq-picozed.dts b/arch/arm/dts/zynq-picozed.dts
new file mode 100644
index 0000000..686b98f
--- /dev/null
+++ b/arch/arm/dts/zynq-picozed.dts
@@ -0,0 +1,23 @@
+/*
+ * Avnet PicoZed board DTS
+ *
+ * Copyright (C) 2015 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+/dts-v1/;
+#include "zynq-7000.dtsi"
+
+/ {
+	model = "Zynq PicoZed Board";
+	compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x40000000>;
+	};
+};
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 606482f..b9f1ca4 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -22,6 +22,9 @@ ifeq ($(SOC),$(filter $(SOC),mx6))
 obj-$(CONFIG_CMD_SATA) += sata.o
 obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
 endif
+ifeq ($(SOC),$(filter $(SOC),vf610))
+obj-y += ddrmc-vf610.o
+endif
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
 obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c
new file mode 100644
index 0000000..e462631
--- /dev/null
+++ b/arch/arm/imx-common/ddrmc-vf610.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright 2015 Toradex, Inc.
+ *
+ * Based on vf610twr:
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-vf610.h>
+#include <asm/arch/ddrmc-vf610.h>
+
+void ddrmc_setup_iomux(void)
+{
+	static const iomux_v3_cfg_t ddr_pads[] = {
+		VF610_PAD_DDR_A15__DDR_A_15,
+		VF610_PAD_DDR_A14__DDR_A_14,
+		VF610_PAD_DDR_A13__DDR_A_13,
+		VF610_PAD_DDR_A12__DDR_A_12,
+		VF610_PAD_DDR_A11__DDR_A_11,
+		VF610_PAD_DDR_A10__DDR_A_10,
+		VF610_PAD_DDR_A9__DDR_A_9,
+		VF610_PAD_DDR_A8__DDR_A_8,
+		VF610_PAD_DDR_A7__DDR_A_7,
+		VF610_PAD_DDR_A6__DDR_A_6,
+		VF610_PAD_DDR_A5__DDR_A_5,
+		VF610_PAD_DDR_A4__DDR_A_4,
+		VF610_PAD_DDR_A3__DDR_A_3,
+		VF610_PAD_DDR_A2__DDR_A_2,
+		VF610_PAD_DDR_A1__DDR_A_1,
+		VF610_PAD_DDR_A0__DDR_A_0,
+		VF610_PAD_DDR_BA2__DDR_BA_2,
+		VF610_PAD_DDR_BA1__DDR_BA_1,
+		VF610_PAD_DDR_BA0__DDR_BA_0,
+		VF610_PAD_DDR_CAS__DDR_CAS_B,
+		VF610_PAD_DDR_CKE__DDR_CKE_0,
+		VF610_PAD_DDR_CLK__DDR_CLK_0,
+		VF610_PAD_DDR_CS__DDR_CS_B_0,
+		VF610_PAD_DDR_D15__DDR_D_15,
+		VF610_PAD_DDR_D14__DDR_D_14,
+		VF610_PAD_DDR_D13__DDR_D_13,
+		VF610_PAD_DDR_D12__DDR_D_12,
+		VF610_PAD_DDR_D11__DDR_D_11,
+		VF610_PAD_DDR_D10__DDR_D_10,
+		VF610_PAD_DDR_D9__DDR_D_9,
+		VF610_PAD_DDR_D8__DDR_D_8,
+		VF610_PAD_DDR_D7__DDR_D_7,
+		VF610_PAD_DDR_D6__DDR_D_6,
+		VF610_PAD_DDR_D5__DDR_D_5,
+		VF610_PAD_DDR_D4__DDR_D_4,
+		VF610_PAD_DDR_D3__DDR_D_3,
+		VF610_PAD_DDR_D2__DDR_D_2,
+		VF610_PAD_DDR_D1__DDR_D_1,
+		VF610_PAD_DDR_D0__DDR_D_0,
+		VF610_PAD_DDR_DQM1__DDR_DQM_1,
+		VF610_PAD_DDR_DQM0__DDR_DQM_0,
+		VF610_PAD_DDR_DQS1__DDR_DQS_1,
+		VF610_PAD_DDR_DQS0__DDR_DQS_0,
+		VF610_PAD_DDR_RAS__DDR_RAS_B,
+		VF610_PAD_DDR_WE__DDR_WE_B,
+		VF610_PAD_DDR_ODT1__DDR_ODT_0,
+		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+		VF610_PAD_DDR_RESETB,
+	};
+
+	imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
+}
+
+void ddrmc_phy_init(void)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
+	writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
+
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
+	writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
+
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
+	writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
+
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
+	writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
+
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
+	writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
+
+	/* LPDDR2 only parameter */
+	writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
+
+	writel(DDRMC_PHY50_DDR3_MODE |
+		   DDRMC_PHY50_EN_SW_HALF_CYCLE, &ddrmr->phy[50]);
+
+	/* Processor Pad ODT settings */
+	writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
+}
+
+static void ddrmc_ctrl_lvl_init(struct ddrmc_lvl_info *lvl)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+	u32 cr102 = 0, cr105 = 0, cr106 = 0, cr110 = 0;
+
+	if (lvl->wrlvl_reg_en) {
+		writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
+		writel(DDRMC_CR98_WRLVL_DL_0(lvl->wrlvl_dl_0), &ddrmr->cr[98]);
+		writel(DDRMC_CR99_WRLVL_DL_1(lvl->wrlvl_dl_1), &ddrmr->cr[99]);
+	}
+
+	if (lvl->rdlvl_reg_en) {
+		cr102 |= DDRMC_CR102_RDLVL_REG_EN;
+		cr105 |= DDRMC_CR105_RDLVL_DL_0(lvl->rdlvl_dl_0);
+		cr110 |= DDRMC_CR110_RDLVL_DL_1(lvl->rdlvl_dl_1);
+	}
+
+	if (lvl->rdlvl_gt_reg_en) {
+		cr102 |= DDRMC_CR102_RDLVL_GT_REGEN;
+		cr106 |= DDRMC_CR106_RDLVL_GTDL_0(lvl->rdlvl_gt_dl_0);
+		cr110 |= DDRMC_CR110_RDLVL_GTDL_1(lvl->rdlvl_gt_dl_1);
+	}
+
+	writel(cr102, &ddrmr->cr[102]);
+	writel(cr105, &ddrmr->cr[105]);
+	writel(cr106, &ddrmr->cr[106]);
+	writel(cr110, &ddrmr->cr[110]);
+}
+
+void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
+						  struct ddrmc_lvl_info *lvl,
+						  int col_diff, int row_diff)
+{
+	struct ddrmr_regs *ddrmr = (struct ddrmr_regs *)DDR_BASE_ADDR;
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
+	writel(DDRMC_CR02_DRAM_TINIT(timings->tinit), &ddrmr->cr[2]);
+	writel(DDRMC_CR10_TRST_PWRON(timings->trst_pwron), &ddrmr->cr[10]);
+
+	writel(DDRMC_CR11_CKE_INACTIVE(timings->cke_inactive), &ddrmr->cr[11]);
+	writel(DDRMC_CR12_WRLAT(timings->wrlat) |
+		   DDRMC_CR12_CASLAT_LIN(timings->caslat_lin), &ddrmr->cr[12]);
+	writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) |
+		   DDRMC_CR13_TCCD(timings->tccd), &ddrmr->cr[13]);
+	writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) |
+		   DDRMC_CR14_TWTR(timings->twtr) |
+		   DDRMC_CR14_TRAS_MIN(timings->tras_min), &ddrmr->cr[14]);
+	writel(DDRMC_CR16_TMRD(timings->tmrd) |
+		   DDRMC_CR16_TRTP(timings->trtp), &ddrmr->cr[16]);
+	writel(DDRMC_CR17_TRAS_MAX(timings->tras_max) |
+		   DDRMC_CR17_TMOD(timings->tmod), &ddrmr->cr[17]);
+	writel(DDRMC_CR18_TCKESR(timings->tckesr) |
+		   DDRMC_CR18_TCKE(timings->tcke), &ddrmr->cr[18]);
+
+	writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
+	writel(DDRMC_CR21_TRCD_INT(timings->trcd_int) |
+		   DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+
+	writel(DDRMC_CR22_TDAL(timings->tdal), &ddrmr->cr[22]);
+	writel(DDRMC_CR23_BSTLEN(3) |
+		   DDRMC_CR23_TDLL(timings->tdll), &ddrmr->cr[23]);
+	writel(DDRMC_CR24_TRP_AB(timings->trp_ab), &ddrmr->cr[24]);
+
+	writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
+	writel(DDRMC_CR26_TREF(timings->tref) |
+		   DDRMC_CR26_TRFC(timings->trfc), &ddrmr->cr[26]);
+	writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
+	writel(DDRMC_CR29_TPDEX(timings->tpdex), &ddrmr->cr[29]);
+
+	writel(DDRMC_CR30_TXPDLL(timings->txpdll), &ddrmr->cr[30]);
+	writel(DDRMC_CR31_TXSNR(timings->txsnr) |
+		   DDRMC_CR31_TXSR(timings->txsr), &ddrmr->cr[31]);
+	writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
+	writel(DDRMC_CR34_CKSRX(timings->cksrx) |
+		   DDRMC_CR34_CKSRE(timings->cksre), &ddrmr->cr[34]);
+
+	writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
+	writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
+		   DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
+
+	writel(DDRMC_CR41_PHY_INI_STRT_INI_DIS, &ddrmr->cr[41]);
+	writel(DDRMC_CR48_MR1_DA_0(70) |
+		   DDRMC_CR48_MR0_DA_0(1056), &ddrmr->cr[48]);
+
+	writel(DDRMC_CR66_ZQCL(timings->zqcl) |
+		   DDRMC_CR66_ZQINIT(timings->zqinit), &ddrmr->cr[66]);
+	writel(DDRMC_CR67_ZQCS(timings->zqcs), &ddrmr->cr[67]);
+	writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
+
+	writel(DDRMC_CR70_REF_PER_ZQ(timings->ref_per_zq), &ddrmr->cr[70]);
+	writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
+
+	writel(DDRMC_CR73_APREBIT(timings->aprebit) |
+		   DDRMC_CR73_COL_DIFF(col_diff) |
+		   DDRMC_CR73_ROW_DIFF(row_diff), &ddrmr->cr[73]);
+	writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
+		   DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
+		   &ddrmr->cr[74]);
+	writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
+		   DDRMC_CR75_PLEN, &ddrmr->cr[75]);
+	writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
+		   DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
+	writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
+		   DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
+	writel(DDRMC_CR78_Q_FULLNESS(7) |
+		   DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
+	writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
+
+	writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
+
+	writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
+	writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
+	writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
+
+	writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
+	writel(DDRMC_CR96_WLMRD(timings->wlmrd) |
+		   DDRMC_CR96_WLDQSEN(timings->wldqsen), &ddrmr->cr[96]);
+
+	if (lvl != NULL)
+		ddrmc_ctrl_lvl_init(lvl);
+
+	writel(DDRMC_CR117_AXI0_W_PRI(0) |
+		   DDRMC_CR117_AXI0_R_PRI(0), &ddrmr->cr[117]);
+	writel(DDRMC_CR118_AXI1_W_PRI(1) |
+		   DDRMC_CR118_AXI1_R_PRI(1), &ddrmr->cr[118]);
+
+	writel(DDRMC_CR120_AXI0_PRI1_RPRI(2) |
+		   DDRMC_CR120_AXI0_PRI0_RPRI(2), &ddrmr->cr[120]);
+	writel(DDRMC_CR121_AXI0_PRI3_RPRI(2) |
+		   DDRMC_CR121_AXI0_PRI2_RPRI(2), &ddrmr->cr[121]);
+	writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
+		   DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
+	writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+		   DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
+	writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
+
+	writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
+	writel(DDRMC_CR132_WRLAT_ADJ(5) |
+		   DDRMC_CR132_RDLAT_ADJ(6), &ddrmr->cr[132]);
+	writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
+	writel(DDRMC_CR138_PHY_WRLV_MXDL(256) |
+		   DDRMC_CR138_PHYDRAM_CK_EN(1), &ddrmr->cr[138]);
+	writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
+		   DDRMC_CR139_PHY_WRLV_DLL(3) |
+		   DDRMC_CR139_PHY_WRLV_EN(3), &ddrmr->cr[139]);
+	writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
+	writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) |
+		   DDRMC_CR143_RDLV_MXDL(128), &ddrmr->cr[143]);
+	writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+		   DDRMC_CR144_PHY_RDLV_DLL(3) |
+		   DDRMC_CR144_PHY_RDLV_EN(3), &ddrmr->cr[144]);
+	writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
+	writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
+	writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
+	writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
+	writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
+
+	writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
+		   DDRMC_CR154_PAD_ZQ_MODE(1) |
+		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
+	writel(DDRMC_CR155_PAD_ODT_BYTE1(2) |
+		   DDRMC_CR155_PAD_ODT_BYTE0(2), &ddrmr->cr[155]);
+	writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+	writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+		   DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
+
+	ddrmc_phy_init();
+
+	writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
+
+	while (!(readl(&ddrmr->cr[80]) && 0x100))
+		udelay(10);
+}
diff --git a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
index 98fc2b5..2f4a3d1 100644
--- a/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
+++ b/arch/arm/include/asm/arch-am33xx/mux_am43xx.h
@@ -137,14 +137,62 @@ struct pad_signals {
 	int mcasp0_fsr;
 	int mcasp0_axr1;
 	int mcasp0_ahclkx;
-	int xdma_event_intr0;
-	int xdma_event_intr1;
+	int cam0_hd;
+	int cam0_vd;
+	int cam0_field;
+	int cam0_wen;
+	int cam0_pclk;
+	int cam0_data8;
+	int cam0_data9;
+	int cam1_data9;
+	int cam1_data8;
+	int cam1_hd;
+	int cam1_vd;
+	int cam1_pclk;
+	int cam1_field;
+	int cam1_wen;
+	int cam1_data0;
+	int cam1_data1;
+	int cam1_data2;
+	int cam1_data3;
+	int cam1_data4;
+	int cam1_data5;
+	int cam1_data6;
+	int cam1_data7;
+	int cam0_data0;
+	int cam0_data1;
+	int cam0_data2;
+	int cam0_data3;
+	int cam0_data4;
+	int cam0_data5;
+	int cam0_data6;
+	int cam0_data7;
+	int uart3_rxd;
+	int uart3_txd;
+	int uart3_ctsn;
+	int uart3_rtsn;
+	int gpio5_8;
+	int gpio5_9;
+	int gpio5_10;
+	int gpio5_11;
+	int gpio5_12;
+	int gpio5_13;
+	int spi4_sclk;
+	int spi4_d0;
+	int spi4_d1;
+	int spi4_cs0;
+	int spi2_sclk;
+	int spi2_d0;
+	int spi2_d1;
+	int spi2_cs0;
+	int xdma_evt_intr0;
+	int xdma_evt_intr1;
+	int clkreq;
 	int nresetin_out;
-	int porz;
-	int nnmi;
-	int osc0_in;
-	int osc0_out;
 	int rsvd1;
+	int nnmi;
+	int rsvd2;
+	int rsvd3;
 	int tms;
 	int tdi;
 	int tdo;
@@ -154,34 +202,11 @@ struct pad_signals {
 	int emu1;
 	int osc1_in;
 	int osc1_out;
-	int pmic_power_en;
 	int rtc_porz;
-	int rsvd2;
-	int ext_wakeup;
-	int enz_kaldo_1p8v;
-	int usb0_dm;
-	int usb0_dp;
-	int usb0_ce;
-	int usb0_id;
-	int usb0_vbus;
+	int ext_wakeup0;
+	int pmic_power_en0;
 	int usb0_drvvbus;
-	int usb1_dm;
-	int usb1_dp;
-	int usb1_ce;
-	int usb1_id;
-	int usb1_vbus;
 	int usb1_drvvbus;
-	int ddr_resetn;
-	int ddr_csn0;
-	int ddr_cke;
-	int ddr_ck;
-	int ddr_nck;
-	int ddr_casn;
-	int ddr_rasn;
-	int ddr_wen;
-	int ddr_ba0;
-	int ddr_ba1;
-	int ddr_ba2;
 };
 
 #endif /* _MUX_AM43XX_H_ */
diff --git a/arch/arm/include/asm/arch-arm720t/hardware.h b/arch/arm/include/asm/arch-arm720t/hardware.h
deleted file mode 100644
index 8ca42d9..0000000
--- a/arch/arm/include/asm/arch-arm720t/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __ARM7_HW_H
-#define __ARM7_HW_H
-
-/*
- * Copyright (c) 2004	Cucy Systems (http://www.cucy.com)
- * Curt Brune <curt@cucy.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#if defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
-/* include IntegratorCP/CM720T specific hardware file if there was one */
-#else
-#error No hardware file defined for this configuration
-#endif
-
-#endif /* __ARM7_HW_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index b140c1f..ca8d38c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -8,6 +8,14 @@
 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
 
 #include <fsl_ddrc_version.h>
+
+#define CONFIG_SYS_PAGE_SIZE		0x10000
+
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT		6
+#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
+#endif
+
 #define CONFIG_MP
 #define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000	/* initial RAM */
 /* Link Definitions */
@@ -23,6 +31,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR	(CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR	(CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR	(CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011C0600)
@@ -30,6 +39,20 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR		(CONFIG_SYS_FSL_PMU_ADDR + \
 						 0x18A0)
 
+#define CONFIG_SYS_FSL_WRIOP1_ADDR		(CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2	(CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR	(CONFIG_SYS_IMMR + 0xEA0000)
+
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR			(CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR		(CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1		(CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2		\
+					(CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART	\
+					(CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR		0x70012c000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR		0x70012d000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR		0x700132000ULL
@@ -88,22 +111,57 @@
 #define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
 
-
+#define CONFIG_SYS_FSL_ESDHC_LE
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR			(CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR		0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE		0x04000000
+#define CCI_MN_RNF_NODEID_LIST		0x180
+#define CCI_MN_DVM_DOMAIN_CTL		0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET	0x210
+
+/* Device Configuration */
+#define DCFG_BASE		0x01e00000
+#define DCFG_PORSR1			0x000
+#define DCFG_PORSR1_RCW_SRC		0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR		0x12f00000
+
+#define DCFG_DCSR_BASE		0X700100000ULL
+#define DCFG_DCSR_PORCR1		0x000
+
+/* Supplemental Configuration */
+#define SCFG_BASE		0x01fc0000
+#define SCFG_USB3PRM1CR			0x000
 
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS				16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT		8
 #define CONFIG_NUM_DDR_CONTROLLERS		3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #else
 #error SoC not defined
 #endif
 
 #ifdef CONFIG_LS2085A
 #define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
 #endif
 
 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
new file mode 100644
index 0000000..2810f3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/fsl_serdes.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SERDES_H
+#define __FSL_SERDES_H
+
+#include <config.h>
+
+#define	SRDS_MAX_LANES	8
+
+enum srds_prtcl {
+	NONE = 0,
+	PCIE1,
+	PCIE2,
+	PCIE3,
+	PCIE4,
+	SATA1,
+	SATA2,
+	XAUI1,
+	XAUI2,
+	XFI1,
+	XFI2,
+	XFI3,
+	XFI4,
+	XFI5,
+	XFI6,
+	XFI7,
+	XFI8,
+	SGMII1,
+	SGMII2,
+	SGMII3,
+	SGMII4,
+	SGMII5,
+	SGMII6,
+	SGMII7,
+	SGMII8,
+	SGMII9,
+	SGMII10,
+	SGMII11,
+	SGMII12,
+	SGMII13,
+	SGMII14,
+	SGMII15,
+	SGMII16,
+	QSGMII_A, /* A indicates MACs 1-4 */
+	QSGMII_B, /* B indicates MACs 5-8 */
+	QSGMII_C, /* C indicates MACs 9-12 */
+	QSGMII_D, /* D indicates MACs 12-16 */
+	SERDES_PRCTL_COUNT
+};
+
+enum srds {
+	FSL_SRDS_1  = 0,
+	FSL_SRDS_2  = 1,
+};
+
+int is_serdes_configured(enum srds_prtcl device);
+void fsl_serdes_init(void);
+
+int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
+int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+
+#endif /* __FSL_SERDES_H */
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index dd11ef7..d6bee60 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -47,6 +47,30 @@ struct ccsr_gur {
 	u32	devdisr5;	/* Device disable control 5 */
 	u32	devdisr6;	/* Device disable control 6 */
 	u32	devdisr7;	/* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1	0x00000001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2	0x00000002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3	0x00000004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4	0x00000008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5	0x00000010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6	0x00000020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7	0x00000040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8	0x00000080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9	0x00000100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10	0x00000200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11	0x00000400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12	0x00000800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13	0x00001000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14	0x00002000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15	0x00004000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16	0x00008000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17	0x00010000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18	0x00020000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19	0x00040000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20	0x00080000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21	0x00100000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22	0x00200000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23	0x00400000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24	0x00800000
 	u8	res_08c[0x90-0x8c];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
 	u32	coredisrl;	/* lower portion for support of 64 cores */
@@ -63,6 +87,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT	18
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK	0x3f
+#define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK	0x00FF0000
+#define	FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT	16
+#define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK	0xFF000000
+#define	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT	24
+
 	u8	res_180[0x200-0x180];
 	u32	scratchrw[32];	/* Scratch Read/Write */
 	u8	res_280[0x300-0x280];
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/soc.h b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
new file mode 100644
index 0000000..16b723d
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-lsch3/soc.h
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+void fsl_lsch3_early_init_f(void);
+
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 6561ce6..4dc528b 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -119,10 +119,6 @@
 
 #define DCU_LAYER_MAX_NUM			16
 
-#define QE_MURAM_SIZE          0x6000UL
-#define MAX_QE_RISC            1
-#define QE_NUM_OF_SNUM         28
-
 #define CONFIG_SYS_FSL_SRDS_1
 
 #ifdef CONFIG_LS102XA
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 3a64afc..a8122c1 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
 #define SOC_VER_LS1021		0x11
 #define SOC_VER_LS1022		0x12
 
+#define SOC_MAJOR_VER_1_0	0x1
+#define SOC_MAJOR_VER_2_0	0x2
+
 #define CCSR_BRR_OFFSET		0xe4
 #define CCSR_SCRATCHRW1_OFFSET	0x200
 
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 8e0d7d1..c49aa62 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -250,6 +250,7 @@ struct mx6_ddr_sysinfo {
 	u8 mif3_mode;	/* Command prediction working mode */
 	u8 rst_to_cke;	/* Time from SDE enable to CKE rise */
 	u8 sde_to_rst;	/* Time from SDE enable until DDR reset# is high */
+	u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 };
 
 /*
diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h
index 034135b..d63a285 100644
--- a/arch/arm/include/asm/arch-socfpga/reset_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/reset_manager.h
@@ -15,6 +15,9 @@ void socfpga_bridges_reset(int enable);
 void socfpga_emac_reset(int enable);
 void socfpga_watchdog_reset(void);
 void socfpga_spim_enable(void);
+void socfpga_uart0_enable(void);
+void socfpga_sdram_enable(void);
+void socfpga_osc1timer_enable(void);
 
 struct socfpga_reset_manager {
 	u32	status;
@@ -36,7 +39,10 @@ struct socfpga_reset_manager {
 #define RSTMGR_PERMODRST_EMAC0_LSB	0
 #define RSTMGR_PERMODRST_EMAC1_LSB	1
 #define RSTMGR_PERMODRST_L4WD0_LSB	6
+#define RSTMGR_PERMODRST_OSC1TIMER0_LSB	8
+#define RSTMGR_PERMODRST_UART0_LSB	16
 #define RSTMGR_PERMODRST_SPIM0_LSB	18
 #define RSTMGR_PERMODRST_SPIM1_LSB	19
+#define RSTMGR_PERMODRST_SDR_LSB	29
 
 #endif /* _RESET_MANAGER_H_ */
diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h
new file mode 100644
index 0000000..4f6489d
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/sdram.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * FIXME: This file contains temporary stub functions and is here
+ *        only until these functions are properly merged into
+ *        mainline.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_SDRAM_H__
+#define __ARCH_SDRAM_H__
+
+/* function declaration */
+inline unsigned long sdram_calculate_size(void) { return 0; }
+inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; }
+inline int sdram_calibration_full(void) { return 0; }
+
+#endif	/* __ARCH_SDRAM_H__ */
diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h
index 071ec4f..51d9815 100644
--- a/arch/arm/include/asm/arch-socfpga/system_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
@@ -10,6 +10,7 @@
 #ifndef __ASSEMBLY__
 
 void sysmgr_pinmux_init(void);
+void sysmgr_enable_warmrstcfgio(void);
 
 /* declaration for handoff table type */
 extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM];
diff --git a/arch/arm/include/asm/arch-stm32f4/fmc.h b/arch/arm/include/asm/arch-stm32f4/fmc.h
new file mode 100644
index 0000000..4ab3031
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/fmc.h
@@ -0,0 +1,75 @@
+/*
+ * (C) Copyright 2013
+ * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MACH_FMC_H_
+#define _MACH_FMC_H_
+
+struct stm32_fmc_regs {
+	u32 sdcr1;	/* Control register 1 */
+	u32 sdcr2;	/* Control register 2 */
+	u32 sdtr1;	/* Timing register 1 */
+	u32 sdtr2;	/* Timing register 2 */
+	u32 sdcmr;	/* Mode register */
+	u32 sdrtr;	/* Refresh timing register */
+	u32 sdsr;	/* Status register */
+};
+
+/*
+ * FMC registers base
+ */
+#define STM32_SDRAM_FMC_BASE	0xA0000140
+#define STM32_SDRAM_FMC		((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE)
+
+/* Control register SDCR */
+#define FMC_SDCR_RPIPE_SHIFT	13	/* RPIPE bit shift */
+#define FMC_SDCR_RBURST_SHIFT	12	/* RBURST bit shift */
+#define FMC_SDCR_SDCLK_SHIFT	10	/* SDRAM clock divisor shift */
+#define FMC_SDCR_WP_SHIFT	9	/* Write protection shift */
+#define FMC_SDCR_CAS_SHIFT	7	/* CAS latency shift */
+#define FMC_SDCR_NB_SHIFT	6	/* Number of banks shift */
+#define FMC_SDCR_MWID_SHIFT	4	/* Memory width shift */
+#define FMC_SDCR_NR_SHIFT	2	/* Number of row address bits shift */
+#define FMC_SDCR_NC_SHIFT	0	/* Number of col address bits shift */
+
+/* Timings register SDTR */
+#define FMC_SDTR_TMRD_SHIFT	0	/* Load mode register to active */
+#define FMC_SDTR_TXSR_SHIFT	4	/* Exit self-refresh time */
+#define FMC_SDTR_TRAS_SHIFT	8	/* Self-refresh time */
+#define FMC_SDTR_TRC_SHIFT	12	/* Row cycle delay */
+#define FMC_SDTR_TWR_SHIFT	16	/* Recovery delay */
+#define FMC_SDTR_TRP_SHIFT	20	/* Row precharge delay */
+#define FMC_SDTR_TRCD_SHIFT	24	/* Row-to-column delay */
+
+
+#define FMC_SDCMR_NRFS_SHIFT	5
+
+#define FMC_SDCMR_MODE_NORMAL		0
+#define FMC_SDCMR_MODE_START_CLOCK	1
+#define FMC_SDCMR_MODE_PRECHARGE	2
+#define FMC_SDCMR_MODE_AUTOREFRESH	3
+#define FMC_SDCMR_MODE_WRITE_MODE	4
+#define FMC_SDCMR_MODE_SELFREFRESH	5
+#define FMC_SDCMR_MODE_POWERDOWN	6
+
+#define FMC_SDCMR_BANK_1		(1 << 4)
+#define FMC_SDCMR_BANK_2		(1 << 3)
+
+#define FMC_SDCMR_MODE_REGISTER_SHIFT	9
+
+#define FMC_SDSR_BUSY			(1 << 5)
+
+#define FMC_BUSY_WAIT()		do { \
+		__asm__ __volatile__ ("dsb" : : : "memory"); \
+		while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \
+			; \
+	} while (0)
+
+
+#endif /* _MACH_FMC_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/gpio.h b/arch/arm/include/asm/arch-stm32f4/gpio.h
new file mode 100644
index 0000000..7cd866e
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/gpio.h
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _STM32_GPIO_H_
+#define _STM32_GPIO_H_
+
+enum stm32_gpio_port {
+	STM32_GPIO_PORT_A = 0,
+	STM32_GPIO_PORT_B,
+	STM32_GPIO_PORT_C,
+	STM32_GPIO_PORT_D,
+	STM32_GPIO_PORT_E,
+	STM32_GPIO_PORT_F,
+	STM32_GPIO_PORT_G,
+	STM32_GPIO_PORT_H,
+	STM32_GPIO_PORT_I
+};
+
+enum stm32_gpio_pin {
+	STM32_GPIO_PIN_0 = 0,
+	STM32_GPIO_PIN_1,
+	STM32_GPIO_PIN_2,
+	STM32_GPIO_PIN_3,
+	STM32_GPIO_PIN_4,
+	STM32_GPIO_PIN_5,
+	STM32_GPIO_PIN_6,
+	STM32_GPIO_PIN_7,
+	STM32_GPIO_PIN_8,
+	STM32_GPIO_PIN_9,
+	STM32_GPIO_PIN_10,
+	STM32_GPIO_PIN_11,
+	STM32_GPIO_PIN_12,
+	STM32_GPIO_PIN_13,
+	STM32_GPIO_PIN_14,
+	STM32_GPIO_PIN_15
+};
+
+enum stm32_gpio_mode {
+	STM32_GPIO_MODE_IN = 0,
+	STM32_GPIO_MODE_OUT,
+	STM32_GPIO_MODE_AF,
+	STM32_GPIO_MODE_AN
+};
+
+enum stm32_gpio_otype {
+	STM32_GPIO_OTYPE_PP = 0,
+	STM32_GPIO_OTYPE_OD
+};
+
+enum stm32_gpio_speed {
+	STM32_GPIO_SPEED_2M = 0,
+	STM32_GPIO_SPEED_25M,
+	STM32_GPIO_SPEED_50M,
+	STM32_GPIO_SPEED_100M
+};
+
+enum stm32_gpio_pupd {
+	STM32_GPIO_PUPD_NO = 0,
+	STM32_GPIO_PUPD_UP,
+	STM32_GPIO_PUPD_DOWN
+};
+
+enum stm32_gpio_af {
+	STM32_GPIO_AF0 = 0,
+	STM32_GPIO_AF1,
+	STM32_GPIO_AF2,
+	STM32_GPIO_AF3,
+	STM32_GPIO_AF4,
+	STM32_GPIO_AF5,
+	STM32_GPIO_AF6,
+	STM32_GPIO_AF7,
+	STM32_GPIO_AF8,
+	STM32_GPIO_AF9,
+	STM32_GPIO_AF10,
+	STM32_GPIO_AF11,
+	STM32_GPIO_AF12,
+	STM32_GPIO_AF13,
+	STM32_GPIO_AF14,
+	STM32_GPIO_AF15
+};
+
+struct stm32_gpio_dsc {
+	enum stm32_gpio_port	port;
+	enum stm32_gpio_pin	pin;
+};
+
+struct stm32_gpio_ctl {
+	enum stm32_gpio_mode	mode;
+	enum stm32_gpio_otype	otype;
+	enum stm32_gpio_speed	speed;
+	enum stm32_gpio_pupd	pupd;
+	enum stm32_gpio_af	af;
+};
+
+static inline unsigned stm32_gpio_to_port(unsigned gpio)
+{
+	return gpio / 16;
+}
+
+static inline unsigned stm32_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 16;
+}
+
+int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc,
+		const struct stm32_gpio_ctl *gpio_ctl);
+int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state);
+
+#endif /* _STM32_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-stm32f4/stm32.h b/arch/arm/include/asm/arch-stm32f4/stm32.h
new file mode 100644
index 0000000..a9f88db
--- /dev/null
+++ b/arch/arm/include/asm/arch-stm32f4/stm32.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2011
+ * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MACH_STM32_H_
+#define _MACH_STM32_H_
+
+/*
+ * Peripheral memory map
+ */
+#define STM32_PERIPH_BASE	0x40000000
+#define STM32_APB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00000000)
+#define STM32_APB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x00010000)
+#define STM32_AHB1PERIPH_BASE	(STM32_PERIPH_BASE + 0x00020000)
+#define STM32_AHB2PERIPH_BASE	(STM32_PERIPH_BASE + 0x10000000)
+
+#define STM32_BUS_MASK		0xFFFF0000
+
+/*
+ * Register maps
+ */
+struct stm32_rcc_regs {
+	u32 cr;		/* RCC clock control */
+	u32 pllcfgr;	/* RCC PLL configuration */
+	u32 cfgr;	/* RCC clock configuration */
+	u32 cir;	/* RCC clock interrupt */
+	u32 ahb1rstr;	/* RCC AHB1 peripheral reset */
+	u32 ahb2rstr;	/* RCC AHB2 peripheral reset */
+	u32 ahb3rstr;	/* RCC AHB3 peripheral reset */
+	u32 rsv0;
+	u32 apb1rstr;	/* RCC APB1 peripheral reset */
+	u32 apb2rstr;	/* RCC APB2 peripheral reset */
+	u32 rsv1[2];
+	u32 ahb1enr;	/* RCC AHB1 peripheral clock enable */
+	u32 ahb2enr;	/* RCC AHB2 peripheral clock enable */
+	u32 ahb3enr;	/* RCC AHB3 peripheral clock enable */
+	u32 rsv2;
+	u32 apb1enr;	/* RCC APB1 peripheral clock enable */
+	u32 apb2enr;	/* RCC APB2 peripheral clock enable */
+	u32 rsv3[2];
+	u32 ahb1lpenr;	/* RCC AHB1 periph clk enable in low pwr mode */
+	u32 ahb2lpenr;	/* RCC AHB2 periph clk enable in low pwr mode */
+	u32 ahb3lpenr;	/* RCC AHB3 periph clk enable in low pwr mode */
+	u32 rsv4;
+	u32 apb1lpenr;	/* RCC APB1 periph clk enable in low pwr mode */
+	u32 apb2lpenr;	/* RCC APB2 periph clk enable in low pwr mode */
+	u32 rsv5[2];
+	u32 bdcr;	/* RCC Backup domain control */
+	u32 csr;	/* RCC clock control & status */
+	u32 rsv6[2];
+	u32 sscgr;	/* RCC spread spectrum clock generation */
+	u32 plli2scfgr;	/* RCC PLLI2S configuration */
+	u32 pllsaicfgr;
+	u32 dckcfgr;
+};
+
+struct stm32_pwr_regs {
+	u32 cr;
+	u32 csr;
+};
+
+struct stm32_flash_regs {
+	u32 acr;
+	u32 key;
+	u32 optkeyr;
+	u32 sr;
+	u32 cr;
+	u32 optcr;
+	u32 optcr1;
+};
+
+/*
+ * Registers access macros
+ */
+#define STM32_RCC_BASE		(STM32_AHB1PERIPH_BASE + 0x3800)
+#define STM32_RCC		((struct stm32_rcc_regs *)STM32_RCC_BASE)
+
+#define STM32_PWR_BASE		(STM32_APB1PERIPH_BASE + 0x7000)
+#define STM32_PWR		((struct stm32_pwr_regs *)STM32_PWR_BASE)
+
+#define STM32_FLASH_BASE	(STM32_AHB1PERIPH_BASE + 0x3C00)
+#define STM32_FLASH		((struct stm32_flash_regs *)STM32_FLASH_BASE)
+
+#define STM32_FLASH_SR_BSY		(1 << 16)
+
+#define STM32_FLASH_CR_PG		(1 << 0)
+#define STM32_FLASH_CR_SER		(1 << 1)
+#define STM32_FLASH_CR_STRT		(1 << 16)
+#define STM32_FLASH_CR_LOCK		(1 << 31)
+#define STM32_FLASH_CR_SNB_OFFSET	3
+
+enum clock {
+	CLOCK_CORE,
+	CLOCK_AHB,
+	CLOCK_APB1,
+	CLOCK_APB2
+};
+
+int configure_clocks(void);
+unsigned long clock_get(enum clock clck);
+
+#endif /* _MACH_STM32_H_ */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index dae6069..f403742 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -94,6 +94,13 @@
 #define SUNXI_TWI0_BASE			0x01c2ac00
 #define SUNXI_TWI1_BASE			0x01c2b000
 #define SUNXI_TWI2_BASE			0x01c2b400
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_TWI3_BASE			0x01c0b800
+#endif
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_TWI3_BASE			0x01c2b800
+#define SUNXI_TWI4_BASE			0x01c2c000
+#endif
 
 #define SUNXI_CAN_BASE			0x01c2bc00
 
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f2c247d..ae7cbb7 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -84,7 +84,7 @@ struct sunxi_gpio_reg {
 #define GPIO_CFG_INDEX(pin)	(((pin) & 0x1f) >> 3)
 #define GPIO_CFG_OFFSET(pin)	((((pin) & 0x1f) & 0x7) << 2)
 
-#define GPIO_DRV_INDEX(pin)   (((pin) & 0x1f) >> 4)
+#define GPIO_DRV_INDEX(pin)	(((pin) & 0x1f) >> 4)
 #define GPIO_DRV_OFFSET(pin)	((((pin) & 0x1f) & 0xf) << 1)
 
 #define GPIO_PULL_INDEX(pin)	(((pin) & 0x1f) >> 4)
@@ -142,71 +142,77 @@ enum sunxi_gpio_number {
 #define SUNXI_GPIO_INPUT	0
 #define SUNXI_GPIO_OUTPUT	1
 
-#define SUNXI_GPA0_EMAC		2
-#define SUN6I_GPA0_GMAC		2
-#define SUN7I_GPA0_GMAC		5
-
-#define SUNXI_GPB0_TWI0		2
-
-#define SUN4I_GPB22_UART0_TX	2
-#define SUN4I_GPB23_UART0_RX	2
-
-#define SUN5I_GPB19_UART0_TX	2
-#define SUN5I_GPB20_UART0_RX	2
-
-#define SUNXI_GPC6_SDC2		3
-
-#define SUNXI_GPD0_LCD0		2
-#define SUNXI_GPD0_LVDS0	3
-
-#define SUNXI_GPF0_SDC0		2
-
-#define SUNXI_GPF2_SDC0		2
-
-#ifdef CONFIG_MACH_SUN8I
-#define SUNXI_GPF2_UART0_TX	3
-#define SUNXI_GPF4_UART0_RX	3
-#else
-#define SUNXI_GPF2_UART0_TX	4
-#define SUNXI_GPF4_UART0_RX	4
-#endif
-
-#define SUN4I_GPG0_SDC1		4
-
-#define SUN5I_GPG3_SDC1		2
-
-#define SUN5I_GPG3_UART1_TX	4
-#define SUN5I_GPG4_UART1_RX	4
-
-#define SUN4I_GPH22_SDC1	5
-
-#define SUN6I_GPH20_UART0_TX	2
-#define SUN6I_GPH21_UART0_RX	2
-
-#define SUN4I_GPI4_SDC3		2
+#define SUNXI_GPA_EMAC		2
+#define SUN6I_GPA_GMAC		2
+#define SUN7I_GPA_GMAC		5
+#define SUN6I_GPA_SDC2		5
+#define SUN6I_GPA_SDC3		4
+
+#define SUN4I_GPB_TWI0		2
+#define SUN4I_GPB_TWI1		2
+#define SUN5I_GPB_TWI1		2
+#define SUN4I_GPB_TWI2		2
+#define SUN5I_GPB_TWI2		2
+#define SUN4I_GPB_UART0		2
+#define SUN5I_GPB_UART0		2
+
+#define SUNXI_GPC_SDC2		3
+#define SUN6I_GPC_SDC3		4
+
+#define SUN8I_GPD_SDC1		3
+#define SUNXI_GPD_LCD0		2
+#define SUNXI_GPD_LVDS0		3
+
+#define SUN5I_GPE_SDC2		3
+#define SUN8I_GPE_TWI2		3
+
+#define SUNXI_GPF_SDC0		2
+#define SUNXI_GPF_UART0		4
+#define SUN8I_GPF_UART0		3
+
+#define SUN4I_GPG_SDC1		4
+#define SUN5I_GPG_SDC1		2
+#define SUN6I_GPG_SDC1		2
+#define SUN8I_GPG_SDC1		2
+#define SUN6I_GPG_TWI3		2
+#define SUN5I_GPG_UART1		4
+
+#define SUN4I_GPH_SDC1		5
+#define SUN6I_GPH_TWI0		2
+#define SUN8I_GPH_TWI0		2
+#define SUN6I_GPH_TWI1		2
+#define SUN8I_GPH_TWI1		2
+#define SUN6I_GPH_TWI2		2
+#define SUN6I_GPH_UART0		2
+
+#define SUNXI_GPI_SDC3		2
+#define SUN7I_GPI_TWI3		3
+#define SUN7I_GPI_TWI4		3
 
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
 
-#define SUN8I_GPL0_R_RSB_SCK	2
-#define SUN8I_GPL1_R_RSB_SDA	2
-#define SUN8I_GPL2_R_UART_TX	2
-#define SUN8I_GPL3_R_UART_RX	2
+#define SUN8I_GPL_R_RSB		2
+#define SUN8I_GPL_R_UART	2
 
-#define SUN9I_GPN0_R_RSB_SCK	3
-#define SUN9I_GPN1_R_RSB_SDA    3
+#define SUN9I_GPN_R_RSB		3
 
 /* GPIO pin pull-up/down config */
 #define SUNXI_GPIO_PULL_DISABLE	0
 #define SUNXI_GPIO_PULL_UP	1
 #define SUNXI_GPIO_PULL_DOWN	2
 
+/* Virtual AXP0 GPIOs */
+#define SUNXI_GPIO_AXP0_VBUS_DETECT	8
+#define SUNXI_GPIO_AXP0_VBUS_ENABLE	9
+
 void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val);
 void sunxi_gpio_set_cfgpin(u32 pin, u32 val);
 int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset);
 int sunxi_gpio_get_cfgpin(u32 pin);
 int sunxi_gpio_set_drv(u32 pin, u32 val);
 int sunxi_gpio_set_pull(u32 pin, u32 val);
+int sunxi_name_to_gpio_bank(const char *name);
 int sunxi_name_to_gpio(const char *name);
 #define name_to_gpio(name) sunxi_name_to_gpio(name)
 
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index dc5406b..561cd2b 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -8,7 +8,22 @@
 
 #include <asm/arch/cpu.h>
 
-#define CONFIG_I2C_MVTWSI_BASE	SUNXI_TWI0_BASE
+#ifdef CONFIG_I2C0_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
+#endif
+#ifdef CONFIG_I2C1_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
+#endif
+#ifdef CONFIG_I2C2_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE2	SUNXI_TWI2_BASE
+#endif
+#ifdef CONFIG_I2C3_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE3	SUNXI_TWI3_BASE
+#endif
+#ifdef CONFIG_I2C4_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
+#endif
+
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
 #define CONFIG_SYS_TCLK		24000000
 
diff --git a/arch/arm/include/asm/arch-sunxi/usbc.h b/arch/arm/include/asm/arch-sunxi/usbc.h
index 1330733..ab0f272 100644
--- a/arch/arm/include/asm/arch-sunxi/usbc.h
+++ b/arch/arm/include/asm/arch-sunxi/usbc.h
@@ -20,4 +20,5 @@ void sunxi_usbc_enable(int index);
 void sunxi_usbc_disable(int index);
 void sunxi_usbc_vbus_enable(int index);
 void sunxi_usbc_vbus_disable(int index);
+int sunxi_usbc_vbus_detect(int index);
 void sunxi_usbc_enable_squelch_detect(int index, int enable);
diff --git a/arch/arm/include/asm/arch-tegra114/hardware.h b/arch/arm/include/asm/arch-tegra114/hardware.h
deleted file mode 100644
index c21fbb6..0000000
--- a/arch/arm/include/asm/arch-tegra114/hardware.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _TEGRA114_HARDWARE_H_
-#define _TEGRA114_HARDWARE_H_
-
-/* include tegra specific hardware definitions */
-
-#endif /* _TEGRA114_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra124/hardware.h b/arch/arm/include/asm/arch-tegra124/hardware.h
deleted file mode 100644
index 114fce8..0000000
--- a/arch/arm/include/asm/arch-tegra124/hardware.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * (C) Copyright 2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#ifndef _TEGRA124_HARDWARE_H_
-#define _TEGRA124_HARDWARE_H_
-
-/*
- * Include Tegra-specific hardware definitions
- * Nothing needed currently for Tegra124
- */
-
-#endif /* _TEGRA124_HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra20/hardware.h b/arch/arm/include/asm/arch-tegra20/hardware.h
deleted file mode 100644
index a295894..0000000
--- a/arch/arm/include/asm/arch-tegra20/hardware.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
-* (C) Copyright 2010-2011
-* NVIDIA Corporation <www.nvidia.com>
-*
- * SPDX-License-Identifier:	GPL-2.0+
-*/
-
-#ifndef __TEGRA2_HW_H
-#define __TEGRA2_HW_H
-
-/* include tegra specific hardware definitions */
-
-#endif /* __TEGRA2_HW_H */
diff --git a/arch/arm/include/asm/arch-tegra30/hardware.h b/arch/arm/include/asm/arch-tegra30/hardware.h
deleted file mode 100644
index b1a5aa9..0000000
--- a/arch/arm/include/asm/arch-tegra30/hardware.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _TEGRA30_HARDWARE_H_
-#define _TEGRA30_HARDWARE_H_
-
-/* include tegra specific hardware definitions */
-
-#endif /* _TEGRA30-HARDWARE_H_ */
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 724682c..bc6db2a 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -189,6 +189,7 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK			0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK		(0x3 << 16)
+#define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK			(0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK		(0x3 << 8)
@@ -199,6 +200,7 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTD_CTRL_MASK		(0x3 << 24)
 #define CCM_CCGR2_PORTE_CTRL_MASK		(0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK		0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
 #define CCM_CCGR4_WKUP_CTRL_MASK		(0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK			(0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK			(0x3 << 24)
@@ -206,14 +208,23 @@ struct anadig_reg {
 #define CCM_CCGR6_OCOTP_CTRL_MASK		(0x3 << 10)
 #define CCM_CCGR6_DDRMC_CTRL_MASK		(0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK		(0x3 << 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR9_FEC0_CTRL_MASK		0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK		(0x3 << 2)
 #define CCM_CCGR10_NFC_CTRL_MASK		0x3
 
+#define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT     (1 << 1)
 #define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
 #define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
 #define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
 #define ANADIG_PLL5_CTRL_DIV_SELECT		1
+#define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL3_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT     (1 << 1)
 #define ANADIG_PLL2_CTRL_ENABLE			(1 << 13)
 #define ANADIG_PLL2_CTRL_POWERDOWN		(1 << 12)
 #define ANADIG_PLL2_CTRL_DIV_SELECT		1
diff --git a/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
new file mode 100644
index 0000000..6730cde
--- /dev/null
+++ b/arch/arm/include/asm/arch-vf610/ddrmc-vf610.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2015
+ * Toradex, Inc.
+ *
+ * Authors: Stefan Agner
+ *          Sanchayan Maity
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_VF610_DDRMC_H
+#define __ASM_ARCH_VF610_DDRMC_H
+
+struct ddrmc_lvl_info {
+	u16 wrlvl_reg_en;
+	u16 wrlvl_dl_0;
+	u16 wrlvl_dl_1;
+	u16 rdlvl_gt_reg_en;
+	u16 rdlvl_gt_dl_0;
+	u16 rdlvl_gt_dl_1;
+	u16 rdlvl_reg_en;
+	u16 rdlvl_dl_0;
+	u16 rdlvl_dl_1;
+};
+
+struct ddr3_jedec_timings {
+	u8 tinit;
+	u32 trst_pwron;
+	u32 cke_inactive;
+	u8 wrlat;
+	u8 caslat_lin;
+	u8 trc;
+	u8 trrd;
+	u8 tccd;
+	u8 tfaw;
+	u8 trp;
+	u8 twtr;
+	u8 tras_min;
+	u8 tmrd;
+	u8 trtp;
+	u32 tras_max;
+	u8 tmod;
+	u8 tckesr;
+	u8 tcke;
+	u8 trcd_int;
+	u8 tdal;
+	u16 tdll;
+	u8 trp_ab;
+	u16 tref;
+	u8 trfc;
+	u8 tpdex;
+	u8 txpdll;
+	u8 txsnr;
+	u16 txsr;
+	u8 cksrx;
+	u8 cksre;
+	u16 zqcl;
+	u16 zqinit;
+	u8 zqcs;
+	u8 ref_per_zq;
+	u8 aprebit;
+	u8 wlmrd;
+	u8 wldqsen;
+};
+
+void ddrmc_setup_iomux(void);
+void ddrmc_phy_init(void);
+void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
+						  struct ddrmc_lvl_info *lvl,
+						  int col_diff, int row_diff);
+
+#endif
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 6b10bdf..a7d765a 100644
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -52,6 +52,7 @@
 #define SAI2_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00031000)
 #define SAI3_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00032000)
 #define CRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00033000)
+#define USBC0_BASE_ADDR     (AIPS0_BASE_ADDR + 0x00034000)
 #define PDB_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00036000)
 #define PIT_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00037000)
 #define FTM0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00038000)
@@ -65,7 +66,9 @@
 #define QSPI0_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00044000)
 #define IOMUXC_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00048000)
 #define ANADIG_BASE_ADDR	(AIPS0_BASE_ADDR + 0x00050000)
-#define SCSCM_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
+#define USB_PHY0_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050800)
+#define USB_PHY1_BASE_ADDR  (AIPS0_BASE_ADDR + 0x00050C00)
+#define SCSC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00052000)
 #define ASRC_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00060000)
 #define SPDIF_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00061000)
 #define ESAI_BASE_ADDR		(AIPS0_BASE_ADDR + 0x00062000)
@@ -84,6 +87,7 @@
 #define DDR_BASE_ADDR		(AIPS1_BASE_ADDR + 0x0002E000)
 #define ESDHC0_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00031000)
 #define ESDHC1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00032000)
+#define USBC1_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00034000)
 #define ENET_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00050000)
 #define ENET1_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00051000)
 #define NFC_BASE_ADDR		(AIPS1_BASE_ADDR + 0x00060000)
@@ -196,8 +200,8 @@
 #define DDRMC_CR96_WLMRD(v)				(((v) & 0x3f) << 8)
 #define DDRMC_CR96_WLDQSEN(v)				((v) & 0x3f)
 #define DDRMC_CR97_WRLVL_EN				(1 << 24)
-#define DDRMC_CR98_WRLVL_DL_0				(0)
-#define DDRMC_CR99_WRLVL_DL_1				(0)
+#define DDRMC_CR98_WRLVL_DL_0(v)			((v) & 0xffff)
+#define DDRMC_CR99_WRLVL_DL_1(v)			((v) & 0xffff)
 #define DDRMC_CR102_RDLVL_GT_REGEN			(1 << 16)
 #define DDRMC_CR102_RDLVL_REG_EN			(1 << 8)
 #define DDRMC_CR105_RDLVL_DL_0(v)			(((v) & 0xff) << 8)
@@ -263,6 +267,14 @@
 #define SRC_SRSR_WDOG_M4				(0x1 << 4)
 #define SRC_SRSR_WDOG_A5				(0x1 << 3)
 #define SRC_SRSR_POR_RST				(0x1 << 0)
+#define SRC_SBMR2_BMOD_MASK             (0x3 << 24)
+#define SRC_SBMR2_BMOD_SHIFT            24
+#define SRC_SBMR2_BMOD_FUSES            0x0
+#define SRC_SBMR2_BMOD_SERIAL           0x1
+#define SRC_SBMR2_BMOD_RCON             0x2
+
+/* Slow Clock Source Controller Module (SCSC) */
+#define SCSC_SOSC_CTR_SOSC_EN            0x1
 
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
@@ -448,6 +460,24 @@ struct mscm_ir {
 	u16 rsvd3[848];
 };
 
+/* SCSC */
+struct scsc_reg {
+	u32 sirc_ctr;
+	u32 sosc_ctr;
+};
+
+/* MSCM */
+struct mscm {
+	u32 cpxtype;
+	u32 cpxnum;
+	u32 cpxmaster;
+	u32 cpxcount;
+	u32 cpxcfg0;
+	u32 cpxcfg1;
+	u32 cpxcfg2;
+	u32 cpxcfg3;
+};
+
 #endif	/* __ASSEMBLER__*/
 
 #endif	/* __ASM_ARCH_IMX_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-zynq/gpio.h b/arch/arm/include/asm/arch-zynq/gpio.h
deleted file mode 100644
index a26ae87..0000000
--- a/arch/arm/include/asm/arch-zynq/gpio.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2013 Xilinx, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ZYNQ_GPIO_H
-#define _ZYNQ_GPIO_H
-
-#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/include/asm/arch-zynqmp/gpio.h b/arch/arm/include/asm/arch-zynqmp/gpio.h
new file mode 100644
index 0000000..098bbde
--- /dev/null
+++ b/arch/arm/include/asm/arch-zynqmp/gpio.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2015 Xilinx, Inc.
+ *
+ * SPDX-License-Identifier:      GPL-2.0+
+ */
+
+#ifndef __ARCH_ZYNQMP_GPIO_H
+#define __ARCH_ZYNQMP_GPIO_H
+
+/* Empty file - sdhci requires this. */
+
+#endif
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index 97fb49a..c9dc49d 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -11,6 +11,12 @@
 #define ZYNQ_SERIAL_BASEADDR0	0xFF000000
 #define ZYNQ_SERIAL_BASEADDR1	0xFF001000
 
+#define ZYNQ_SPI_BASEADDR0	0xFF040000
+#define ZYNQ_SPI_BASEADDR1	0xFF050000
+
+#define ZYNQ_I2C_BASEADDR0	0xFF020000
+#define ZYNQ_I2C_BASEADDR1	0xFF030000
+
 #define ZYNQ_SDHCI_BASEADDR0	0xFF160000
 #define ZYNQ_SDHCI_BASEADDR1	0xFF170000
 
@@ -18,11 +24,15 @@
 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT	0x1000000
 
 struct crlapb_regs {
-	u32 reserved0[74];
+	u32 reserved0[36];
+	u32 cpu_r5_ctrl; /* 0x90 */
+	u32 reserved1[37];
 	u32 timestamp_ref_ctrl; /* 0x128 */
-	u32 reserved0_1[53];
+	u32 reserved2[53];
 	u32 boot_mode; /* 0x200 */
-	u32 reserved1[26];
+	u32 reserved3[14];
+	u32 rst_lpd_top; /* 0x23C */
+	u32 reserved4[26];
 };
 
 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
@@ -41,12 +51,47 @@ struct iou_scntr {
 
 /* Bootmode setting values */
 #define BOOT_MODES_MASK	0x0000000F
-#define SD_MODE		0x00000005
+#define SD_MODE		0x00000003
+#define EMMC_MODE	0x00000006
 #define JTAG_MODE	0x00000000
 
+#define ZYNQMP_RPU_BASEADDR	0xFF9A0000
+
+struct rpu_regs {
+	u32 rpu_glbl_ctrl;
+	u32 reserved0[63];
+	u32 rpu0_cfg; /* 0x100 */
+	u32 reserved1[63];
+	u32 rpu1_cfg; /* 0x200 */
+};
+
+#define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR)
+
+#define ZYNQMP_CRF_APB_BASEADDR	0xFD1A0000
+
+struct crfapb_regs {
+	u32 reserved0[65];
+	u32 rst_fpd_apu; /* 0x104 */
+	u32 reserved1;
+};
+
+#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
+
+#define ZYNQMP_APU_BASEADDR	0xFD5C0000
+
+struct apu_regs {
+	u32 reserved0[16];
+	u32 rvbar_addr0_l; /* 0x40 */
+	u32 rvbar_addr0_h; /* 0x44 */
+	u32 reserved1[20];
+};
+
+#define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR)
+
 /* Board version value */
 #define ZYNQMP_CSU_VERSION_SILICON	0x0
 #define ZYNQMP_CSU_VERSION_EP108	0x1
+#define ZYNQMP_CSU_VERSION_VELOCE	0x2
 #define ZYNQMP_CSU_VERSION_QEMU		0x3
 
 #endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h
new file mode 100644
index 0000000..d2aa1c4
--- /dev/null
+++ b/arch/arm/include/asm/armv7m.h
@@ -0,0 +1,60 @@
+/*
+ * (C) Copyright 2010,2011
+ * Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
+ *
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef ARMV7M_H
+#define ARMV7M_H
+
+#if defined(__ASSEMBLY__)
+.syntax unified
+.thumb
+#endif
+
+#define V7M_SCB_BASE		0xE000ED00
+#define V7M_MPU_BASE		0xE000ED90
+
+#define V7M_SCB_VTOR		0x08
+
+#if !defined(__ASSEMBLY__)
+struct v7m_scb {
+	uint32_t cpuid;		/* CPUID Base Register */
+	uint32_t icsr;		/* Interrupt Control and State Register */
+	uint32_t vtor;		/* Vector Table Offset Register */
+	uint32_t aircr;		/* App Interrupt and Reset Control Register */
+};
+#define V7M_SCB				((struct v7m_scb *)V7M_SCB_BASE)
+
+#define V7M_AIRCR_VECTKEY		0x5fa
+#define V7M_AIRCR_VECTKEY_SHIFT		16
+#define V7M_AIRCR_ENDIAN		(1 << 15)
+#define V7M_AIRCR_PRIGROUP_SHIFT	8
+#define V7M_AIRCR_PRIGROUP_MSK		(0x7 << V7M_AIRCR_PRIGROUP_SHIFT)
+#define V7M_AIRCR_SYSRESET		(1 << 2)
+
+#define V7M_ICSR_VECTACT_MSK		0xFF
+
+struct v7m_mpu {
+	uint32_t type;		/* Type Register */
+	uint32_t ctrl;		/* Control Register */
+	uint32_t rnr;		/* Region Number Register */
+	uint32_t rbar;		/* Region Base Address Register */
+	uint32_t rasr;		/* Region Attribute and Size Register */
+};
+#define V7M_MPU				((struct v7m_mpu *)V7M_MPU_BASE)
+
+#define V7M_MPU_CTRL_ENABLE		(1 << 0)
+#define V7M_MPU_CTRL_HFNMIENA		(1 << 1)
+
+#define V7M_MPU_RASR_EN			(1 << 0)
+#define V7M_MPU_RASR_SIZE_BITS		1
+#define V7M_MPU_RASR_SIZE_4GB		(31 << V7M_MPU_RASR_SIZE_BITS)
+#define V7M_MPU_RASR_AP_RW_RW		(3 << 24)
+
+#endif /* !defined(__ASSEMBLY__) */
+#endif /* ARMV7M_H */
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
new file mode 100644
index 0000000..f097c81
--- /dev/null
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __FSL_SECURE_BOOT_H
+#define __FSL_SECURE_BOOT_H
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_FIT_SIGNATURE
+
+#define CONFIG_EXTRA_ENV \
+	"setenv fdt_high 0xcfffffff;"	\
+	"setenv initrd_high 0xcfffffff;"	\
+	"setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
+
+/* The address needs to be modified according to NOR memory map */
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0x600a0000
+
+#include <config_fsl_secboot.h>
+#endif
+#endif
+
+#endif
diff --git a/arch/arm/include/asm/imx-common/regs-usbphy.h b/arch/arm/include/asm/imx-common/regs-usbphy.h
new file mode 100644
index 0000000..220e45f
--- /dev/null
+++ b/arch/arm/include/asm/imx-common/regs-usbphy.h
@@ -0,0 +1,26 @@
+/*
+ * Freescale USB PHY Register Definitions
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ */
+
+#ifndef __REGS_USBPHY_H__
+#define __REGS_USBPHY_H__
+
+#define USBPHY_CTRL						0x00000030
+#define USBPHY_CTRL_SET					0x00000034
+#define USBPHY_CTRL_CLR					0x00000038
+#define USBPHY_CTRL_TOG					0x0000003C
+#define USBPHY_PWD						0x00000000
+#define USBPHY_TX						0x00000010
+#define USBPHY_RX						0x00000020
+#define USBPHY_DEBUG					0x00000050
+
+#define USBPHY_CTRL_ENUTMILEVEL2		(1 << 14)
+#define USBPHY_CTRL_ENUTMILEVEL3		(1 << 15)
+#define USBPHY_CTRL_OTG_ID				(1 << 27)
+#define USBPHY_CTRL_CLKGATE				(1 << 30)
+#define USBPHY_CTRL_SFTRST				(1 << 31)
+
+#endif /* __REGS_USBPHY_H__ */
diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h
index 1a907d4..cad5f86 100644
--- a/arch/arm/include/asm/imx-common/video.h
+++ b/arch/arm/include/asm/imx-common/video.h
@@ -26,4 +26,5 @@ extern struct display_info_t const displays[];
 extern size_t display_count;
 #endif
 
+int ipu_set_ldb_clock(int rate);
 #endif
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index c424a22..5afe791 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -1108,6 +1108,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_KZM9G                4140
 #define MACH_TYPE_COLIBRI_T30          4493
 #define MACH_TYPE_APALIS_T30           4513
+#define MACH_TYPE_OMAPL138_LCDK        2495
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index c8c3e71..b0296fb 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -362,6 +362,10 @@ struct omap_sys_ctrl_regs {
 	u32 control_core_control_io1;
 	u32 control_core_control_io2;
 	u32 control_id_code;
+	u32 control_std_fuse_die_id_0;
+	u32 control_std_fuse_die_id_1;
+	u32 control_std_fuse_die_id_2;
+	u32 control_std_fuse_die_id_3;
 	u32 control_std_fuse_opp_bgap;
 	u32 control_ldosram_iva_voltage_ctrl;
 	u32 control_ldosram_mpu_voltage_ctrl;
@@ -578,6 +582,7 @@ void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
 s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
 
 void usb_fake_mac_from_die_id(u32 *id);
+void usb_set_serial_num_from_die_id(u32 *id);
 
 void omap_smc1(u32 service, u32 val);
 
diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h
deleted file mode 100644
index fb08578..0000000
--- a/arch/arm/include/asm/pcie_layerscape.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __PCIE_LAYERSCAPE_H_
-#define __PCIE_LAYERSCAPE_H_
-
-void pci_init_board(void);
-void ft_pcie_setup(void *blob, bd_t *bd);
-
-#endif
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index da8ed72..0e1ad0e 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -8,7 +8,9 @@
 lib-$(CONFIG_USE_PRIVATE_LIBGCC) += _ashldi3.o _ashrdi3.o _divsi3.o \
 			_lshrdi3.o _modsi3.o _udivsi3.o _umodsi3.o div0.o
 
-ifdef CONFIG_ARM64
+ifdef CONFIG_CPU_V7M
+obj-y	+= vectors_m.o crt0.o
+else ifdef CONFIG_ARM64
 obj-y	+= crt0_64.o
 else
 obj-y	+= vectors.o crt0.o
@@ -36,7 +38,9 @@ obj-$(CONFIG_SEMIHOSTING) += semihosting.o
 
 obj-y	+= sections.o
 obj-y	+= stack.o
-ifdef CONFIG_ARM64
+ifdef CONFIG_CPU_V7M
+obj-y	+= interrupts_m.o
+else ifdef CONFIG_ARM64
 obj-y	+= gic_64.o
 obj-y	+= interrupts_64.o
 else
diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c
index f606255..37ea6e9 100644
--- a/arch/arm/lib/board.c
+++ b/arch/arm/lib/board.c
@@ -644,7 +644,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #endif
 #if defined(CONFIG_CMD_NET)
 	puts("Net:   ");
-	eth_initialize(gd->bd);
+	eth_initialize();
 #if defined(CONFIG_RESET_PHY_R)
 	debug("Reset Ethernet PHY\n");
 	reset_phy();
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 2d6b676..b1bff8c 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -18,6 +18,7 @@
 #include <u-boot/zlib.h>
 #include <asm/byteorder.h>
 #include <libfdt.h>
+#include <mapmem.h>
 #include <fdt_support.h>
 #include <asm/bootm.h>
 #include <asm/secure.h>
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index 92d3732..afd4f10 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -9,6 +9,9 @@
 #include <config.h>
 #include <asm-offsets.h>
 #include <linux/linkage.h>
+#ifdef CONFIG_CPU_V7M
+#include <asm/armv7m.h>
+#endif
 
 /*
  * This file handles the target-independent stages of the U-Boot
@@ -66,15 +69,30 @@ ENTRY(_main)
 #else
 	ldr	sp, =(CONFIG_SYS_INIT_SP_ADDR)
 #endif
+#if defined(CONFIG_CPU_V7M)	/* v7M forbids using SP as BIC destination */
+	mov	r3, sp
+	bic	r3, r3, #7
+	mov	sp, r3
+#else
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+#endif
 	mov	r2, sp
 	sub	sp, sp, #GD_SIZE	/* allocate one GD above SP */
+#if defined(CONFIG_CPU_V7M)	/* v7M forbids using SP as BIC destination */
+	mov	r3, sp
+	bic	r3, r3, #7
+	mov	sp, r3
+#else
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+#endif
 	mov	r9, sp		/* GD is above SP */
 	mov	r1, sp
 	mov	r0, #0
 clr_gd:
 	cmp	r1, r2			/* while not at end of GD */
+#if defined(CONFIG_CPU_V7M)
+	itt	lo
+#endif
 	strlo	r0, [r1]		/* clear 32-bit GD word */
 	addlo	r1, r1, #4		/* move to next */
 	blo	clr_gd
@@ -94,13 +112,22 @@ clr_gd:
  */
 
 	ldr	sp, [r9, #GD_START_ADDR_SP]	/* sp = gd->start_addr_sp */
+#if defined(CONFIG_CPU_V7M)	/* v7M forbids using SP as BIC destination */
+	mov	r3, sp
+	bic	r3, r3, #7
+	mov	sp, r3
+#else
 	bic	sp, sp, #7	/* 8-byte alignment for ABI compliance */
+#endif
 	ldr	r9, [r9, #GD_BD]		/* r9 = gd->bd */
 	sub	r9, r9, #GD_SIZE		/* new GD is below bd */
 
 	adr	lr, here
 	ldr	r0, [r9, #GD_RELOC_OFF]		/* r0 = gd->reloc_off */
 	add	lr, lr, r0
+#if defined(CONFIG_CPU_V7M)
+	orr	lr, #1				/* As required by Thumb-only */
+#endif
 	ldr	r0, [r9, #GD_RELOCADDR]		/* r0 = gd->relocaddr */
 	b	relocate_code
 here:
@@ -134,6 +161,9 @@ here:
 	mov	r2, #0x00000000		/* prepare zero to clear BSS */
 
 clbss_l:cmp	r0, r1			/* while not at end of BSS */
+#if defined(CONFIG_CPU_V7M)
+	itt	lo
+#endif
 	strlo	r2, [r0]		/* clear 32-bit BSS word */
 	addlo	r0, r0, #4		/* move to next */
 	blo	clbss_l
diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S
index 1654011..bc9c53c 100644
--- a/arch/arm/lib/crt0_64.S
+++ b/arch/arm/lib/crt0_64.S
@@ -61,7 +61,11 @@ ENTRY(_main)
 /*
  * Set up initial C runtime environment and call board_init_f(0).
  */
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
+	ldr	x0, =(CONFIG_SPL_STACK)
+#else
 	ldr	x0, =(CONFIG_SYS_INIT_SP_ADDR)
+#endif
 	sub	x18, x0, #GD_SIZE	/* allocate one GD above SP */
 	bic	x18, x18, #0x7		/* 8-byte alignment for GD */
 zero_gd:
@@ -77,6 +81,7 @@ zero_gd:
 	mov	x0, #0
 	bl	board_init_f
 
+#if !defined(CONFIG_SPL_BUILD)
 /*
  * Set up intermediate environment (new sp and gd) and call
  * relocate_code(addr_moni). Trick here is that we'll return
@@ -119,4 +124,6 @@ clear_loop:
 
 	/* NOTREACHED - board_init_r() does not return */
 
+#endif /* !CONFIG_SPL_BUILD */
+
 ENDPROC(_main)
diff --git a/arch/arm/lib/interrupts_m.c b/arch/arm/lib/interrupts_m.c
new file mode 100644
index 0000000..89ce493
--- /dev/null
+++ b/arch/arm/lib/interrupts_m.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+/*
+ * Upon exception entry ARMv7-M processors automatically save stack
+ * frames containing some registers. For simplicity initial
+ * implementation uses only this auto-saved stack frame.
+ * This does not contain complete register set dump,
+ * only R0-R3, R12, LR, PC and xPSR are saved.
+ */
+
+struct autosave_regs {
+	long uregs[8];
+};
+
+#define ARM_XPSR	uregs[7]
+#define ARM_PC		uregs[6]
+#define ARM_LR		uregs[5]
+#define ARM_R12		uregs[4]
+#define ARM_R3		uregs[3]
+#define ARM_R2		uregs[2]
+#define ARM_R1		uregs[1]
+#define ARM_R0		uregs[0]
+
+int interrupt_init(void)
+{
+	return 0;
+}
+
+void enable_interrupts(void)
+{
+	return;
+}
+
+int disable_interrupts(void)
+{
+	return 0;
+}
+
+void dump_regs(struct autosave_regs *regs)
+{
+	printf("pc : %08lx    lr : %08lx    xPSR : %08lx\n",
+	       regs->ARM_PC, regs->ARM_LR, regs->ARM_XPSR);
+	printf("r12 : %08lx   r3 : %08lx    r2 : %08lx\n"
+		"r1 : %08lx    r0 : %08lx\n",
+		regs->ARM_R12, regs->ARM_R3, regs->ARM_R2,
+		regs->ARM_R1, regs->ARM_R0);
+}
+
+void bad_mode(void)
+{
+	panic("Resetting CPU ...\n");
+	reset_cpu(0);
+}
+
+void do_hard_fault(struct autosave_regs *autosave_regs)
+{
+	printf("Hard fault\n");
+	dump_regs(autosave_regs);
+	bad_mode();
+}
+
+void do_mm_fault(struct autosave_regs *autosave_regs)
+{
+	printf("Memory management fault\n");
+	dump_regs(autosave_regs);
+	bad_mode();
+}
+
+void do_bus_fault(struct autosave_regs *autosave_regs)
+{
+	printf("Bus fault\n");
+	dump_regs(autosave_regs);
+	bad_mode();
+}
+
+void do_usage_fault(struct autosave_regs *autosave_regs)
+{
+	printf("Usage fault\n");
+	dump_regs(autosave_regs);
+	bad_mode();
+}
+
+void do_invalid_entry(struct autosave_regs *autosave_regs)
+{
+	printf("Exception\n");
+	dump_regs(autosave_regs);
+	bad_mode();
+}
diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index 92f5314..475d503 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -9,6 +9,9 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <linux/linkage.h>
+#ifdef CONFIG_CPU_V7M
+#include <asm/armv7m.h>
+#endif
 
 /*
  * Default/weak exception vectors relocation routine
@@ -23,6 +26,15 @@
 
 ENTRY(relocate_vectors)
 
+#ifdef CONFIG_CPU_V7M
+	/*
+	 * On ARMv7-M we only have to write the new vector address
+	 * to VTOR register.
+	 */
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	ldr	r1, =V7M_SCB_BASE
+	str	r0, [r1, V7M_SCB_VTOR]
+#else
 #ifdef CONFIG_HAS_VBAR
 	/*
 	 * If the ARM processor has the security extensions,
@@ -47,6 +59,7 @@ ENTRY(relocate_vectors)
 	ldmia	r0!, {r2-r8,r10}
 	stmia	r1!, {r2-r8,r10}
 #endif
+#endif
 	bx	lr
 
 ENDPROC(relocate_vectors)
diff --git a/arch/arm/lib/vectors_m.S b/arch/arm/lib/vectors_m.S
new file mode 100644
index 0000000..abc7f88
--- /dev/null
+++ b/arch/arm/lib/vectors_m.S
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2015
+ * Kamil Lulko, <rev13@wp.pl>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <asm/armv7m.h>
+#include <linux/linkage.h>
+
+.type __hard_fault_entry, %function
+__hard_fault_entry:
+	mov	r0, sp	@ pass auto-saved registers as argument
+	b	do_hard_fault
+
+.type __mm_fault_entry, %function
+__mm_fault_entry:
+	mov	r0, sp	@ pass auto-saved registers as argument
+	b	do_mm_fault
+
+.type __bus_fault_entry, %function
+__bus_fault_entry:
+	mov	r0, sp	@ pass auto-saved registers as argument
+	b	do_bus_fault
+
+.type __usage_fault_entry, %function
+__usage_fault_entry:
+	mov	r0, sp	@ pass auto-saved registers as argument
+	b	do_usage_fault
+
+.type __invalid_entry, %function
+__invalid_entry:
+	mov	r0, sp	@ pass auto-saved registers as argument
+	b	do_invalid_entry
+
+   .section  .vectors
+ENTRY(_start)
+	.long	CONFIG_SYS_INIT_SP_ADDR		@ 0 - Reset stack pointer
+	.long	reset				@ 1 - Reset
+	.long	__invalid_entry			@ 2 - NMI
+	.long	__hard_fault_entry		@ 3 - HardFault
+	.long	__mm_fault_entry		@ 4 - MemManage
+	.long	__bus_fault_entry		@ 5 - BusFault
+	.long	__usage_fault_entry		@ 6 - UsageFault
+	.long	__invalid_entry			@ 7 - Reserved
+	.long	__invalid_entry			@ 8 - Reserved
+	.long	__invalid_entry			@ 9 - Reserved
+	.long	__invalid_entry			@ 10 - Reserved
+	.long	__invalid_entry			@ 11 - SVCall
+	.long	__invalid_entry			@ 12 - Debug Monitor
+	.long	__invalid_entry			@ 13 - Reserved
+	.long	__invalid_entry			@ 14 - PendSV
+	.long	__invalid_entry			@ 15 - SysTick
+	.rept	255 - 16
+	.long	__invalid_entry			@ 16..255 - External Interrupts
+	.endr
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 30c4e17..b660a5b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -30,6 +30,9 @@ config TARGET_TNY_A9260
 config TARGET_SNAPPER9260
 	bool "Support snapper9260"
 	select CPU_ARM926EJS
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
 
 config TARGET_AFEB9260
 	bool "Support afeb9260"
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 0c04c30..c740180 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -14,15 +14,6 @@ config TARGET_RPI_2
 
 endchoice
 
-config DM
-	default y
-
-config DM_SERIAL
-	default y
-
-config DM_GPIO
-	default y
-
 config PHYS_TO_BUS
 	default y
 
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 6827721..3ef55d3 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -21,6 +21,10 @@ config TARGET_CAM_ENC_4XX
 	bool "CAM ENC 4xx board"
 	select SUPPORT_SPL
 
+config TARGET_OMAPL138_LCDK
+	bool "OMAPL138 LCDK"
+	select SUPPORT_SPL
+
 config TARGET_DAVINCI_DM355EVM
 	bool "DM355 EVM board"
 
diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c
index e18bdfc..e699d61 100644
--- a/arch/arm/mach-davinci/misc.c
+++ b/arch/arm/mach-davinci/misc.c
@@ -49,7 +49,7 @@ int dvevm_read_mac_address(uint8_t *buf)
 		goto i2cerr;
 
 	/* Check that MAC address is valid. */
-	if (!is_valid_ether_addr(buf))
+	if (!is_valid_ethaddr(buf))
 		goto err;
 
 	return 1; /* Found */
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
new file mode 100644
index 0000000..8ffc544
--- /dev/null
+++ b/arch/arm/mach-integrator/Kconfig
@@ -0,0 +1,54 @@
+menu "Integrator Options"
+	depends on ARCH_INTEGRATOR
+
+choice
+	prompt "Integrator platform select"
+
+config ARCH_INTEGRATOR_AP
+	bool "Support Integrator/AP platform"
+
+config ARCH_INTEGRATOR_CP
+	bool "Support Integrator/CP platform"
+	select ARCH_CINTEGRATOR
+
+endchoice
+
+config ARCH_CINTEGRATOR
+	bool
+
+choice
+	prompt "Integrator core module select"
+
+config CM720T
+	bool "Core Module for ARM720T"
+	select CPU_ARM720T
+
+config CM920T
+	bool "Core Module for ARM920T"
+	select CPU_ARM920T
+
+config CM926EJ_S
+	bool "Core Module for ARM926EJ-STM"
+	select CPU_ARM926EJS
+
+config CM946ES
+	bool "Core Module for ARM946E-STM"
+	select CPU_ARM946ES
+
+config CM1136
+	bool "Core Module for ARM1136JF-STM"
+	select CPU_ARM1136
+
+endchoice
+
+config SYS_BOARD
+	default "integrator"
+
+config SYS_VENDOR
+	default "armltd"
+
+config SYS_CONFIG_NAME
+	default "integratorap" if ARCH_INTEGRATOR_AP
+	default "integratorcp" if ARCH_INTEGRATOR_CP
+
+endmenu
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index e77ac40..d049395 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -44,7 +44,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
 #define CONFIG_NR_DRAM_BANKS_MAX	2
 
-#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
 #define MV_UART_CONSOLE_BASE	KW_UART0_BASE
 #define MV_SATA_BASE		KW_SATA_BASE
 #define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index fce1c1d..8bab594 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -23,27 +23,9 @@ config SYS_MALLOC_F_LEN
 config USE_PRIVATE_LIBGCC
 	default y
 
-config DM
-	default y
-
 config SPL_DM
 	default y
 
-config DM_SERIAL
-	default y
-
-config DM_SPI
-	default y
-
-config DM_SPI_FLASH
-	default y
-
-config DM_I2C
-	default y
-
-config DM_GPIO
-	default y
-
 source "arch/arm/mach-tegra/tegra20/Kconfig"
 source "arch/arm/mach-tegra/tegra30/Kconfig"
 source "arch/arm/mach-tegra/tegra114/Kconfig"
diff --git a/arch/arm/cpu/armv7/zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 3a52535..1046ece 100644
--- a/arch/arm/cpu/armv7/zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,4 +1,4 @@
-if ZYNQ
+if ARCH_ZYNQ
 
 choice
 	prompt "Xilinx Zynq board select"
@@ -9,6 +9,9 @@ config TARGET_ZYNQ_ZED
 config TARGET_ZYNQ_MICROZED
 	bool "Zynq MicroZed"
 
+config TARGET_ZYNQ_PICOZED
+	bool "Zynq PicoZed"
+
 config TARGET_ZYNQ_ZC70X
 	bool "Zynq ZC702/ZC706 Board"
 
@@ -32,6 +35,7 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "zynq_zed" if TARGET_ZYNQ_ZED
 	default "zynq_microzed" if TARGET_ZYNQ_MICROZED
+	default "zynq_picozed" if TARGET_ZYNQ_PICOZED
 	default "zynq_zc70x" if TARGET_ZYNQ_ZC70X
 	default "zynq_zc770" if TARGET_ZYNQ_ZC770
 	default "zynq_zybo" if TARGET_ZYNQ_ZYBO
diff --git a/arch/arm/cpu/armv7/zynq/Makefile b/arch/arm/mach-zynq/Makefile
index 901f2ce..bf29b4d 100644
--- a/arch/arm/cpu/armv7/zynq/Makefile
+++ b/arch/arm/mach-zynq/Makefile
@@ -14,4 +14,5 @@ obj-y	+= ddrc.o
 obj-y	+= slcr.o
 obj-y	+= clk.o
 obj-y	+= lowlevel_init.o
+AFLAGS_lowlevel_init.o := -mfpu=neon
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
diff --git a/arch/arm/cpu/armv7/zynq/clk.c b/arch/arm/mach-zynq/clk.c
index d2885dc..d2885dc 100644
--- a/arch/arm/cpu/armv7/zynq/clk.c
+++ b/arch/arm/mach-zynq/clk.c
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/mach-zynq/cpu.c
index 914b1fe..914b1fe 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/mach-zynq/cpu.c
diff --git a/arch/arm/cpu/armv7/zynq/ddrc.c b/arch/arm/mach-zynq/ddrc.c
index 5b20acc..5b20acc 100644
--- a/arch/arm/cpu/armv7/zynq/ddrc.c
+++ b/arch/arm/mach-zynq/ddrc.c
diff --git a/arch/arm/include/asm/arch-zynq/clk.h b/arch/arm/mach-zynq/include/mach/clk.h
index 250c5bc..250c5bc 100644
--- a/arch/arm/include/asm/arch-zynq/clk.h
+++ b/arch/arm/mach-zynq/include/mach/clk.h
diff --git a/arch/arm/mach-zynq/include/mach/gpio.h b/arch/arm/mach-zynq/include/mach/gpio.h
new file mode 100644
index 0000000..9e1e7da
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/gpio.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2013 Xilinx, Inc.
+ * Copyright (c) 2015 DAVE Embedded Systems
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ZYNQ_GPIO_H
+#define _ZYNQ_GPIO_H
+
+#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
+
+/* Maximum banks */
+#define ZYNQ_GPIO_MAX_BANK	4
+
+#define ZYNQ_GPIO_BANK0_NGPIO	32
+#define ZYNQ_GPIO_BANK1_NGPIO	22
+#define ZYNQ_GPIO_BANK2_NGPIO	32
+#define ZYNQ_GPIO_BANK3_NGPIO	32
+
+#define ZYNQ_GPIO_NR_GPIOS	(ZYNQ_GPIO_BANK0_NGPIO + \
+				 ZYNQ_GPIO_BANK1_NGPIO + \
+				 ZYNQ_GPIO_BANK2_NGPIO + \
+				 ZYNQ_GPIO_BANK3_NGPIO)
+
+#define ZYNQ_GPIO_BANK0_PIN_MIN	0
+#define ZYNQ_GPIO_BANK0_PIN_MAX	(ZYNQ_GPIO_BANK0_PIN_MIN + \
+					ZYNQ_GPIO_BANK0_NGPIO - 1)
+#define ZYNQ_GPIO_BANK1_PIN_MIN	(ZYNQ_GPIO_BANK0_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK1_PIN_MAX	(ZYNQ_GPIO_BANK1_PIN_MIN + \
+					ZYNQ_GPIO_BANK1_NGPIO - 1)
+#define ZYNQ_GPIO_BANK2_PIN_MIN	(ZYNQ_GPIO_BANK1_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK2_PIN_MAX	(ZYNQ_GPIO_BANK2_PIN_MIN + \
+					ZYNQ_GPIO_BANK2_NGPIO - 1)
+#define ZYNQ_GPIO_BANK3_PIN_MIN	(ZYNQ_GPIO_BANK2_PIN_MAX + 1)
+#define ZYNQ_GPIO_BANK3_PIN_MAX	(ZYNQ_GPIO_BANK3_PIN_MIN + \
+					ZYNQ_GPIO_BANK3_NGPIO - 1)
+
+/* Register offsets for the GPIO device */
+/* LSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK)	(0x000 + (8 * BANK))
+/* MSW Mask & Data -WO */
+#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK)	(0x004 + (8 * BANK))
+/* Data Register-RW */
+#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK)	(0x060 + (4 * BANK))
+/* Direction mode reg-RW */
+#define ZYNQ_GPIO_DIRM_OFFSET(BANK)	(0x204 + (0x40 * BANK))
+/* Output enable reg-RW */
+#define ZYNQ_GPIO_OUTEN_OFFSET(BANK)	(0x208 + (0x40 * BANK))
+/* Interrupt mask reg-RO */
+#define ZYNQ_GPIO_INTMASK_OFFSET(BANK)	(0x20C + (0x40 * BANK))
+/* Interrupt enable reg-WO */
+#define ZYNQ_GPIO_INTEN_OFFSET(BANK)	(0x210 + (0x40 * BANK))
+/* Interrupt disable reg-WO */
+#define ZYNQ_GPIO_INTDIS_OFFSET(BANK)	(0x214 + (0x40 * BANK))
+/* Interrupt status reg-RO */
+#define ZYNQ_GPIO_INTSTS_OFFSET(BANK)	(0x218 + (0x40 * BANK))
+/* Interrupt type reg-RW */
+#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK)	(0x21C + (0x40 * BANK))
+/* Interrupt polarity reg-RW */
+#define ZYNQ_GPIO_INTPOL_OFFSET(BANK)	(0x220 + (0x40 * BANK))
+/* Interrupt on any, reg-RW */
+#define ZYNQ_GPIO_INTANY_OFFSET(BANK)	(0x224 + (0x40 * BANK))
+
+/* Disable all interrupts mask */
+#define ZYNQ_GPIO_IXR_DISABLE_ALL	0xFFFFFFFF
+
+/* Mid pin number of a bank */
+#define ZYNQ_GPIO_MID_PIN_NUM 16
+
+/* GPIO upper 16 bit mask */
+#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
+
+#define BIT(x) (1<<x)
+
+#endif /* _ZYNQ_GPIO_H */
diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
index e2e0b73..e2e0b73 100644
--- a/arch/arm/include/asm/arch-zynq/hardware.h
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 9d50e24..9d50e24 100644
--- a/arch/arm/include/asm/arch-zynq/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
diff --git a/arch/arm/cpu/armv7/zynq/lowlevel_init.S b/arch/arm/mach-zynq/lowlevel_init.S
index 6d714b7..6d714b7 100644
--- a/arch/arm/cpu/armv7/zynq/lowlevel_init.S
+++ b/arch/arm/mach-zynq/lowlevel_init.S
diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 2521589..05f4099 100644
--- a/arch/arm/cpu/armv7/zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -129,11 +129,18 @@ out:
 
 void zynq_slcr_devcfg_disable(void)
 {
+	u32 reg_val;
+
 	zynq_slcr_unlock();
 
 	/* Disable AXI interface by asserting FPGA resets */
 	writel(0xF, &slcr_base->fpga_rst_ctrl);
 
+	/* Disable Level shifters before setting PS-PL */
+	reg_val = readl(&slcr_base->lvl_shftr_en);
+	reg_val &= ~0xF;
+	writel(reg_val, &slcr_base->lvl_shftr_en);
+
 	/* Set Level Shifters DT618760 */
 	writel(0xA, &slcr_base->lvl_shftr_en);
 
diff --git a/arch/arm/cpu/armv7/zynq/spl.c b/arch/arm/mach-zynq/spl.c
index b80c357..13025f0 100644
--- a/arch/arm/cpu/armv7/zynq/spl.c
+++ b/arch/arm/mach-zynq/spl.c
@@ -85,6 +85,6 @@ __weak void ps7_init(void)
 {
 	/*
 	 * This function is overridden by the one in
-	 * board/xilinx/zynq/ps7_init.c, if it exists.
+	 * board/xilinx/zynq/ps7_init_gpl.c, if it exists.
 	 */
 }
diff --git a/arch/arm/cpu/armv7/zynq/timer.c b/arch/arm/mach-zynq/timer.c
index 303dbcf..5ed9642 100644
--- a/arch/arm/cpu/armv7/zynq/timer.c
+++ b/arch/arm/mach-zynq/timer.c
@@ -93,7 +93,9 @@ ulong get_timer_masked(void)
 		gd->arch.tbl += gd->arch.lastinc - now;
 	} else {
 		/* We have an overflow ... */
-		gd->arch.tbl += gd->arch.lastinc + TIMER_LOAD_VAL - now + 1;
+		gd->arch.tbl += gd->arch.lastinc + (TIMER_LOAD_VAL /
+				(gd->arch.timer_rate_hz / CONFIG_SYS_HZ)) -
+				now + 1;
 	}
 	gd->arch.lastinc = now;
 
diff --git a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds b/arch/arm/mach-zynq/u-boot-spl.lds
index 0f2f756..0f2f756 100644
--- a/arch/arm/cpu/armv7/zynq/u-boot-spl.lds
+++ b/arch/arm/mach-zynq/u-boot-spl.lds
diff --git a/arch/arm/cpu/armv7/zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds
index 4dc9bb0..4dc9bb0 100644
--- a/arch/arm/cpu/armv7/zynq/u-boot.lds
+++ b/arch/arm/mach-zynq/u-boot.lds
diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c
index 99aa96e..aacfcbf 100644
--- a/arch/avr32/lib/board.c
+++ b/arch/avr32/lib/board.c
@@ -244,7 +244,7 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
 #endif
 #if defined(CONFIG_CMD_NET)
 	puts("Net:   ");
-	eth_initialize(gd->bd);
+	eth_initialize();
 #endif
 
 #ifdef CONFIG_GENERIC_ATMEL_MCI
diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds
new file mode 100644
index 0000000..d8dc715
--- /dev/null
+++ b/arch/m68k/cpu/u-boot.lds
@@ -0,0 +1,91 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2015
+ * Angelo Dureghello, Sysam Firmware, angelo@sysam.it
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <config.h>
+
+OUTPUT_ARCH(m68k)
+
+#ifndef LDS_BOARD_TEXT
+#define LDS_BOARD_TEXT
+#endif
+
+SECTIONS
+{
+	.text :
+	{
+		CPUDIR/start.o (.text*)
+		LDS_BOARD_TEXT
+
+		*(.text*)
+	}
+	_etext = .;
+	PROVIDE (etext = .);
+	.rodata :
+	{
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	/* Read-write section, merged into data segment: */
+	. = (. + 0x00FF) & 0xFFFFFF00;
+	_erotext = .;
+	PROVIDE (erotext = .);
+
+	.reloc :
+	{
+		__got_start = .;
+		KEEP(*(.got))
+		__got_end = .;
+		_GOT2_TABLE_ = .;
+		KEEP(*(.got2))
+		_FIXUP_TABLE_ = .;
+		KEEP(*(.fixup))
+	}
+	__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+	__fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+	.data :
+	{
+		*(.data*)
+		*(.sdata*)
+	}
+	_edata = .;
+	PROVIDE (edata = .);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = .;
+	__start___ex_table = .;
+	__ex_table : { *(__ex_table) }
+	__stop___ex_table = .;
+
+	. = ALIGN(256);
+	__init_begin = .;
+	.text.init : { *(.text.init) }
+	.data.init : { *(.data.init) }
+	. = ALIGN(256);
+	__init_end = .;
+
+	__bss_start = .;
+	.bss (NOLOAD)       :
+	{
+		_sbss = .;
+		*(.bss*)
+		*(.sbss*)
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+	}
+	__bss_end = . ;
+	PROVIDE (end = .);
+}
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bc4283d..b0a8a43 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -141,15 +141,12 @@ config MIPS_BOOT_ENV_LEGACY
 	  The address of the enviroment is stored in register $a2.
 
 config MIPS_BOOT_FDT
-	bool "Hand over a flattened device tree to Linux kernel (INCOMPLETE)"
+	bool "Hand over a flattened device tree to Linux kernel"
 	default n
 	help
 	  Enable this option if you want U-Boot to hand over a flattened
-	  device tree to the kernel.
-
-	  Note: the final hand over to the kernel is not yet implemented. After
-	        the community agreed on the MIPS boot interface for device trees,
-	        the corresponding code will be added.
+	  device tree to the kernel. According to UHI register $a0 will be set
+	  to -2 and the FDT address is stored in $a1.
 
 endmenu
 
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index d9d8396..e289799 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -317,7 +317,11 @@ static void boot_jump_linux(bootm_headers_t *images)
 	bootstage_report();
 #endif
 
-	kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env, linux_extra);
+	if (images->ft_len)
+		kernel(-2, (ulong)images->ft_addr, 0, 0);
+	else
+		kernel(linux_argc, (ulong)linux_argv, (ulong)linux_env,
+			linux_extra);
 }
 
 int do_bootm_linux(int flag, int argc, char * const argv[],
diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c
index 39c5b6b..d6ebe07 100644
--- a/arch/mips/mach-au1x00/au1x00_eth.c
+++ b/arch/mips/mach-au1x00/au1x00_eth.c
@@ -187,13 +187,14 @@ static int au1x00_recv(struct eth_device* dev){
 
 		if(status&RX_ERROR){
 			printf("Rx error 0x%x\n", status);
-		}
-		else{
+		} else {
 			/* Pass the packet up to the protocol layers. */
-			NetReceive(NetRxPackets[next_rx], length - 4);
+			net_process_received_packet(net_rx_packets[next_rx],
+						    length - 4);
 		}
 
-		fifo_rx[next_rx].addr = (virt_to_phys(NetRxPackets[next_rx]))|RX_DMA_ENABLE;
+		fifo_rx[next_rx].addr =
+			(virt_to_phys(net_rx_packets[next_rx])) | RX_DMA_ENABLE;
 
 		next_rx++;
 		if(next_rx>=NO_OF_FIFOS){
@@ -234,11 +235,12 @@ static int au1x00_init(struct eth_device* dev, bd_t * bd){
 	for(i=0;i<NO_OF_FIFOS;i++){
 		fifo_tx[i].len = 0;
 		fifo_tx[i].addr = virt_to_phys(&txbuf[0]);
-		fifo_rx[i].addr = (virt_to_phys(NetRxPackets[i]))|RX_DMA_ENABLE;
+		fifo_rx[i].addr = (virt_to_phys(net_rx_packets[i])) |
+			RX_DMA_ENABLE;
 	}
 
 	/* Put mac addr in little endian */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
 	*mac_addr_high	=	(ea[5] <<  8) | (ea[4]	    ) ;
 	*mac_addr_low	=	(ea[3] << 24) | (ea[2] << 16) |
 		(ea[1] <<  8) | (ea[0]	    ) ;
diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
index 4c06a48..24a09bc 100644
--- a/arch/nds32/lib/board.c
+++ b/arch/nds32/lib/board.c
@@ -383,7 +383,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #if defined(CONFIG_CMD_NET)
 	puts("Net:   ");
 
-	eth_initialize(gd->bd);
+	eth_initialize();
 #if defined(CONFIG_RESET_PHY_R)
 	debug("Reset Ethernet PHY\n");
 	reset_phy();
diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c
index 2346685..c26cc8f 100644
--- a/arch/openrisc/lib/board.c
+++ b/arch/openrisc/lib/board.c
@@ -128,7 +128,7 @@ void board_init(void)
 
 #if defined(CONFIG_CMD_NET)
 	puts("NET:   ");
-	eth_initialize(bd);
+	eth_initialize();
 #endif
 
 	/* main_loop */
diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c
index f9f15b5..30ea3de 100644
--- a/arch/powerpc/cpu/mpc8260/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c
@@ -183,7 +183,7 @@ static int fec_recv(struct eth_device* dev)
 	}
 	else {
 	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 	}
 
 
@@ -243,7 +243,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     {
       rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
       rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+      rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
     }
     rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 
@@ -299,7 +299,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
      * it unique by setting a few bits in the upper byte of the
      * non-static part of the address.
      */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
     pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
     pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
     pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
@@ -637,7 +637,7 @@ eth_loopback_test (void)
 
 	puts ("FCC Ethernet External loopback test\n");
 
-	eth_getenv_enetaddr("ethaddr", NetOurEther);
+	eth_getenv_enetaddr("ethaddr", net_ethaddr);
 
 	/*
 	 * global initialisations for all FCC channels
@@ -720,8 +720,8 @@ eth_loopback_test (void)
 			bdp->cbd_sc = BD_ENET_TX_READY | BD_ENET_TX_PAD | \
 				BD_ENET_TX_LAST | BD_ENET_TX_TC;
 
-			memset ((void *)bp, patbytes[i], ELBT_BUFSZ);
-			NetSetEther (bp, NetBcastAddr, 0x8000);
+			memset((void *)bp, patbytes[i], ELBT_BUFSZ);
+			net_set_ether(bp, net_bcast_ethaddr, 0x8000);
 		}
 		ecp->txbd[ELBT_NTXBD - 1].cbd_sc |= BD_ENET_TX_WRAP;
 
@@ -799,11 +799,9 @@ eth_loopback_test (void)
 		 * So, far we have only been given one Ethernet address. We use
 		 * the same address for all channels
 		 */
-#define ea NetOurEther
-		fpp->fen_paddrh = (ea[5] << 8) + ea[4];
-		fpp->fen_paddrm = (ea[3] << 8) + ea[2];
-		fpp->fen_paddrl = (ea[1] << 8) + ea[0];
-#undef ea
+		fpp->fen_paddrh = (net_ethaddr[5] << 8) + net_ethaddr[4];
+		fpp->fen_paddrm = (net_ethaddr[3] << 8) + net_ethaddr[2];
+		fpp->fen_paddrl = (net_ethaddr[1] << 8) + net_ethaddr[0];
 
 		fpp->fen_minflr = PKT_MINBUF_SIZE; /* min frame len register */
 		/*
@@ -1016,7 +1014,7 @@ eth_loopback_test (void)
 							&ecp->rxbufs[i][0];
 
 						ours = memcmp (ehp->et_src, \
-							NetOurEther, 6);
+							net_ethaddr, 6);
 
 						prot = swap16 (ehp->et_protlen);
 						tb = prot & 0x8000;
diff --git a/arch/powerpc/cpu/mpc8260/ether_scc.c b/arch/powerpc/cpu/mpc8260/ether_scc.c
index c988def..5ba8bed 100644
--- a/arch/powerpc/cpu/mpc8260/ether_scc.c
+++ b/arch/powerpc/cpu/mpc8260/ether_scc.c
@@ -146,7 +146,7 @@ static int sec_rx(struct eth_device *dev)
 	else
 	{
 	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 	}
 
 
@@ -263,7 +263,7 @@ static int sec_init(struct eth_device *dev, bd_t *bis)
     {
 	rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 	rtx->rxbd[i].cbd_datlen = 0;                  /* Reset */
-	rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+	rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
     }
 
     rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 4d6cb09..88a3bd6 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -49,6 +49,7 @@ config TARGET_MPC837XERDB
 
 config TARGET_IDS8313
 	bool "Support ids8313"
+	select DM
 
 config TARGET_KM8360
 	bool "Support km8360"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 5ca9bf5..235a635 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_A003399_NOR_WORKAROUND
 void setup_ifc(void)
 {
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 _mas0, _mas1, _mas2, _mas3, _mas7;
 	phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
 
@@ -70,9 +70,9 @@ void setup_ifc(void)
 #endif
 
 	/* Change flash's physical address */
-	ifc_out32(&(ifc_regs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
-	ifc_out32(&(ifc_regs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
-	ifc_out32(&(ifc_regs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
+	ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
+	ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
+	ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
 
 	return ;
 }
diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
index 166dc9e..14358ae 100644
--- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c
+++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c
@@ -186,7 +186,7 @@ static int fec_recv(struct eth_device* dev)
 	}
 	else {
 	    /* Pass the packet up to the protocol layers. */
-	    NetReceive(NetRxPackets[rxIdx], length - 4);
+	    net_process_received_packet(net_rx_packets[rxIdx], length - 4);
 	}
 
 
@@ -263,7 +263,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
     {
       rtx.rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
       rtx.rxbd[i].cbd_datlen = 0;
-      rtx.rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+      rtx.rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
     }
     rtx.rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 
@@ -338,7 +338,7 @@ static int fec_init(struct eth_device* dev, bd_t *bis)
      * it unique by setting a few bits in the upper byte of the
      * non-static part of the address.
      */
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
     pram_ptr->fen_paddrh = (ea[5] << 8) + ea[4];
     pram_ptr->fen_paddrm = (ea[3] << 8) + ea[2];
     pram_ptr->fen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index e24b857..321ade2 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -28,7 +28,7 @@ void get_sys_info(sys_info_t *sys_info)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_FSL_IFC
-	struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
+	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
 #ifdef CONFIG_FSL_CORENET
@@ -597,7 +597,7 @@ void get_sys_info(sys_info_t *sys_info)
 #endif
 
 #if defined(CONFIG_FSL_IFC)
-	ccr = ifc_in32(&ifc_regs->ifc_ccr);
+	ccr = ifc_in32(&ifc_regs.gregs->ifc_ccr);
 	ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
 
 	sys_info->freq_localbus = sys_info->freq_systembus / ccr;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index d8c9fb6..28f04ee 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -252,39 +252,36 @@ l2_disabled:
 	lis	r1,CONFIG_SYS_MONITOR_BASE@h
 	mtspr	IVPR,r1
 
-	lis	r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@h
-	ori	r3,r3,(CONFIG_SYS_MONITOR_BASE & 0xffff)@l
-
-	addi	r4,r3,CriticalInput - _start + _START_OFFSET
+	li	r4,CriticalInput@l
 	mtspr	IVOR0,r4	/* 0: Critical input */
-	addi	r4,r3,MachineCheck - _start + _START_OFFSET
+	li	r4,MachineCheck@l
 	mtspr	IVOR1,r4	/* 1: Machine check */
-	addi	r4,r3,DataStorage - _start + _START_OFFSET
+	li	r4,DataStorage@l
 	mtspr	IVOR2,r4	/* 2: Data storage */
-	addi	r4,r3,InstStorage - _start + _START_OFFSET
+	li	r4,InstStorage@l
 	mtspr	IVOR3,r4	/* 3: Instruction storage */
-	addi	r4,r3,ExtInterrupt - _start + _START_OFFSET
+	li	r4,ExtInterrupt@l
 	mtspr	IVOR4,r4	/* 4: External interrupt */
-	addi	r4,r3,Alignment - _start + _START_OFFSET
+	li	r4,Alignment@l
 	mtspr	IVOR5,r4	/* 5: Alignment */
-	addi	r4,r3,ProgramCheck - _start + _START_OFFSET
+	li	r4,ProgramCheck@l
 	mtspr	IVOR6,r4	/* 6: Program check */
-	addi	r4,r3,FPUnavailable - _start + _START_OFFSET
+	li	r4,FPUnavailable@l
 	mtspr	IVOR7,r4	/* 7: floating point unavailable */
-	addi	r4,r3,SystemCall - _start + _START_OFFSET
+	li	r4,SystemCall@l
 	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	addi	r4,r3,Decrementer - _start + _START_OFFSET
+	li	r4,Decrementer@l
 	mtspr	IVOR10,r4	/* 10: Decrementer */
-	addi	r4,r3,IntervalTimer - _start + _START_OFFSET
+	li	r4,IntervalTimer@l
 	mtspr	IVOR11,r4	/* 11: Interval timer */
-	addi	r4,r3,WatchdogTimer - _start + _START_OFFSET
+	li	r4,WatchdogTimer@l
 	mtspr	IVOR12,r4	/* 12: Watchdog timer */
-	addi	r4,r3,DataTLBError - _start + _START_OFFSET
+	li	r4,DataTLBError@l
 	mtspr	IVOR13,r4	/* 13: Data TLB error */
-	addi	r4,r3,InstructionTLBError - _start + _START_OFFSET
+	li	r4,InstructionTLBError@l
 	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
-	addi	r4,r3,DebugBreakpoint - _start + _START_OFFSET
+	li	r4,DebugBreakpoint@l
 	mtspr	IVOR15,r4	/* 15: Debug */
 #endif
 
@@ -1121,7 +1118,7 @@ switch_as:
 	/*--------------------------------------------------------------*/
 	lis	r3,CONFIG_SYS_MONITOR_BASE@h
 	ori	r3,r3,CONFIG_SYS_MONITOR_BASE@l
-	addi	r3,r3,_start_cont - _start + _START_OFFSET
+	addi	r3,r3,_start_cont - _start
 	mtlr	r3
 	blr
 #endif
@@ -1165,7 +1162,6 @@ _start_cont:
 	/* NOTREACHED - board_init_f() does not return */
 
 #ifndef MINIMAL_SPL
-	. = EXC_OFF_SYS_RESET
 	.globl	_start_of_vectors
 _start_of_vectors:
 
@@ -1185,7 +1181,6 @@ _start_of_vectors:
 	STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
 
 /* Alignment exception. */
-	. = 0x0600
 Alignment:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	mfspr	r4,DAR
@@ -1193,87 +1188,20 @@ Alignment:
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
+	EXC_XFER_TEMPLATE(0x600, Alignment, AlignmentException,
+		MSR_KERNEL, COPY_EE)
 
 /* Program check exception */
-	. = 0x0700
 ProgramCheck:
 	EXCEPTION_PROLOG(SRR0, SRR1)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
-	EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
+	EXC_XFER_TEMPLATE(0x700, ProgramCheck, ProgramCheckException,
 		MSR_KERNEL, COPY_EE)
 
 	/* No FPU on MPC85xx.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
-
-	. = 0x0900
-/*
- * r0 - SYSCALL number
- * r3-... arguments
- */
-SystemCall:
-	addis	r11,r0,0	/* get functions table addr */
-	ori	r11,r11,0	/* Note: this code is patched in trap_init */
-	addis	r12,r0,0	/* get number of functions */
-	ori	r12,r12,0
-
-	cmplw	0,r0,r12
-	bge	1f
-
-	rlwinm	r0,r0,2,0,31	/* fn_addr = fn_tbl[r0] */
-	add	r11,r11,r0
-	lwz	r11,0(r11)
-
-	li	r20,0xd00-4	/* Get stack pointer */
-	lwz	r12,0(r20)
-	subi	r12,r12,12	/* Adjust stack pointer */
-	li	r0,0xc00+_end_back-SystemCall
-	cmplw	0,r0,r12	/* Check stack overflow */
-	bgt	1f
-	stw	r12,0(r20)
-
-	mflr	r0
-	stw	r0,0(r12)
-	mfspr	r0,SRR0
-	stw	r0,4(r12)
-	mfspr	r0,SRR1
-	stw	r0,8(r12)
-
-	li	r12,0xc00+_back-SystemCall
-	mtlr	r12
-	mtspr	SRR0,r11
-
-1:	SYNC
-	rfi
-_back:
-
-	mfmsr	r11			/* Disable interrupts */
-	li	r12,0
-	ori	r12,r12,MSR_EE
-	andc	r11,r11,r12
-	SYNC				/* Some chip revs need this... */
-	mtmsr	r11
-	SYNC
-
-	li	r12,0xd00-4		/* restore regs */
-	lwz	r12,0(r12)
-
-	lwz	r11,0(r12)
-	mtlr	r11
-	lwz	r11,4(r12)
-	mtspr	SRR0,r11
-	lwz	r11,8(r12)
-	mtspr	SRR1,r11
-
-	addi	r12,r12,12		/* Adjust stack pointer */
-	li	r20,0xd00-4
-	stw	r12,0(r20)
-
-	SYNC
-	rfi
-_end_back:
-
+	STD_EXCEPTION(0x0900, SystemCall, UnknownException)
 	STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
 	STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
@@ -1293,32 +1221,22 @@ _end_of_vectors:
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
+ * r23 is the address of the handler.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
-	stw	r22,_NIP(r21)
-	lis	r22,MSR_POW@h
-	andc	r23,r23,r22
-	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 
-	mflr	r23
-	andi.	r24,r23,0x3f00		/* get vector offset */
-	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
 
-	lwz	r24,0(r23)		/* virtual address of handler */
-	lwz	r23,4(r23)		/* where to go when done */
-	mtspr	SRR0,r24
-	mtspr	SRR1,r20
-	mtlr	r23
-	SYNC
-	rfi				/* jump to handler, enable MMU */
+	mtctr	r23			/* virtual address of handler */
+	mtmsr	r20
+	bctrl
 
 int_return:
 	mfmsr	r28		/* Disable interrupts */
@@ -1350,66 +1268,6 @@ int_return:
 	SYNC
 	rfi
 
-crit_return:
-	mfmsr	r28		/* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			/* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	/* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SPRN_CSRR0,r2
-	mtspr	SPRN_CSRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfci
-
-mck_return:
-	mfmsr	r28		/* Disable interrupts */
-	li	r4,0
-	ori	r4,r4,MSR_EE
-	andc	r28,r28,r4
-	SYNC			/* Some chip revs need this... */
-	mtmsr	r28
-	SYNC
-	lwz	r2,_CTR(r1)
-	lwz	r0,_LINK(r1)
-	mtctr	r2
-	mtlr	r0
-	lwz	r2,_XER(r1)
-	lwz	r0,_CCR(r1)
-	mtspr	XER,r2
-	mtcrf	0xFF,r0
-	REST_10GPRS(3, r1)
-	REST_10GPRS(13, r1)
-	REST_8GPRS(23, r1)
-	REST_GPR(31, r1)
-	lwz	r2,_NIP(r1)	/* Restore environment */
-	lwz	r0,_MSR(r1)
-	mtspr	SPRN_MCSRR0,r2
-	mtspr	SPRN_MCSRR1,r0
-	lwz	r0,GPR0(r1)
-	lwz	r2,GPR2(r1)
-	lwz	r1,GPR1(r1)
-	SYNC
-	rfmci
-
 /* Cache functions.
 */
 .globl flush_icache
@@ -1494,11 +1352,6 @@ dcache_status:
 	andi.	r3,r3,L1CSR0_DCE
 	blr
 
-	.globl get_pir
-get_pir:
-	mfspr	r3,PIR
-	blr
-
 	.globl get_pvr
 get_pvr:
 	mfspr	r3,PVR
@@ -1509,11 +1362,6 @@ get_svr:
 	mfspr	r3,SVR
 	blr
 
-	.globl wr_tcr
-wr_tcr:
-	mtspr	TCR,r3
-	blr
-
 /*------------------------------------------------------------------------------- */
 /* Function:	 in8 */
 /* Description:	 Input 8 bits */
@@ -1728,7 +1576,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 
-	addi	r0,r10,in_ram - _start + _START_OFFSET
+	addi	r0,r10,in_ram - _start
 
 	/*
 	 * As IVPR is going to point RAM address,
@@ -1816,89 +1664,41 @@ clear_bss:
 	 */
 	.globl	trap_init
 trap_init:
-	mflr	r4			/* save link register		*/
-	GET_GOT
-	lwz	r7,GOT(_start_of_vectors)
-	lwz	r8,GOT(_end_of_vectors)
-
-	li	r9,0x100		/* reset vector always at 0x100 */
-
-	cmplw	0,r7,r8
-	bgelr				/* return if r7>=r8 - just in case */
-1:
-	lwz	r0,0(r7)
-	stw	r0,0(r9)
-	addi	r7,r7,4
-	addi	r9,r9,4
-	cmplw	0,r7,r8
-	bne	1b
+	/* Update IVORs as per relocation */
+	mtspr	IVPR,r3
 
-	/*
-	 * relocate `hdlr' and `int_return' entries
-	 */
-	li	r7,.L_CriticalInput - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_MachineCheck - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_DataStorage - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_InstStorage - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_ExtInterrupt - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_Alignment - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_ProgramCheck - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_FPUnavailable - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_Decrementer - _start + _START_OFFSET
-	bl	trap_reloc
-	li	r7,.L_IntervalTimer - _start + _START_OFFSET
-	li	r8,_end_of_vectors - _start + _START_OFFSET
-2:
-	bl	trap_reloc
-	addi	r7,r7,0x100		/* next exception vector	*/
-	cmplw	0,r7,r8
-	blt	2b
-
-	/* Update IVORs as per relocated vector table address */
-	li	r7,0x0100
-	mtspr	IVOR0,r7	/* 0: Critical input */
-	li	r7,0x0200
-	mtspr	IVOR1,r7	/* 1: Machine check */
-	li	r7,0x0300
-	mtspr	IVOR2,r7	/* 2: Data storage */
-	li	r7,0x0400
-	mtspr	IVOR3,r7	/* 3: Instruction storage */
-	li	r7,0x0500
-	mtspr	IVOR4,r7	/* 4: External interrupt */
-	li	r7,0x0600
-	mtspr	IVOR5,r7	/* 5: Alignment */
-	li	r7,0x0700
-	mtspr	IVOR6,r7	/* 6: Program check */
-	li	r7,0x0800
-	mtspr	IVOR7,r7	/* 7: floating point unavailable */
-	li	r7,0x0900
-	mtspr	IVOR8,r7	/* 8: System call */
+	li	r4,CriticalInput@l
+	mtspr	IVOR0,r4	/* 0: Critical input */
+	li	r4,MachineCheck@l
+	mtspr	IVOR1,r4	/* 1: Machine check */
+	li	r4,DataStorage@l
+	mtspr	IVOR2,r4	/* 2: Data storage */
+	li	r4,InstStorage@l
+	mtspr	IVOR3,r4	/* 3: Instruction storage */
+	li	r4,ExtInterrupt@l
+	mtspr	IVOR4,r4	/* 4: External interrupt */
+	li	r4,Alignment@l
+	mtspr	IVOR5,r4	/* 5: Alignment */
+	li	r4,ProgramCheck@l
+	mtspr	IVOR6,r4	/* 6: Program check */
+	li	r4,FPUnavailable@l
+	mtspr	IVOR7,r4	/* 7: floating point unavailable */
+	li	r4,SystemCall@l
+	mtspr	IVOR8,r4	/* 8: System call */
 	/* 9: Auxiliary processor unavailable(unsupported) */
-	li	r7,0x0a00
-	mtspr	IVOR10,r7	/* 10: Decrementer */
-	li	r7,0x0b00
-	mtspr	IVOR11,r7	/* 11: Interval timer */
-	li	r7,0x0c00
-	mtspr	IVOR12,r7	/* 12: Watchdog timer */
-	li	r7,0x0d00
-	mtspr	IVOR13,r7	/* 13: Data TLB error */
-	li	r7,0x0e00
-	mtspr	IVOR14,r7	/* 14: Instruction TLB error */
-	li	r7,0x0f00
-	mtspr	IVOR15,r7	/* 15: Debug */
-
-	lis	r7,0x0
-	mtspr	IVPR,r7
-
-	mtlr	r4			/* restore link register	*/
+	li	r4,Decrementer@l
+	mtspr	IVOR10,r4	/* 10: Decrementer */
+	li	r4,IntervalTimer@l
+	mtspr	IVOR11,r4	/* 11: Interval timer */
+	li	r4,WatchdogTimer@l
+	mtspr	IVOR12,r4	/* 12: Watchdog timer */
+	li	r4,DataTLBError@l
+	mtspr	IVOR13,r4	/* 13: Data TLB error */
+	li	r4,InstructionTLBError@l
+	mtspr	IVOR14,r4	/* 14: Instruction TLB error */
+	li	r4,DebugBreakpoint@l
+	mtspr	IVOR15,r4	/* 15: Debug */
+
 	blr
 
 .globl unlock_ram_in_cache
diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c
index 22b8ec7..2e19603 100644
--- a/arch/powerpc/cpu/mpc8xx/fec.c
+++ b/arch/powerpc/cpu/mpc8xx/fec.c
@@ -247,21 +247,21 @@ static int fec_recv (struct eth_device *dev)
 				rtx->rxbd[rxIdx].cbd_sc);
 #endif
 		} else {
-			uchar *rx = NetRxPackets[rxIdx];
+			uchar *rx = net_rx_packets[rxIdx];
 
 			length -= 4;
 
 #if defined(CONFIG_CMD_CDP)
-			if ((rx[0] & 1) != 0
-			    && memcmp ((uchar *) rx, NetBcastAddr, 6) != 0
-			    && !is_cdp_packet((uchar *)rx))
+			if ((rx[0] & 1) != 0 &&
+			    memcmp((uchar *)rx, net_bcast_ethaddr, 6) != 0 &&
+			    !is_cdp_packet((uchar *)rx))
 				rx = NULL;
 #endif
 			/*
 			 * Pass the packet up to the protocol layers.
 			 */
 			if (rx != NULL)
-				NetReceive (rx, length);
+				net_process_received_packet(rx, length);
 		}
 
 		/* Give the buffer back to the FEC. */
@@ -576,7 +576,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd)
 	for (i = 0; i < PKTBUFSRX; i++) {
 		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+		rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 	}
 	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
 
diff --git a/arch/powerpc/cpu/mpc8xx/scc.c b/arch/powerpc/cpu/mpc8xx/scc.c
index 251966b..5498440 100644
--- a/arch/powerpc/cpu/mpc8xx/scc.c
+++ b/arch/powerpc/cpu/mpc8xx/scc.c
@@ -159,7 +159,8 @@ static int scc_recv (struct eth_device *dev)
 #endif
 		} else {
 			/* Pass the packet up to the protocol layers. */
-			NetReceive (NetRxPackets[rxIdx], length - 4);
+			net_process_received_packet(net_rx_packets[rxIdx],
+						    length - 4);
 		}
 
 
@@ -280,7 +281,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	for (i = 0; i < PKTBUFSRX; i++) {
 		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
 		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
-		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
+		rtx->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
 	}
 
 	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
@@ -339,7 +340,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis)
 	pram_ptr->sen_gaddr3 = 0x0;	/* Group Address Filter 3 (unused) */
 	pram_ptr->sen_gaddr4 = 0x0;	/* Group Address Filter 4 (unused) */
 
-#define ea eth_get_dev()->enetaddr
+#define ea eth_get_ethaddr()
 	pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
 	pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
 	pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 9e52d3f..89cb3e9 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -43,6 +43,8 @@ config TARGET_BUBINGA
 
 config TARGET_CANYONLANDS
 	bool "Support canyonlands"
+	select DM
+	select DM_SERIAL
 
 config TARGET_EBONY
 	bool "Support ebony"
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index 61c6d70..4861e3bf 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -45,7 +45,7 @@ static inline bool has_erratum_a007186(void)
 		return IS_SVR_REV(svr, 2, 0);
 	case SVR_T2081:
 	case SVR_T2080:
-		return IS_SVR_REV(svr, 1, 0);
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
 	}
 
 	return false;
diff --git a/arch/powerpc/include/asm/fsl_memac.h b/arch/powerpc/include/asm/fsl_memac.h
deleted file mode 100644
index bed2a40..0000000
--- a/arch/powerpc/include/asm/fsl_memac.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *	Roy Zang <tie-fei.zang@freescale.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __MEMAC_H__
-#define __MEMAC_H__
-
-#include <phy.h>
-
-struct memac {
-	/* memac general control and status registers */
-	u32	res_0[2];
-	u32	command_config;	/* Control and configuration register */
-	u32	mac_addr_0;	/* Lower 32 bits of 48-bit MAC address */
-	u32	mac_addr_1;	/* Upper 16 bits of 48-bit MAC address */
-	u32	maxfrm;		/* Maximum frame length register */
-	u32	res_18[5];
-	u32	hashtable_ctrl;	/* Hash table control register */
-	u32	res_30[4];
-	u32	ievent;		/* Interrupt event register */
-	u32	tx_ipg_length;	/* Transmitter inter-packet-gap register */
-	u32	res_48;
-	u32	imask;		/* interrupt mask register */
-	u32	res_50;
-	u32	cl_pause_quanta[4]; /* CL01-CL67 pause quanta register */
-	u32	cl_pause_thresh[4]; /* CL01-CL67 pause thresh register */
-	u32	rx_pause_status;	/* Receive pause status register */
-	u32	res_78[2];
-	u32	mac_addr[14];	/* MAC address */
-	u32	lpwake_timer;	/* EEE low power wakeup timer register */
-	u32	sleep_timer;	/* Transmit EEE Low Power Timer register */
-	u32	res_c0[8];
-	u32	statn_config;	/* Statistics configuration register */
-	u32	res_e4[7];
-
-	/* memac statistics counter registers */
-	u32	rx_eoct_l;	/* Rx ethernet octests lower */
-	u32	rx_eoct_u;	/* Rx ethernet octests upper */
-	u32	rx_oct_l;	/* Rx octests lower */
-	u32	rx_oct_u;	/* Rx octests upper */
-	u32	rx_align_err_l;	/* Rx alignment error lower */
-	u32	rx_align_err_u;	/* Rx alignment error upper */
-	u32	rx_pause_frame_l; /* Rx valid pause frame upper */
-	u32	rx_pause_frame_u; /* Rx valid pause frame upper */
-	u32	rx_frame_l;	/* Rx frame counter lower */
-	u32	rx_frame_u;	/* Rx frame counter upper */
-	u32	rx_frame_crc_err_l; /* Rx frame check sequence error lower */
-	u32	rx_frame_crc_err_u; /* Rx frame check sequence error upper */
-	u32	rx_vlan_l;	/* Rx VLAN frame lower */
-	u32	rx_vlan_u;	/* Rx VLAN frame upper */
-	u32	rx_err_l;	/* Rx frame error lower */
-	u32	rx_err_u;	/* Rx frame error upper */
-	u32	rx_uni_l;	/* Rx unicast frame lower */
-	u32	rx_uni_u;	/* Rx unicast frame upper */
-	u32	rx_multi_l;	/* Rx multicast frame lower */
-	u32	rx_multi_u;	/* Rx multicast frame upper */
-	u32	rx_brd_l;	/* Rx broadcast frame lower */
-	u32	rx_brd_u;	/* Rx broadcast frame upper */
-	u32	rx_drop_l;	/* Rx dropped packets lower */
-	u32	rx_drop_u;	/* Rx dropped packets upper */
-	u32	rx_pkt_l;	/* Rx packets lower */
-	u32	rx_pkt_u;	/* Rx packets upper */
-	u32	rx_undsz_l;	/* Rx undersized packet lower */
-	u32	rx_undsz_u;	/* Rx undersized packet upper */
-	u32	rx_64_l;	/* Rx 64 oct packet lower */
-	u32	rx_64_u;	/* Rx 64 oct packet upper */
-	u32	rx_127_l;	/* Rx 65 to 127 oct packet lower */
-	u32	rx_127_u;	/* Rx 65 to 127 oct packet upper */
-	u32	rx_255_l;	/* Rx 128 to 255 oct packet lower */
-	u32	rx_255_u;	/* Rx 128 to 255 oct packet upper */
-	u32	rx_511_l;	/* Rx 256 to 511 oct packet lower */
-	u32	rx_511_u;	/* Rx 256 to 511 oct packet upper */
-	u32	rx_1023_l;	/* Rx 512 to 1023 oct packet lower */
-	u32	rx_1023_u;	/* Rx 512 to 1023 oct packet upper */
-	u32	rx_1518_l;	/* Rx 1024 to 1518 oct packet lower */
-	u32	rx_1518_u;	/* Rx 1024 to 1518 oct packet upper */
-	u32	rx_1519_l;	/* Rx 1519 to max oct packet lower */
-	u32	rx_1519_u;	/* Rx 1519 to max oct packet upper */
-	u32	rx_oversz_l;	/* Rx oversized packet lower */
-	u32	rx_oversz_u;	/* Rx oversized packet upper */
-	u32	rx_jabber_l;	/* Rx Jabber packet lower */
-	u32	rx_jabber_u;	/* Rx Jabber packet upper */
-	u32	rx_frag_l;	/* Rx Fragment packet lower */
-	u32	rx_frag_u;	/* Rx Fragment packet upper */
-	u32	rx_cnp_l;	/* Rx control packet lower */
-	u32	rx_cnp_u;	/* Rx control packet upper */
-	u32	rx_drntp_l;	/* Rx dripped not truncated packet lower */
-	u32	rx_drntp_u;	/* Rx dripped not truncated packet upper */
-	u32	res_1d0[0xc];
-
-	u32	tx_eoct_l;	/* Tx ethernet octests lower */
-	u32	tx_eoct_u;	/* Tx ethernet octests upper */
-	u32	tx_oct_l;	/* Tx octests lower */
-	u32	tx_oct_u;	/* Tx octests upper */
-	u32	res_210[0x2];
-	u32	tx_pause_frame_l; /* Tx valid pause frame lower */
-	u32	tx_pause_frame_u; /* Tx valid pause frame upper */
-	u32	tx_frame_l;	/* Tx frame counter lower */
-	u32	tx_frame_u;	/* Tx frame counter upper */
-	u32	tx_frame_crc_err_l; /* Tx frame check sequence error lower */
-	u32	tx_frame_crc_err_u; /* Tx frame check sequence error upper */
-	u32	tx_vlan_l;	/* Tx VLAN frame lower */
-	u32	tx_vlan_u;	/* Tx VLAN frame upper */
-	u32	tx_frame_err_l;	/* Tx frame error lower */
-	u32	tx_frame_err_u;	/* Tx frame error upper */
-	u32	tx_uni_l;	/* Tx unicast frame lower */
-	u32	tx_uni_u;	/* Tx unicast frame upper */
-	u32	tx_multi_l;	/* Tx multicast frame lower */
-	u32	tx_multi_u;	/* Tx multicast frame upper */
-	u32	tx_brd_l;	/* Tx broadcast frame lower */
-	u32	tx_brd_u;	/* Tx broadcast frame upper */
-	u32	res_258[0x2];
-	u32	tx_pkt_l;	/* Tx packets lower */
-	u32	tx_pkt_u;	/* Tx packets upper */
-	u32	tx_undsz_l;	/* Tx undersized packet lower */
-	u32	tx_undsz_u;	/* Tx undersized packet upper */
-	u32	tx_64_l;	/* Tx 64 oct packet lower */
-	u32	tx_64_u;	/* Tx 64 oct packet upper */
-	u32	tx_127_l;	/* Tx 65 to 127 oct packet lower */
-	u32	tx_127_u;	/* Tx 65 to 127 oct packet upper */
-	u32	tx_255_l;	/* Tx 128 to 255 oct packet lower */
-	u32	tx_255_u;	/* Tx 128 to 255 oct packet upper */
-	u32	tx_511_l;	/* Tx 256 to 511 oct packet lower */
-	u32	tx_511_u;	/* Tx 256 to 511 oct packet upper */
-	u32	tx_1023_l;	/* Tx 512 to 1023 oct packet lower */
-	u32	tx_1023_u;	/* Tx 512 to 1023 oct packet upper */
-	u32	tx_1518_l;	/* Tx 1024 to 1518 oct packet lower */
-	u32	tx_1518_u;	/* Tx 1024 to 1518 oct packet upper */
-	u32	tx_1519_l;	/* Tx 1519 to max oct packet lower */
-	u32	tx_1519_u;	/* Tx 1519 to max oct packet upper */
-	u32	res_2a8[0x6];
-	u32	tx_cnp_l;	/* Tx control packet lower */
-	u32	tx_cnp_u;	/* Tx control packet upper */
-	u32	res_2c8[0xe];
-
-	/* Line interface control register */
-	u32 if_mode;		/* interface mode control */
-	u32 if_status;		/* interface status */
-	u32 res_308[0xe];
-
-	/* HiGig/2 Register */
-	u32 hg_config;	/* HiGig2 control and configuration */
-	u32 res_344[0x3];
-	u32 hg_pause_quanta;	/* HiGig2 pause quanta */
-	u32 res_354[0x3];
-	u32 hg_pause_thresh;	/* HiGig2 pause quanta threshold */
-	u32 res_364[0x3];
-	u32 hgrx_pause_status;	/* HiGig2 rx pause quanta status */
-	u32 hg_fifos_status;	/* HiGig2 fifos status */
-	u32 rhm;	/* Rx HiGig2 message counter register */
-	u32 thm;/* Tx HiGig2 message counter register */
-	u32 res_380[0x320];
-};
-
-/* COMMAND_CONFIG - command and configuration register */
-#define MEMAC_CMD_CFG_RX_EN		0x00000002 /* MAC Rx path enable */
-#define MEMAC_CMD_CFG_TX_EN		0x00000001 /* MAC Tx path enable */
-#define MEMAC_CMD_CFG_RXTX_EN	(MEMAC_CMD_CFG_RX_EN | MEMAC_CMD_CFG_TX_EN)
-#define MEMAC_CMD_CFG_NO_LEN_CHK 0x20000 /* Payload length check disable */
-
-/* HASHTABLE_CTRL - Hashtable control register */
-#define HASHTABLE_CTRL_MCAST_EN	0x00000200 /* enable mulitcast Rx hash */
-#define HASHTABLE_CTRL_ADDR_MASK	0x000001ff
-
-/* TX_IPG_LENGTH - Transmit inter-packet gap length register */
-#define TX_IPG_LENGTH_IPG_LEN_MASK	0x000003ff
-
-/* IMASK - interrupt mask register */
-#define IMASK_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event mask */
-#define IMASK_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion mask */
-#define IMASK_REM_FAULT		0x00004000 /* remote fault mask */
-#define IMASK_LOC_FAULT		0x00002000 /* local fault mask */
-#define IMASK_TX_ECC_ER		0x00001000 /* Tx frame ECC error mask */
-#define IMASK_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow mask */
-#define IMASK_TX_ER		0x00000200 /* Tx frame error mask */
-#define IMASK_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow mask */
-#define IMASK_RX_ECC_ER		0x00000080 /* Rx frame ECC error mask */
-#define IMASK_RX_JAB_FRM	0x00000040 /* Rx jabber frame mask */
-#define IMASK_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame mask */
-#define IMASK_RX_RUNT_FRM	0x00000010 /* Rx runt frame mask */
-#define IMASK_RX_FRAG_FRM	0x00000008 /* Rx fragment frame mask */
-#define IMASK_RX_LEN_ER		0x00000004 /* Rx payload length error mask */
-#define IMASK_RX_CRC_ER		0x00000002 /* Rx CRC error mask */
-#define IMASK_RX_ALIGN_ER	0x00000001 /* Rx alignment error mask */
-
-#define IMASK_MASK_ALL		0x00000000
-
-/* IEVENT - interrupt event register */
-#define IEVENT_MDIO_SCAN_EVENT	0x00010000 /* MDIO scan event */
-#define IEVENT_MDIO_CMD_CMPL	0x00008000 /* MDIO cmd completion */
-#define IEVENT_REM_FAULT	0x00004000 /* remote fault */
-#define IEVENT_LOC_FAULT	0x00002000 /* local fault */
-#define IEVENT_TX_ECC_ER	0x00001000 /* Tx frame ECC error */
-#define IEVENT_TX_FIFO_UNFL	0x00000800 /* Tx FIFO underflow */
-#define IEVENT_TX_ER		0x00000200 /* Tx frame error */
-#define IEVENT_RX_FIFO_OVFL	0x00000100 /* Rx FIFO overflow */
-#define IEVENT_RX_ECC_ER	0x00000080 /* Rx frame ECC error */
-#define IEVENT_RX_JAB_FRM	0x00000040 /* Rx jabber frame */
-#define IEVENT_RX_OVRSZ_FRM	0x00000020 /* Rx oversized frame */
-#define IEVENT_RX_RUNT_FRM	0x00000010 /* Rx runt frame */
-#define IEVENT_RX_FRAG_FRM	0x00000008 /* Rx fragment frame */
-#define IEVENT_RX_LEN_ER	0x00000004 /* Rx payload length error */
-#define IEVENT_RX_CRC_ER	0x00000002 /* Rx CRC error */
-#define IEVENT_RX_ALIGN_ER	0x00000001 /* Rx alignment error */
-
-#define IEVENT_CLEAR_ALL	0xffffffff
-
-/* IF_MODE - Interface Mode Register */
-#define IF_MODE_EN_AUTO	0x00008000 /* 1 - Enable automatic speed selection */
-#define IF_MODE_SETSP_100M	0x00000000 /* 00 - 100Mbps RGMII */
-#define IF_MODE_SETSP_10M	0x00002000 /* 01 - 10Mbps RGMII */
-#define IF_MODE_SETSP_1000M	0x00004000 /* 10 - 1000Mbps RGMII */
-#define IF_MODE_SETSP_MASK	0x00006000 /* setsp mask bits */
-#define IF_MODE_XGMII	0x00000000 /* 00- XGMII(10) interface mode */
-#define IF_MODE_GMII		0x00000002 /* 10- GMII interface mode */
-#define IF_MODE_MASK	0x00000003 /* mask for mode interface mode */
-#define IF_MODE_RG		0x00000004 /* 1- RGMII */
-#define IF_MODE_RM		0x00000008 /* 1- RGMII */
-
-#define IF_DEFAULT	(IF_GMII)
-
-/* Internal PHY Registers - SGMII */
-#define PHY_SGMII_CR_PHY_RESET      0x8000
-#define PHY_SGMII_CR_RESET_AN       0x0200
-#define PHY_SGMII_CR_DEF_VAL        0x1140
-#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
-#define PHY_SGMII_IF_MODE_AN        0x0002
-#define PHY_SGMII_IF_MODE_SGMII     0x0001
-
-struct memac_mdio_controller {
-	u32	res0[0xc];
-	u32	mdio_stat;	/* MDIO configuration and status */
-	u32	mdio_ctl;	/* MDIO control */
-	u32	mdio_data;	/* MDIO data */
-	u32	mdio_addr;	/* MDIO address */
-};
-
-#define MDIO_STAT_CLKDIV(x)	(((x>>1) & 0xff) << 8)
-#define MDIO_STAT_BSY		(1 << 0)
-#define MDIO_STAT_RD_ER		(1 << 1)
-#define MDIO_STAT_PRE		(1 << 5)
-#define MDIO_STAT_ENC		(1 << 6)
-#define MDIO_STAT_HOLD_15_CLK	(7 << 2)
-#define MDIO_STAT_NEG		(1 << 23)
-
-#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
-#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
-#define MDIO_CTL_PRE_DIS	(1 << 10)
-#define MDIO_CTL_SCAN_EN	(1 << 11)
-#define MDIO_CTL_POST_INC	(1 << 14)
-#define MDIO_CTL_READ		(1 << 15)
-
-#define MDIO_DATA(x)		(x & 0xffff)
-#define MDIO_DATA_BSY		(1 << 31)
-
-struct fsl_enet_mac;
-
-void init_memac(struct fsl_enet_mac *mac, void *base, void *phyregs,
-		int max_rx_len);
-
-#endif
diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h
index 49f6814..8f794ef 100644
--- a/arch/powerpc/include/asm/fsl_secure_boot.h
+++ b/arch/powerpc/include/asm/fsl_secure_boot.h
@@ -67,5 +67,24 @@
 #define CONFIG_FSL_ISBC_KEY_EXT
 #endif
 
+#ifndef CONFIG_FIT_SIGNATURE
+/* The bootscript header address is different for B4860 because the NOR
+ * mapping is different on B4 due to reduced NOR size.
+ */
+#if defined(CONFIG_B4860QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xecc00000
+#elif defined(CONFIG_FSL_CORENET)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xe8e00000
+#elif defined(CONFIG_BSC9132QDS)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0x88020000
+#elif defined(CONFIG_C29XPCIE)
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xec020000
+#else
+#define CONFIG_BOOTSCRIPT_HDR_ADDR	0xee020000
+#endif
+
+#include <config_fsl_secboot.h>
+#endif
+
 #endif
 #endif
diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c
index 91645d3..5ea29cc 100644
--- a/arch/powerpc/lib/board.c
+++ b/arch/powerpc/lib/board.c
@@ -890,7 +890,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
 #if defined(CONFIG_CMD_NET)
 	WATCHDOG_RESET();
 	puts("Net:   ");
-	eth_initialize(bd);
+	eth_initialize();
 #endif
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index 2098b9c..8aac96f 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -10,28 +10,26 @@ config SYS_BOARD
 config SYS_CONFIG_NAME
 	default "sandbox"
 
-config DM
-	default y
-
-config DM_GPIO
-	default y
-
-config DM_SERIAL
+config DM_TEST
 	default y
 
-config DM_CROS_EC
-	default y
+config PCI
+	bool "PCI support"
+	help
+	  Enable support for PCI (Peripheral Interconnect Bus), a type of bus
+	  used on some devices to allow the CPU to communicate with its
+	  peripherals.
 
-config DM_SPI
+config NET
 	default y
 
-config DM_SPI_FLASH
+config NETDEVICES
 	default y
 
-config DM_I2C
+config DM_ETH
 	default y
 
-config DM_TEST
+config ETH_SANDBOX_RAW
 	default y
 
 endmenu
diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile
index 7d4410c..1b42fee 100644
--- a/arch/sandbox/cpu/Makefile
+++ b/arch/sandbox/cpu/Makefile
@@ -8,6 +8,7 @@
 #
 
 obj-y	:= cpu.o os.o start.o state.o
+obj-$(CONFIG_ETH_SANDBOX_RAW)	+= eth-raw-os.o
 obj-$(CONFIG_SANDBOX_SDL)	+= sdl.o
 
 # os.c is build in the system environment, so needs standard includes
@@ -20,3 +21,12 @@ $(obj)/os.o: $(src)/os.c FORCE
 	$(call if_changed_dep,cc_os.o)
 $(obj)/sdl.o: $(src)/sdl.c FORCE
 	$(call if_changed_dep,cc_os.o)
+
+# eth-raw-os.c is built in the system env, so needs standard includes
+# CFLAGS_REMOVE_eth-raw-os.o cannot be used to drop header include path
+quiet_cmd_cc_eth-raw-os.o = CC $(quiet_modtag)  $@
+cmd_cc_eth-raw-os.o = $(CC) $(filter-out -nostdinc, \
+	$(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $<
+
+$(obj)/eth-raw-os.o: $(src)/eth-raw-os.c FORCE
+	$(call if_changed_dep,cc_eth-raw-os.o)
diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c
index 1aa397c..168f2ef 100644
--- a/arch/sandbox/cpu/cpu.c
+++ b/arch/sandbox/cpu/cpu.c
@@ -2,14 +2,24 @@
  * Copyright (c) 2011 The Chromium OS Authors.
  * SPDX-License-Identifier:	GPL-2.0+
  */
-
+#define DEBUG
 #include <common.h>
 #include <dm/root.h>
 #include <os.h>
+#include <asm/io.h>
 #include <asm/state.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Enable access to PCI memory with map_sysmem() */
+static bool enable_pci_map;
+
+#ifdef CONFIG_PCI
+/* Last device that was mapped into memory, and length of mapping */
+static struct udevice *map_dev;
+unsigned long map_len;
+#endif
+
 void reset_cpu(ulong ignored)
 {
 	if (state_uninit())
@@ -40,26 +50,44 @@ unsigned long __attribute__((no_instrument_function)) timer_get_us(void)
 	return os_get_nsec() / 1000;
 }
 
-int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+int cleanup_before_linux(void)
 {
-	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
-		bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-		printf("## Transferring control to Linux (at address %08lx)...\n",
-		       images->ep);
-		reset_cpu(0);
+	return 0;
+}
+
+void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+#ifdef CONFIG_PCI
+	unsigned long plen = len;
+	void *ptr;
+
+	map_dev = NULL;
+	if (enable_pci_map && !pci_map_physmem(paddr, &len, &map_dev, &ptr)) {
+		if (plen != len) {
+			printf("%s: Warning: partial map at %x, wanted %lx, got %lx\n",
+			       __func__, paddr, len, plen);
+		}
+		map_len = len;
+		return ptr;
 	}
+#endif
 
-	return 0;
+	return (void *)(gd->arch.ram_buf + paddr);
 }
 
-int cleanup_before_linux(void)
+void unmap_physmem(const void *vaddr, unsigned long flags)
 {
-	return 0;
+#ifdef CONFIG_PCI
+	if (map_dev) {
+		pci_unmap_physmem(vaddr, map_len, map_dev);
+		map_dev = NULL;
+	}
+#endif
 }
 
-void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+void sandbox_set_enable_pci_map(int enable)
 {
-	return (void *)(gd->arch.ram_buf + paddr);
+	enable_pci_map = enable;
 }
 
 phys_addr_t map_to_sysmem(const void *ptr)
@@ -70,3 +98,43 @@ phys_addr_t map_to_sysmem(const void *ptr)
 void flush_dcache_range(unsigned long start, unsigned long stop)
 {
 }
+
+int sandbox_read_fdt_from_file(void)
+{
+	struct sandbox_state *state = state_get_current();
+	const char *fname = state->fdt_fname;
+	void *blob;
+	loff_t size;
+	int err;
+	int fd;
+
+	blob = map_sysmem(CONFIG_SYS_FDT_LOAD_ADDR, 0);
+	if (!state->fdt_fname) {
+		err = fdt_create_empty_tree(blob, 256);
+		if (!err)
+			goto done;
+		printf("Unable to create empty FDT: %s\n", fdt_strerror(err));
+		return -EINVAL;
+	}
+
+	err = os_get_filesize(fname, &size);
+	if (err < 0) {
+		printf("Failed to file FDT file '%s'\n", fname);
+		return err;
+	}
+	fd = os_open(fname, OS_O_RDONLY);
+	if (fd < 0) {
+		printf("Failed to open FDT file '%s'\n", fname);
+		return -EACCES;
+	}
+	if (os_read(fd, blob, size) != size) {
+		os_close(fd);
+		return -EIO;
+	}
+	os_close(fd);
+
+done:
+	gd->fdt_blob = blob;
+
+	return 0;
+}
diff --git a/arch/sandbox/cpu/eth-raw-os.c b/arch/sandbox/cpu/eth-raw-os.c
new file mode 100644
index 0000000..b76a731
--- /dev/null
+++ b/arch/sandbox/cpu/eth-raw-os.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <asm/eth-raw-os.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <net/if.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/udp.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#include <unistd.h>
+
+#include <arpa/inet.h>
+#include <linux/if_ether.h>
+#include <linux/if_packet.h>
+
+static int _raw_packet_start(const char *ifname, unsigned char *ethmac,
+			    struct eth_sandbox_raw_priv *priv)
+{
+	struct sockaddr_ll *device;
+	struct packet_mreq mr;
+	int ret;
+	int flags;
+
+	/* Prepare device struct */
+	priv->device = malloc(sizeof(struct sockaddr_ll));
+	if (priv->device == NULL)
+		return -ENOMEM;
+	device = priv->device;
+	memset(device, 0, sizeof(struct sockaddr_ll));
+	device->sll_ifindex = if_nametoindex(ifname);
+	device->sll_family = AF_PACKET;
+	memcpy(device->sll_addr, ethmac, 6);
+	device->sll_halen = htons(6);
+
+	/* Open socket */
+	priv->sd = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
+	if (priv->sd < 0) {
+		printf("Failed to open socket: %d %s\n", errno,
+		       strerror(errno));
+		return -errno;
+	}
+	/* Bind to the specified interface */
+	ret = setsockopt(priv->sd, SOL_SOCKET, SO_BINDTODEVICE, ifname,
+		   strlen(ifname) + 1);
+	if (ret < 0) {
+		printf("Failed to bind to '%s': %d %s\n", ifname, errno,
+		       strerror(errno));
+		return -errno;
+	}
+
+	/* Make the socket non-blocking */
+	flags = fcntl(priv->sd, F_GETFL, 0);
+	fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK);
+
+	/* Enable promiscuous mode to receive responses meant for us */
+	mr.mr_ifindex = device->sll_ifindex;
+	mr.mr_type = PACKET_MR_PROMISC;
+	ret = setsockopt(priv->sd, SOL_PACKET, PACKET_ADD_MEMBERSHIP,
+		   &mr, sizeof(mr));
+	if (ret < 0) {
+		struct ifreq ifr;
+
+		printf("Failed to set promiscuous mode: %d %s\n"
+		       "Falling back to the old \"flags\" way...\n",
+			errno, strerror(errno));
+		strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
+		if (ioctl(priv->sd, SIOCGIFFLAGS, &ifr) < 0) {
+			printf("Failed to read flags: %d %s\n", errno,
+			       strerror(errno));
+			return -errno;
+		}
+		ifr.ifr_flags |= IFF_PROMISC;
+		if (ioctl(priv->sd, SIOCSIFFLAGS, &ifr) < 0) {
+			printf("Failed to write flags: %d %s\n", errno,
+			       strerror(errno));
+			return -errno;
+		}
+	}
+	return 0;
+}
+
+static int _local_inet_start(struct eth_sandbox_raw_priv *priv)
+{
+	struct sockaddr_in *device;
+	int ret;
+	int flags;
+	int one = 1;
+
+	/* Prepare device struct */
+	priv->device = malloc(sizeof(struct sockaddr_in));
+	if (priv->device == NULL)
+		return -ENOMEM;
+	device = priv->device;
+	memset(device, 0, sizeof(struct sockaddr_in));
+	device->sin_family = AF_INET;
+	device->sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+
+	/**
+	 * Open socket
+	 *  Since we specify UDP here, any incoming ICMP packets will
+	 *  not be received, so things like ping will not work on this
+	 *  localhost interface.
+	 */
+	priv->sd = socket(AF_INET, SOCK_RAW, IPPROTO_UDP);
+	if (priv->sd < 0) {
+		printf("Failed to open socket: %d %s\n", errno,
+		       strerror(errno));
+		return -errno;
+	}
+
+	/* Make the socket non-blocking */
+	flags = fcntl(priv->sd, F_GETFL, 0);
+	fcntl(priv->sd, F_SETFL, flags | O_NONBLOCK);
+
+	/* Include the UDP/IP headers on send and receive */
+	ret = setsockopt(priv->sd, IPPROTO_IP, IP_HDRINCL, &one,
+			 sizeof(one));
+	if (ret < 0) {
+		printf("Failed to set header include option: %d %s\n", errno,
+		       strerror(errno));
+		return -errno;
+	}
+	priv->local_bind_sd = -1;
+	priv->local_bind_udp_port = 0;
+	return 0;
+}
+
+int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac,
+			    struct eth_sandbox_raw_priv *priv)
+{
+	if (priv->local)
+		return _local_inet_start(priv);
+	else
+		return _raw_packet_start(ifname, ethmac, priv);
+}
+
+int sandbox_eth_raw_os_send(void *packet, int length,
+			    struct eth_sandbox_raw_priv *priv)
+{
+	int retval;
+	struct udphdr *udph = packet + sizeof(struct iphdr);
+
+	if (!priv->sd || !priv->device)
+		return -EINVAL;
+
+	/*
+	 * This block of code came about when testing tftp on the localhost
+	 * interface. When using the RAW AF_INET API, the network stack is still
+	 * in play responding to incoming traffic based on open "ports". Since
+	 * it is raw (at the IP layer, no Ethernet) the network stack tells the
+	 * TFTP server that the port it responded to is closed. This causes the
+	 * TFTP transfer to be aborted. This block of code inspects the outgoing
+	 * packet as formulated by the u-boot network stack to determine the
+	 * source port (that the TFTP server will send packets back to) and
+	 * opens a typical UDP socket on that port, thus preventing the network
+	 * stack from sending that ICMP message claiming that the port has no
+	 * bound socket.
+	 */
+	if (priv->local && (priv->local_bind_sd == -1 ||
+			    priv->local_bind_udp_port != udph->source)) {
+		struct iphdr *iph = packet;
+		struct sockaddr_in addr;
+
+		if (priv->local_bind_sd != -1)
+			close(priv->local_bind_sd);
+
+		/* A normal UDP socket is required to bind */
+		priv->local_bind_sd = socket(AF_INET, SOCK_DGRAM, 0);
+		if (priv->local_bind_sd < 0) {
+			printf("Failed to open bind sd: %d %s\n", errno,
+			       strerror(errno));
+			return -errno;
+		}
+		priv->local_bind_udp_port = udph->source;
+
+		/**
+		 * Bind the UDP port that we intend to use as our source port
+		 * so that the kernel will not send an ICMP port unreachable
+		 * message to the server
+		 */
+		addr.sin_family = AF_INET;
+		addr.sin_port = udph->source;
+		addr.sin_addr.s_addr = iph->saddr;
+		retval = bind(priv->local_bind_sd, &addr, sizeof(addr));
+		if (retval < 0)
+			printf("Failed to bind: %d %s\n", errno,
+			       strerror(errno));
+	}
+
+	retval = sendto(priv->sd, packet, length, 0,
+			(struct sockaddr *)priv->device,
+			sizeof(struct sockaddr_ll));
+	if (retval < 0) {
+		printf("Failed to send packet: %d %s\n", errno,
+		       strerror(errno));
+		return -errno;
+	}
+	return retval;
+}
+
+int sandbox_eth_raw_os_recv(void *packet, int *length,
+			    const struct eth_sandbox_raw_priv *priv)
+{
+	int retval;
+	int saddr_size;
+
+	if (!priv->sd || !priv->device)
+		return -EINVAL;
+	saddr_size = sizeof(struct sockaddr);
+	retval = recvfrom(priv->sd, packet, 1536, 0,
+			  (struct sockaddr *)priv->device,
+			  (socklen_t *)&saddr_size);
+	*length = 0;
+	if (retval >= 0) {
+		*length = retval;
+		return 0;
+	}
+	/* The socket is non-blocking, so expect EAGAIN when there is no data */
+	if (errno == EAGAIN)
+		return 0;
+	return -errno;
+}
+
+void sandbox_eth_raw_os_stop(struct eth_sandbox_raw_priv *priv)
+{
+	free(priv->device);
+	priv->device = NULL;
+	close(priv->sd);
+	priv->sd = -1;
+	if (priv->local) {
+		if (priv->local_bind_sd != -1)
+			close(priv->local_bind_sd);
+		priv->local_bind_sd = -1;
+		priv->local_bind_udp_port = 0;
+	}
+}
diff --git a/arch/sandbox/dts/cros-ec-keyboard.dtsi b/arch/sandbox/dts/cros-ec-keyboard.dtsi
new file mode 100644
index 0000000..9c7fb0a
--- /dev/null
+++ b/arch/sandbox/dts/cros-ec-keyboard.dtsi
@@ -0,0 +1,105 @@
+/*
+ * Keyboard dts fragment for devices that use cros-ec-keyboard
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <dt-bindings/input/input.h>
+
+&cros_ec {
+	keyboard-controller {
+		compatible = "google,cros-ec-keyb";
+		keypad,num-rows = <8>;
+		keypad,num-columns = <13>;
+		google,needs-ghost-filter;
+
+		linux,keymap = <
+			MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
+			MATRIX_KEY(0x00, 0x02, KEY_F1)
+			MATRIX_KEY(0x00, 0x03, KEY_B)
+			MATRIX_KEY(0x00, 0x04, KEY_F10)
+			MATRIX_KEY(0x00, 0x06, KEY_N)
+			MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
+			MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
+
+			MATRIX_KEY(0x01, 0x01, KEY_ESC)
+			MATRIX_KEY(0x01, 0x02, KEY_F4)
+			MATRIX_KEY(0x01, 0x03, KEY_G)
+			MATRIX_KEY(0x01, 0x04, KEY_F7)
+			MATRIX_KEY(0x01, 0x06, KEY_H)
+			MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
+			MATRIX_KEY(0x01, 0x09, KEY_F9)
+			MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
+
+			MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
+			MATRIX_KEY(0x02, 0x01, KEY_TAB)
+			MATRIX_KEY(0x02, 0x02, KEY_F3)
+			MATRIX_KEY(0x02, 0x03, KEY_T)
+			MATRIX_KEY(0x02, 0x04, KEY_F6)
+			MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
+			MATRIX_KEY(0x02, 0x06, KEY_Y)
+			MATRIX_KEY(0x02, 0x07, KEY_102ND)
+			MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
+			MATRIX_KEY(0x02, 0x09, KEY_F8)
+
+			MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
+			MATRIX_KEY(0x03, 0x02, KEY_F2)
+			MATRIX_KEY(0x03, 0x03, KEY_5)
+			MATRIX_KEY(0x03, 0x04, KEY_F5)
+			MATRIX_KEY(0x03, 0x06, KEY_6)
+			MATRIX_KEY(0x03, 0x08, KEY_MINUS)
+			MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
+
+			MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
+			MATRIX_KEY(0x04, 0x01, KEY_A)
+			MATRIX_KEY(0x04, 0x02, KEY_D)
+			MATRIX_KEY(0x04, 0x03, KEY_F)
+			MATRIX_KEY(0x04, 0x04, KEY_S)
+			MATRIX_KEY(0x04, 0x05, KEY_K)
+			MATRIX_KEY(0x04, 0x06, KEY_J)
+			MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
+			MATRIX_KEY(0x04, 0x09, KEY_L)
+			MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
+			MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
+
+			MATRIX_KEY(0x05, 0x01, KEY_Z)
+			MATRIX_KEY(0x05, 0x02, KEY_C)
+			MATRIX_KEY(0x05, 0x03, KEY_V)
+			MATRIX_KEY(0x05, 0x04, KEY_X)
+			MATRIX_KEY(0x05, 0x05, KEY_COMMA)
+			MATRIX_KEY(0x05, 0x06, KEY_M)
+			MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
+			MATRIX_KEY(0x05, 0x08, KEY_SLASH)
+			MATRIX_KEY(0x05, 0x09, KEY_DOT)
+			MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
+
+			MATRIX_KEY(0x06, 0x01, KEY_1)
+			MATRIX_KEY(0x06, 0x02, KEY_3)
+			MATRIX_KEY(0x06, 0x03, KEY_4)
+			MATRIX_KEY(0x06, 0x04, KEY_2)
+			MATRIX_KEY(0x06, 0x05, KEY_8)
+			MATRIX_KEY(0x06, 0x06, KEY_7)
+			MATRIX_KEY(0x06, 0x08, KEY_0)
+			MATRIX_KEY(0x06, 0x09, KEY_9)
+			MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
+			MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
+			MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
+
+			MATRIX_KEY(0x07, 0x01, KEY_Q)
+			MATRIX_KEY(0x07, 0x02, KEY_E)
+			MATRIX_KEY(0x07, 0x03, KEY_R)
+			MATRIX_KEY(0x07, 0x04, KEY_W)
+			MATRIX_KEY(0x07, 0x05, KEY_I)
+			MATRIX_KEY(0x07, 0x06, KEY_U)
+			MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
+			MATRIX_KEY(0x07, 0x08, KEY_P)
+			MATRIX_KEY(0x07, 0x09, KEY_O)
+			MATRIX_KEY(0x07, 0x0b, KEY_UP)
+			MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
+		>;
+	};
+};
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 9ce31bf..efa2097 100644
--- a/arch/sandbox/dts/sandbox.dts
+++ b/arch/sandbox/dts/sandbox.dts
@@ -1,8 +1,15 @@
 /dts-v1/;
 
+#define USB_CLASS_HUB			9
+
 / {
 	#address-cells = <1>;
-	#size-cells = <0>;
+	#size-cells = <1>;
+
+	aliases {
+		eth5 = "/eth@90000000";
+		pci0 = &pci;
+	};
 
 	chosen {
 		stdout-path = "/serial";
@@ -32,36 +39,31 @@
 		sides = <6>;
 	};
 
-	host@0 {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "sandbox,host-emulation";
-		cros-ec@0 {
-			reg = <0>;
-			compatible = "google,cros-ec";
+	cros_ec: cros-ec@0 {
+		reg = <0 0>;
+		compatible = "google,cros-ec-sandbox";
 
-			/*
-			 * This describes the flash memory within the EC. Note
-			 * that the STM32L flash erases to 0, not 0xff.
-			 */
+		/*
+		 * This describes the flash memory within the EC. Note
+		 * that the STM32L flash erases to 0, not 0xff.
+		 */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		flash@8000000 {
+			reg = <0x08000000 0x20000>;
+			erase-value = <0>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			flash@8000000 {
-				reg = <0x08000000 0x20000>;
-				erase-value = <0>;
-				#address-cells = <1>;
-				#size-cells = <1>;
 
-				/* Information for sandbox */
-				ro {
-					reg = <0 0xf000>;
-				};
-				wp-ro {
-					reg = <0xf000 0x1000>;
-				};
-				rw {
-					reg = <0x10000 0x10000>;
-				};
+			/* Information for sandbox */
+			ro {
+				reg = <0 0xf000>;
+			};
+			wp-ro {
+				reg = <0xf000 0x1000>;
+			};
+			rw {
+				reg = <0x10000 0x10000>;
 			};
 		};
 	};
@@ -72,59 +74,6 @@
 		yres = <600>;
 	};
 
-	cros-ec-keyb {
-		compatible = "google,cros-ec-keyb";
-		keypad,num-rows = <8>;
-		keypad,num-columns = <13>;
-		google,ghost-filter;
-		/*
-		 * Keymap entries take the form of 0xRRCCKKKK where
-		 * RR=Row CC=Column KKKK=Key Code
-		 * The values below are for a US keyboard layout and
-		 * are taken from the Linux driver. Note that the
-		 * 102ND key is not used for US keyboards.
-		 */
-		linux,keymap = <
-			/* CAPSLCK F1         B          F10     */
-			0x0001003a 0x0002003b 0x00030030 0x00040044
-			/* N       =          R_ALT      ESC     */
-			0x00060031 0x0008000d 0x000a0064 0x01010001
-			/* F4      G          F7         H       */
-			0x0102003e 0x01030022 0x01040041 0x01060023
-			/* '       F9         BKSPACE    L_CTRL  */
-			0x01080028 0x01090043 0x010b000e 0x0200001d
-			/* TAB     F3         T          F6      */
-			0x0201000f 0x0202003d 0x02030014 0x02040040
-			/* ]       Y          102ND      [       */
-			0x0205001b 0x02060015 0x02070056 0x0208001a
-			/* F8      GRAVE      F2         5       */
-			0x02090042 0x03010029 0x0302003c 0x03030006
-			/* F5      6          -          \       */
-			0x0304003f 0x03060007 0x0308000c 0x030b002b
-			/* R_CTRL  A          D          F       */
-			0x04000061 0x0401001e 0x04020020 0x04030021
-			/* S       K          J          ;       */
-			0x0404001f 0x04050025 0x04060024 0x04080027
-			/* L       ENTER      Z          C       */
-			0x04090026 0x040b001c 0x0501002c 0x0502002e
-			/* V       X          ,          M       */
-			0x0503002f 0x0504002d 0x05050033 0x05060032
-			/* L_SHIFT /          .          SPACE   */
-			0x0507002a 0x05080035 0x05090034 0x050B0039
-			/* 1       3          4          2       */
-			0x06010002 0x06020004 0x06030005 0x06040003
-			/* 8       7          0          9       */
-			0x06050009 0x06060008 0x0608000b 0x0609000a
-			/* L_ALT   DOWN       RIGHT      Q       */
-			0x060a0038 0x060b006c 0x060c006a 0x07010010
-			/* E       R          W          I       */
-			0x07020012 0x07030013 0x07040011 0x07050017
-			/* U       R_SHIFT    P          O       */
-			0x07060016 0x07070036 0x07080019 0x07090018
-			/* UP      LEFT    */
-			0x070b0067 0x070c0069>;
-	};
-
 	gpio_a: gpios@0 {
 		gpio-controller;
 		compatible = "sandbox,gpio";
@@ -144,7 +93,7 @@
 	i2c@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reg = <0>;
+		reg = <0 0>;
 		compatible = "sandbox,i2c";
 		clock-frequency = <400000>;
 		eeprom@2c {
@@ -161,10 +110,10 @@
 	spi@0 {
 		#address-cells = <1>;
 		#size-cells = <0>;
-		reg = <0>;
+		reg = <0 0>;
 		compatible = "sandbox,spi";
 		cs-gpios = <0>, <&gpio_a 0>;
-		flash@0 {
+		firmware_storage_spi: flash@0 {
 			reg = <0>;
 			compatible = "spansion,m25p16", "sandbox,spi-flash";
 			spi-max-frequency = <40000000>;
@@ -172,13 +121,77 @@
 		};
 	};
 
-	cros-ec@0 {
-		compatible = "google,cros-ec";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		firmware_storage_spi: flash@0 {
-			reg = <0 0x400000>;
+	pci: pci-controller {
+		compatible = "sandbox,pci";
+		device_type = "pci";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
+				0x01000000 0 0x20000000 0x20000000 0 0x2000>;
+		pci@1f,0 {
+			compatible = "pci-generic";
+			reg = <0xf800 0 0 0 0>;
+			emul@1f,0 {
+				compatible = "sandbox,swap-case";
+			};
+		};
+	};
+
+	eth@10002000 {
+		compatible = "sandbox,eth";
+		reg = <0x10002000 0x1000>;
+		fake-host-hwaddr = [00 00 66 44 22 00];
+	};
+
+	eth@80000000 {
+		compatible = "sandbox,eth-raw";
+		reg = <0x80000000 0x1000>;
+		host-raw-interface = "eth0";
+	};
+
+	eth@90000000 {
+		compatible = "sandbox,eth-raw";
+		reg = <0x90000000 0x1000>;
+		host-raw-interface = "lo";
+	};
+
+	usb@0 {
+		compatible = "sandbox,usb";
+		status = "disabled";
+		hub {
+			compatible = "sandbox,usb-hub";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			flash-stick {
+				reg = <0>;
+				compatible = "sandbox,usb-flash";
+			};
 		};
 	};
 
+	usb@1 {
+		compatible = "sandbox,usb";
+		hub {
+			compatible = "usb-hub";
+			usb,device-class = <USB_CLASS_HUB>;
+			hub-emul {
+				compatible = "sandbox,usb-hub";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				flash-stick {
+					reg = <0>;
+					compatible = "sandbox,usb-flash";
+					sandbox,filepath = "flash.bin";
+				};
+			};
+		};
+	};
+
+	usb@2 {
+		compatible = "sandbox,usb";
+		status = "disabled";
+	};
+
 };
+
+#include "cros-ec-keyboard.dtsi"
diff --git a/arch/sandbox/include/asm/bitops.h b/arch/sandbox/include/asm/bitops.h
index e807c4e..f1a7aee 100644
--- a/arch/sandbox/include/asm/bitops.h
+++ b/arch/sandbox/include/asm/bitops.h
@@ -1,6 +1,8 @@
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  *
+ * Modified from Linux arch/arm/include/asm/bitops.h
+ *
  * Copyright 1995, Russell King.
  * Various bits and pieces copyrights include:
  *  Linus Torvalds (test_bit).
diff --git a/arch/sandbox/include/asm/eth-raw-os.h b/arch/sandbox/include/asm/eth-raw-os.h
new file mode 100644
index 0000000..ed4b2e2
--- /dev/null
+++ b/arch/sandbox/include/asm/eth-raw-os.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ETH_RAW_OS_H
+#define __ETH_RAW_OS_H
+
+/**
+ * struct eth_sandbox_raw_priv - raw socket session
+ *
+ * sd: socket descriptor - the open socket during a session
+ * device: struct sockaddr_ll - the host interface packets move to/from
+ * local: 1 or 0 to select the local interface ('lo') or not
+ * local_bindsd: socket descriptor to prevent the kernel from sending
+ *		 a message to the server claiming the port is
+ *		 unreachable
+ * local_bind_udp_port: The UDP port number that we bound to
+ */
+struct eth_sandbox_raw_priv {
+	int sd;
+	void *device;
+	int local;
+	int local_bind_sd;
+	unsigned short local_bind_udp_port;
+};
+
+int sandbox_eth_raw_os_start(const char *ifname, unsigned char *ethmac,
+			    struct eth_sandbox_raw_priv *priv);
+int sandbox_eth_raw_os_send(void *packet, int length,
+			    struct eth_sandbox_raw_priv *priv);
+int sandbox_eth_raw_os_recv(void *packet, int *length,
+			    const struct eth_sandbox_raw_priv *priv);
+void sandbox_eth_raw_os_stop(struct eth_sandbox_raw_priv *priv);
+
+#endif /* __ETH_RAW_OS_H */
diff --git a/arch/sandbox/include/asm/eth.h b/arch/sandbox/include/asm/eth.h
new file mode 100644
index 0000000..4b79ede
--- /dev/null
+++ b/arch/sandbox/include/asm/eth.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2015 National Instruments
+ *
+ * (C) Copyright 2015
+ * Joe Hershberger <joe.hershberger@ni.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __ETH_H
+#define __ETH_H
+
+void sandbox_eth_disable_response(int index, bool disable);
+
+#endif /* __ETH_H */
diff --git a/arch/sandbox/include/asm/io.h b/arch/sandbox/include/asm/io.h
index 895fcb8..5b87fde 100644
--- a/arch/sandbox/include/asm/io.h
+++ b/arch/sandbox/include/asm/io.h
@@ -22,10 +22,7 @@ void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags);
 /*
  * Take down a mapping set up by map_physmem().
  */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
+void unmap_physmem(const void *vaddr, unsigned long flags);
 
 /* For sandbox, we want addresses to point into our RAM buffer */
 static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
@@ -33,8 +30,10 @@ static inline void *map_sysmem(phys_addr_t paddr, unsigned long len)
 	return map_physmem(paddr, len, MAP_WRBACK);
 }
 
+/* Remove a previous mapping */
 static inline void unmap_sysmem(const void *vaddr)
 {
+	unmap_physmem(vaddr, MAP_WRBACK);
 }
 
 /* Map from a pointer to our RAM buffer */
@@ -48,6 +47,15 @@ phys_addr_t map_to_sysmem(const void *ptr);
 #define writew(v, addr)
 #define writel(v, addr)
 
+/* I/O access functions */
+int inl(unsigned int addr);
+int inw(unsigned int addr);
+int inb(unsigned int addr);
+
+void outl(unsigned int value, unsigned int addr);
+void outw(unsigned int value, unsigned int addr);
+void outb(unsigned int value, unsigned int addr);
+
 #include <iotrace.h>
 
 #endif
diff --git a/arch/sandbox/include/asm/processor.h b/arch/sandbox/include/asm/processor.h
new file mode 100644
index 0000000..3c1794e
--- /dev/null
+++ b/arch/sandbox/include/asm/processor.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ASM_PROCESSOR_H
+#define _ASM_PROCESSOR_H
+
+/* This file is required for PCI */
+
+#endif
diff --git a/arch/sandbox/include/asm/test.h b/arch/sandbox/include/asm/test.h
index 25a0c85..8e490e9 100644
--- a/arch/sandbox/include/asm/test.h
+++ b/arch/sandbox/include/asm/test.h
@@ -10,7 +10,12 @@
 #define __ASM_TEST_H
 
 /* The sandbox driver always permits an I2C device with this address */
-#define SANDBOX_I2C_TEST_ADDR	0x59
+#define SANDBOX_I2C_TEST_ADDR		0x59
+
+#define SANDBOX_PCI_VENDOR_ID		0x1234
+#define SANDBOX_PCI_DEVICE_ID		0x5678
+#define SANDBOX_PCI_CLASS_CODE		PCI_CLASS_CODE_COMM
+#define SANDBOX_PCI_CLASS_SUB_CODE	PCI_CLASS_SUB_CODE_COMM_SERIAL
 
 enum sandbox_i2c_eeprom_test_mode {
 	SIE_TEST_MODE_NONE,
diff --git a/arch/sandbox/include/asm/u-boot-sandbox.h b/arch/sandbox/include/asm/u-boot-sandbox.h
index 770ab5c..da87cc3 100644
--- a/arch/sandbox/include/asm/u-boot-sandbox.h
+++ b/arch/sandbox/include/asm/u-boot-sandbox.h
@@ -27,4 +27,60 @@ int cleanup_before_linux(void);
 /* drivers/video/sandbox_sdl.c */
 int sandbox_lcd_sdl_early_init(void);
 
+/**
+ * pci_map_physmem() - map a PCI device into memory
+ *
+ * This is used on sandbox to map a device into memory so that it can be
+ * used with normal memory access. After this call, some part of the device's
+ * internal structure becomes visible.
+ *
+ * This function is normally called from sandbox's map_sysmem() automatically.
+ *
+ * @paddr:	Physical memory address, normally corresponding to a PCI BAR
+ * @lenp:	On entry, the size of the area to map, On exit it is updated
+ *		to the size actually mapped, which may be less if the device
+ *		has less space
+ * @devp:	Returns the device which mapped into this space
+ * @ptrp:	Returns a pointer to the mapped address. The device's space
+ *		can be accessed as @lenp bytes starting here
+ * @return 0 if OK, -ve on error
+ */
+int pci_map_physmem(phys_addr_t paddr, unsigned long *lenp,
+		    struct udevice **devp, void **ptrp);
+
+/**
+ * pci_unmap_physmem() - undo a memory mapping
+ *
+ * This must be called after pci_map_physmem() to undo the mapping.
+ *
+ * @paddr:	Physical memory address, as passed to pci_map_physmem()
+ * @len:	Size of area mapped, as returned by pci_map_physmem()
+ * @dev:	Device to unmap, as returned by pci_map_physmem()
+ * @return 0 if OK, -ve on error
+ */
+int pci_unmap_physmem(const void *addr, unsigned long len,
+		      struct udevice *dev);
+
+/**
+ * sandbox_set_enable_pci_map() - Enable / disable PCI address mapping
+ *
+ * Since address mapping involves calling every driver, provide a way to
+ * enable and disable this. It can be handled automatically by the emulator
+ * uclass, which knows if any emulators are currently active.
+ *
+ * If this is disabled, pci_map_physmem() will not be called from
+ * map_sysmem().
+ *
+ * @enable: 0 to disable, 1 to enable
+ */
+void sandbox_set_enable_pci_map(int enable);
+
+/**
+ * sandbox_read_fdt_from_file() - Read a device tree from a file
+ *
+ * Read a device tree file from a host file and set it up for use as the
+ * control FDT.
+ */
+int sandbox_read_fdt_from_file(void);
+
 #endif	/* _U_BOOT_SANDBOX_H_ */
diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile
index 4c1a38d..96761e2 100644
--- a/arch/sandbox/lib/Makefile
+++ b/arch/sandbox/lib/Makefile
@@ -7,5 +7,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-
 obj-y	+= interrupts.o
+obj-$(CONFIG_PCI)	+= pci_io.o
+obj-$(CONFIG_CMD_BOOTM) += bootm.o
diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c
new file mode 100644
index 0000000..d49c927
--- /dev/null
+++ b/arch/sandbox/lib/bootm.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2015 Sjoerd Simons <sjoerd.simons@collabora.co.uk>
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define	LINUX_ARM_ZIMAGE_MAGIC	0x016f2818
+
+struct arm_z_header {
+	uint32_t	code[9];
+	uint32_t	zi_magic;
+	uint32_t	zi_start;
+	uint32_t	zi_end;
+} __attribute__ ((__packed__));
+
+int bootz_setup(ulong image, ulong *start, ulong *end)
+{
+	uint8_t *zimage = map_sysmem(image, 0);
+	struct arm_z_header *arm_hdr = (struct arm_z_header *)zimage;
+	int ret = 0;
+
+	if (memcmp(zimage + 0x202, "HdrS", 4) == 0) {
+		uint8_t setup_sects = *(zimage + 0x1f1);
+		uint32_t syssize =
+			le32_to_cpu(*(uint32_t *)(zimage + 0x1f4));
+
+		*start = 0;
+		*end = (setup_sects + 1) * 512 + syssize * 16;
+
+		printf("setting up X86 zImage [ %ld - %ld ]\n",
+		       *start, *end);
+	} else if (le32_to_cpu(arm_hdr->zi_magic) == LINUX_ARM_ZIMAGE_MAGIC) {
+		*start = le32_to_cpu(arm_hdr->zi_start);
+		*end = le32_to_cpu(arm_hdr->zi_end);
+
+		printf("setting up ARM zImage [ %ld - %ld ]\n",
+		       *start, *end);
+	} else {
+		printf("Unrecognized zImage\n");
+		ret = 1;
+	}
+
+	unmap_sysmem((void *)image);
+
+	return ret;
+}
+
+int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
+{
+	if (flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO)) {
+		bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+		printf("## Transferring control to Linux (at address %08lx)...\n",
+		       images->ep);
+		reset_cpu(0);
+	}
+
+	return 0;
+}
diff --git a/arch/sandbox/lib/pci_io.c b/arch/sandbox/lib/pci_io.c
new file mode 100644
index 0000000..0de124f
--- /dev/null
+++ b/arch/sandbox/lib/pci_io.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/*
+ * IO space access commands.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <asm/io.h>
+
+int pci_map_physmem(phys_addr_t paddr, unsigned long *lenp,
+		    struct udevice **devp, void **ptrp)
+{
+	struct udevice *dev;
+	int ret;
+
+	*ptrp = 0;
+	for (uclass_first_device(UCLASS_PCI_EMUL, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev);
+
+		if (!ops || !ops->map_physmem)
+			continue;
+		ret = (ops->map_physmem)(dev, paddr, lenp, ptrp);
+		if (ret)
+			continue;
+		*devp = dev;
+		return 0;
+	}
+
+	debug("%s: failed: addr=%x\n", __func__, paddr);
+	return -ENOSYS;
+}
+
+int pci_unmap_physmem(const void *vaddr, unsigned long len,
+		      struct udevice *dev)
+{
+	struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev);
+
+	if (!ops || !ops->unmap_physmem)
+		return -ENOSYS;
+	return (ops->unmap_physmem)(dev, vaddr, len);
+}
+
+static int pci_io_read(unsigned int addr, ulong *valuep, pci_size_t size)
+{
+	struct udevice *dev;
+	int ret;
+
+	*valuep = pci_get_ff(size);
+	for (uclass_first_device(UCLASS_PCI_EMUL, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev);
+
+		if (ops && ops->read_io) {
+			ret = (ops->read_io)(dev, addr, valuep, size);
+			if (!ret)
+				return 0;
+		}
+	}
+
+	debug("%s: failed: addr=%x\n", __func__, addr);
+	return -ENOSYS;
+}
+
+static int pci_io_write(unsigned int addr, ulong value, pci_size_t size)
+{
+	struct udevice *dev;
+	int ret;
+
+	for (uclass_first_device(UCLASS_PCI_EMUL, &dev);
+	     dev;
+	     uclass_next_device(&dev)) {
+		struct dm_pci_emul_ops *ops = pci_get_emul_ops(dev);
+
+		if (ops && ops->write_io) {
+			ret = (ops->write_io)(dev, addr, value, size);
+			if (!ret)
+				return 0;
+		}
+	}
+
+	debug("%s: failed: addr=%x, value=%lx\n", __func__, addr, value);
+	return -ENOSYS;
+}
+
+int inl(unsigned int addr)
+{
+	unsigned long value;
+	int ret;
+
+	ret = pci_io_read(addr, &value, PCI_SIZE_32);
+
+	return ret ? 0 : value;
+}
+
+int inw(unsigned int addr)
+{
+	unsigned long value;
+	int ret;
+
+	ret = pci_io_read(addr, &value, PCI_SIZE_16);
+
+	return ret ? 0 : value;
+}
+
+int inb(unsigned int addr)
+{
+	unsigned long value;
+	int ret;
+
+	ret = pci_io_read(addr, &value, PCI_SIZE_8);
+
+	return ret ? 0 : value;
+}
+
+void outl(unsigned int value, unsigned int addr)
+{
+	pci_io_write(addr, value, PCI_SIZE_32);
+}
+
+void outw(unsigned int value, unsigned int addr)
+{
+	pci_io_write(addr, value, PCI_SIZE_16);
+}
+
+void outb(unsigned int value, unsigned int addr)
+{
+	pci_io_write(addr, value, PCI_SIZE_8);
+}
diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c
index 1eb7afb..6dad3c7 100644
--- a/arch/sh/lib/board.c
+++ b/arch/sh/lib/board.c
@@ -178,7 +178,7 @@ void sh_generic_init(void)
 #endif
 #if defined(CONFIG_CMD_NET)
 	puts("Net:   ");
-	eth_initialize(gd->bd);
+	eth_initialize();
 #endif /* CONFIG_CMD_NET */
 
 	while (1) {
diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c
index b311a94..d2ac6bc 100644
--- a/arch/sparc/lib/board.c
+++ b/arch/sparc/lib/board.c
@@ -351,7 +351,7 @@ void board_init_f(ulong bootflag)
 #if defined(CONFIG_CMD_NET)
 	WATCHDOG_RESET();
 	puts("Net:   ");
-	eth_initialize(bd);
+	eth_initialize();
 #endif
 
 #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index da27115..3f1401a 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -7,6 +7,9 @@ config SYS_ARCH
 config USE_PRIVATE_LIBGCC
 	default y
 
+config SYS_VSNPRINTF
+	default y
+
 choice
 	prompt "Target select"
 
@@ -32,6 +35,20 @@ config TARGET_CHROMEBOOK_LINK
 	  and it provides a 2560x1700 high resolution touch-enabled LCD
 	  display.
 
+config TARGET_CHROMEBOX_PANTHER
+	bool "Support Chromebox panther (not available)"
+	select n
+	help
+	  Note: At present this must be used with Coreboot. See README.x86
+	  for instructions.
+
+	  This is the Asus Chromebox CN60 released in 2014. It uses an Intel
+	  Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
+	  Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also
+	  includes a USB SD reader, four USB3 ports, display port and HDMI
+	  video output and a 16GB SATA solid state drive. There is no Chrome
+	  OS EC on this model.
+
 config TARGET_CROWNBAY
 	bool "Support Intel Crown Bay CRB"
 	help
@@ -67,13 +84,10 @@ config TARGET_GALILEO
 
 endchoice
 
-config DM
-	default y
-
-config DM_GPIO
+config DM_SPI
 	default y
 
-config DM_SERIAL
+config DM_SPI_FLASH
 	default y
 
 config SYS_MALLOC_F_LEN
@@ -432,6 +446,8 @@ source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"
 
+source "board/google/chromebox_panther/Kconfig"
+
 source "board/intel/crownbay/Kconfig"
 
 source "board/intel/minnowmax/Kconfig"
@@ -452,4 +468,13 @@ config PCIE_ECAM_BASE
 	  assigned to PCI devices - i.e. the memory and prefetch regions, as
 	  passed to pci_set_region().
 
+config BOOTSTAGE
+	default y
+
+config BOOTSTAGE_REPORT
+	default y
+
+config CMD_BOOTSTAGE
+	default y
+
 endmenu
diff --git a/arch/x86/cpu/baytrail/early_uart.c b/arch/x86/cpu/baytrail/early_uart.c
index 4199210..b64a3a9 100644
--- a/arch/x86/cpu/baytrail/early_uart.c
+++ b/arch/x86/cpu/baytrail/early_uart.c
@@ -50,7 +50,7 @@ static void score_select_func(int pad, int func)
 	writel(reg, pconf0_addr);
 }
 
-static void pci_write_config32(int dev, unsigned int where, u32 value)
+static void x86_pci_write_config32(int dev, unsigned int where, u32 value)
 {
 	unsigned long addr;
 
@@ -62,7 +62,8 @@ static void pci_write_config32(int dev, unsigned int where, u32 value)
 int setup_early_uart(void)
 {
 	/* Enable the legacy UART hardware. */
-	pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT, 1);
+	x86_pci_write_config32(PCI_DEV_CONFIG(0, LPC_DEV, LPC_FUNC), UART_CONT,
+			       1);
 
 	/*
 	 * Set up the pads to the UART function. This allows the signals to
diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index c9983f1..fa415dd 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -10,58 +10,27 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-			      struct pci_config_table *table)
-{
-	u8 secondary;
-	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-	hose->last_busno = max(hose->last_busno, (int)secondary);
-	pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_coreboot_config_table[] = {
-	/* vendor, device, class, bus, dev, func */
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-	{}
+static const struct dm_pci_ops pci_x86_ops = {
+	.read_config	= pci_x86_read_config,
+	.write_config	= pci_x86_write_config,
 };
 
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-	hose->config_table = pci_coreboot_config_table;
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_PCI_MEM_BUS,
-		       CONFIG_PCI_MEM_PHYS,
-		       CONFIG_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_PCI_IO_BUS,
-		       CONFIG_PCI_IO_PHYS,
-		       CONFIG_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_PREF_BUS,
-		       CONFIG_PCI_PREF_PHYS,
-		       CONFIG_PCI_PREF_SIZE,
-		       PCI_REGION_PREFETCH);
-
-	pci_set_region(hose->regions + 3,
-		       0,
-		       0,
-		       gd->ram_size,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+static const struct udevice_id pci_x86_ids[] = {
+	{ .compatible = "pci-x86" },
+	{ }
+};
 
-	hose->region_count = 4;
-}
+U_BOOT_DRIVER(pci_x86_drv) = {
+	.name		= "pci_x86",
+	.id		= UCLASS_PCI,
+	.of_match	= pci_x86_ids,
+	.ops		= &pci_x86_ops,
+};
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c
index e98a230..9c3ab81 100644
--- a/arch/x86/cpu/coreboot/sdram.c
+++ b/arch/x86/cpu/coreboot/sdram.c
@@ -90,7 +90,8 @@ int dram_init(void)
 		struct memrange *memrange = &lib_sysinfo.memrange[i];
 		unsigned long long end = memrange->base + memrange->size;
 
-		if (memrange->type == CB_MEM_RAM && end > ram_size)
+		if (memrange->type == CB_MEM_RAM && end > ram_size &&
+		    memrange->base < (1ULL << 32))
 			ram_size = end;
 	}
 	gd->ram_size = ram_size;
@@ -108,7 +109,8 @@ void dram_init_banksize(void)
 		for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) {
 			struct memrange *memrange = &lib_sysinfo.memrange[i];
 
-			if (memrange->type == CB_MEM_RAM) {
+			if (memrange->type == CB_MEM_RAM &&
+			    memrange->base < (1ULL << 32)) {
 				gd->bd->bi_dram[j].start = memrange->base;
 				gd->bd->bi_dram[j].size = memrange->size;
 				j++;
diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index ed7905c..a9ca50b 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -163,7 +163,7 @@ void setup_gdt(gd_t *id, u64 *gdt_addr)
 int __weak x86_cleanup_before_linux(void)
 {
 #ifdef CONFIG_BOOTSTAGE_STASH
-	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH,
+	bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
 			CONFIG_BOOTSTAGE_STASH_SIZE);
 #endif
 
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index 65a17d3..ca8cccf 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
@@ -22,36 +23,36 @@ void bd82x6x_pci_init(pci_dev_t dev)
 
 	debug("bd82x6x PCI init.\n");
 	/* Enable Bus Master */
-	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MASTER;
-	pci_write_config16(dev, PCI_COMMAND, reg16);
+	x86_pci_write_config16(dev, PCI_COMMAND, reg16);
 
 	/* This device has no interrupt */
-	pci_write_config8(dev, INTR, 0xff);
+	x86_pci_write_config8(dev, INTR, 0xff);
 
 	/* disable parity error response and SERR */
-	reg16 = pci_read_config16(dev, BCTRL);
+	reg16 = x86_pci_read_config16(dev, BCTRL);
 	reg16 &= ~(1 << 0);
 	reg16 &= ~(1 << 1);
-	pci_write_config16(dev, BCTRL, reg16);
+	x86_pci_write_config16(dev, BCTRL, reg16);
 
 	/* Master Latency Count must be set to 0x04! */
-	reg8 = pci_read_config8(dev, SMLT);
+	reg8 = x86_pci_read_config8(dev, SMLT);
 	reg8 &= 0x07;
 	reg8 |= (0x04 << 3);
-	pci_write_config8(dev, SMLT, reg8);
+	x86_pci_write_config8(dev, SMLT, reg8);
 
 	/* Will this improve throughput of bus masters? */
-	pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+	x86_pci_write_config8(dev, PCI_MIN_GNT, 0x06);
 
 	/* Clear errors in status registers */
-	reg16 = pci_read_config16(dev, PSTS);
+	reg16 = x86_pci_read_config16(dev, PSTS);
 	/* reg16 |= 0xf900; */
-	pci_write_config16(dev, PSTS, reg16);
+	x86_pci_write_config16(dev, PSTS, reg16);
 
-	reg16 = pci_read_config16(dev, SECSTS);
+	reg16 = x86_pci_read_config16(dev, SECSTS);
 	/* reg16 |= 0xf900; */
-	pci_write_config16(dev, SECSTS, reg16);
+	x86_pci_write_config16(dev, SECSTS, reg16);
 }
 
 #define PCI_BRIDGE_UPDATE_COMMAND
@@ -59,7 +60,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
 {
 	uint16_t command;
 
-	command = pci_read_config16(dev, PCI_COMMAND);
+	command = x86_pci_read_config16(dev, PCI_COMMAND);
 	command |= PCI_COMMAND_IO;
 #ifdef PCI_BRIDGE_UPDATE_COMMAND
 	/*
@@ -67,7 +68,7 @@ void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
 	 * ROM and APICs to become invisible.
 	 */
 	debug("%x cmd <- %02x\n", dev, command);
-	pci_write_config16(dev, PCI_COMMAND, command);
+	x86_pci_write_config16(dev, PCI_COMMAND, command);
 #else
 	printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
 #endif
@@ -77,16 +78,16 @@ void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
 {
 	uint16_t ctrl;
 
-	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+	ctrl = x86_pci_read_config16(dev, PCI_BRIDGE_CONTROL);
 	ctrl |= PCI_COMMAND_IO;
 	ctrl |= PCI_BRIDGE_CTL_VGA;
 	debug("%x bridge ctrl <- %04x\n", dev, ctrl);
-	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+	x86_pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
 
 	bd82x6x_pci_dev_enable_resources(dev);
 }
 
-int bd82x6x_init_pci_devices(void)
+static int bd82x6x_probe(struct udevice *dev)
 {
 	const void *blob = gd->fdt_blob;
 	struct pci_controller *hose;
@@ -144,3 +145,15 @@ int bd82x6x_init(void)
 
 	return 0;
 }
+
+static const struct udevice_id bd82x6x_ids[] = {
+	{ .compatible = "intel,bd82x6x" },
+	{ }
+};
+
+U_BOOT_DRIVER(bd82x6x_drv) = {
+	.name		= "bd82x6x",
+	.id		= UCLASS_PCH,
+	.of_match	= bd82x6x_ids,
+	.probe		= bd82x6x_probe,
+};
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index e925310..37f3731 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <asm/cpu.h>
@@ -116,23 +117,32 @@ static void set_spi_speed(void)
 
 int arch_cpu_init(void)
 {
+	post_code(POST_CPU_INIT);
+	timer_set_base(rdtsc());
+
+	return x86_cpu_init_f();
+}
+
+int arch_cpu_init_dm(void)
+{
 	const void *blob = gd->fdt_blob;
 	struct pci_controller *hose;
+	struct udevice *bus;
 	int node;
 	int ret;
 
-	post_code(POST_CPU_INIT);
-	timer_set_base(rdtsc());
-
-	ret = x86_cpu_init_f();
+	post_code(0x70);
+	ret = uclass_get_device(UCLASS_PCI, 0, &bus);
+	post_code(0x71);
 	if (ret)
 		return ret;
+	post_code(0x72);
+	hose = dev_get_uclass_priv(bus);
 
-	ret = pci_early_init_hose(&hose);
-	if (ret)
-		return ret;
+	/* TODO(sjg@chromium.org): Get rid of gd->hose */
+	gd->hose = hose;
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
 	if (node < 0)
 		return -ENOENT;
 	ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
@@ -167,21 +177,21 @@ static int enable_smbus(void)
 	dev = PCI_BDF(0x0, 0x1f, 0x3);
 
 	/* Check to make sure we've got the right device. */
-	value = pci_read_config16(dev, 0x0);
+	value = x86_pci_read_config16(dev, 0x0);
 	if (value != 0x8086) {
 		printf("SMBus controller not found\n");
 		return -ENOSYS;
 	}
 
 	/* Set SMBus I/O base. */
-	pci_write_config32(dev, SMB_BASE,
-			   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+	x86_pci_write_config32(dev, SMB_BASE,
+			       SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 
 	/* Set SMBus enable. */
-	pci_write_config8(dev, HOSTC, HST_EN);
+	x86_pci_write_config8(dev, HOSTC, HST_EN);
 
 	/* Set SMBus I/O space enable. */
-	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+	x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
 
 	/* Disable interrupt generation. */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
@@ -214,25 +224,25 @@ static void enable_usb_bar(void)
 	u32 cmd;
 
 	/* USB Controller 1 */
-	pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
-			   PCH_EHCI0_TEMP_BAR0);
-	cmd = pci_read_config32(usb0, PCI_COMMAND);
+	x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+			       PCH_EHCI0_TEMP_BAR0);
+	cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb0, PCI_COMMAND, cmd);
+	x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
 
 	/* USB Controller 1 */
-	pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
-			   PCH_EHCI1_TEMP_BAR0);
-	cmd = pci_read_config32(usb1, PCI_COMMAND);
+	x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+			       PCH_EHCI1_TEMP_BAR0);
+	cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb1, PCI_COMMAND, cmd);
+	x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
 
 	/* USB3 Controller */
-	pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
-			   PCH_XHCI_TEMP_BAR0);
-	cmd = pci_read_config32(usb3, PCI_COMMAND);
+	x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+			       PCH_XHCI_TEMP_BAR0);
+	cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
 	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config32(usb3, PCI_COMMAND, cmd);
+	x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
 }
 
 static int report_bist_failure(void)
@@ -320,8 +330,8 @@ int print_cpuinfo(void)
 	gd->arch.pei_boot_mode = boot_mode;
 
 	/* TODO: Move this to the board or driver */
-	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-	pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+	x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c
index eb8f613..9ca008e 100644
--- a/arch/x86/cpu/ivybridge/early_init.c
+++ b/arch/x86/cpu/ivybridge/early_init.c
@@ -17,10 +17,10 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
 {
 	/* Setting up Southbridge. In the northbridge code. */
 	debug("Setting up static southbridge registers\n");
-	pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
+	x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
 
-	pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
-	pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
+	x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1);
+	x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */
 
 	debug("Disabling watchdog reboot\n");
 	setbits_le32(RCB_REG(GCS), 1 >> 5);	/* No reset */
@@ -28,25 +28,27 @@ static void sandybridge_setup_bars(pci_dev_t pch_dev, pci_dev_t lpc_dev)
 
 	/* Set up all hardcoded northbridge BARs */
 	debug("Setting up static registers\n");
-	pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
-	pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
-	pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
-	pci_write_config32(pch_dev, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32);
+	x86_pci_write_config32(pch_dev, EPBAR, DEFAULT_EPBAR | 1);
+	x86_pci_write_config32(pch_dev, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32);
+	x86_pci_write_config32(pch_dev, MCHBAR, DEFAULT_MCHBAR | 1);
+	x86_pci_write_config32(pch_dev, MCHBAR + 4,
+			       (0LL + DEFAULT_MCHBAR) >> 32);
 	/* 64MB - busses 0-63 */
-	pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
-	pci_write_config32(pch_dev, PCIEXBAR + 4,
-			   (0LL + DEFAULT_PCIEXBAR) >> 32);
-	pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
-	pci_write_config32(pch_dev, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32);
+	x86_pci_write_config32(pch_dev, PCIEXBAR, DEFAULT_PCIEXBAR | 5);
+	x86_pci_write_config32(pch_dev, PCIEXBAR + 4,
+			       (0LL + DEFAULT_PCIEXBAR) >> 32);
+	x86_pci_write_config32(pch_dev, DMIBAR, DEFAULT_DMIBAR | 1);
+	x86_pci_write_config32(pch_dev, DMIBAR + 4,
+			       (0LL + DEFAULT_DMIBAR) >> 32);
 
 	/* Set C0000-FFFFF to access RAM on both reads and writes */
-	pci_write_config8(pch_dev, PAM0, 0x30);
-	pci_write_config8(pch_dev, PAM1, 0x33);
-	pci_write_config8(pch_dev, PAM2, 0x33);
-	pci_write_config8(pch_dev, PAM3, 0x33);
-	pci_write_config8(pch_dev, PAM4, 0x33);
-	pci_write_config8(pch_dev, PAM5, 0x33);
-	pci_write_config8(pch_dev, PAM6, 0x33);
+	x86_pci_write_config8(pch_dev, PAM0, 0x30);
+	x86_pci_write_config8(pch_dev, PAM1, 0x33);
+	x86_pci_write_config8(pch_dev, PAM2, 0x33);
+	x86_pci_write_config8(pch_dev, PAM3, 0x33);
+	x86_pci_write_config8(pch_dev, PAM4, 0x33);
+	x86_pci_write_config8(pch_dev, PAM5, 0x33);
+	x86_pci_write_config8(pch_dev, PAM6, 0x33);
 }
 
 static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
@@ -55,7 +57,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
 	u16 reg16;
 	u8 reg8;
 
-	reg16 = pci_read_config16(video_dev, PCI_DEVICE_ID);
+	reg16 = x86_pci_read_config16(video_dev, PCI_DEVICE_ID);
 	switch (reg16) {
 	case 0x0102: /* GT1 Desktop */
 	case 0x0106: /* GT1 Mobile */
@@ -75,7 +77,7 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
 	debug("Initialising Graphics\n");
 
 	/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
-	reg16 = pci_read_config16(pch_dev, GGC);
+	reg16 = x86_pci_read_config16(pch_dev, GGC);
 	reg16 &= ~0x00f8;
 	reg16 |= 1 << 3;
 	/* Program GTT memory by setting GGC[9:8] = 2MB */
@@ -83,13 +85,13 @@ static void sandybridge_setup_graphics(pci_dev_t pch_dev, pci_dev_t video_dev)
 	reg16 |= 2 << 8;
 	/* Enable VGA decode */
 	reg16 &= ~0x0002;
-	pci_write_config16(pch_dev, GGC, reg16);
+	x86_pci_write_config16(pch_dev, GGC, reg16);
 
 	/* Enable 256MB aperture */
-	reg8 = pci_read_config8(video_dev, MSAC);
+	reg8 = x86_pci_read_config8(video_dev, MSAC);
 	reg8 &= ~0x06;
 	reg8 |= 0x02;
-	pci_write_config8(video_dev, MSAC, reg8);
+	x86_pci_write_config8(video_dev, MSAC, reg8);
 
 	/* Erratum workarounds */
 	reg32 = readl(MCHBAR_REG(0x5f00));
@@ -124,22 +126,22 @@ void sandybridge_early_init(int chipset_type)
 	u8 reg8;
 
 	/* Device ID Override Enable should be done very early */
-	capid0_a = pci_read_config32(pch_dev, 0xe4);
+	capid0_a = x86_pci_read_config32(pch_dev, 0xe4);
 	if (capid0_a & (1 << 10)) {
-		reg8 = pci_read_config8(pch_dev, 0xf3);
+		reg8 = x86_pci_read_config8(pch_dev, 0xf3);
 		reg8 &= ~7; /* Clear 2:0 */
 
 		if (chipset_type == SANDYBRIDGE_MOBILE)
 			reg8 |= 1; /* Set bit 0 */
 
-		pci_write_config8(pch_dev, 0xf3, reg8);
+		x86_pci_write_config8(pch_dev, 0xf3, reg8);
 	}
 
 	/* Setup all BARs required for early PCIe and raminit */
 	sandybridge_setup_bars(pch_dev, lpc_dev);
 
 	/* Device Enable */
-	pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
+	x86_pci_write_config32(pch_dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
 
 	sandybridge_setup_graphics(pch_dev, video_dev);
 }
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
index b24dea1..356bbb4 100644
--- a/arch/x86/cpu/ivybridge/early_me.c
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -29,7 +29,7 @@ static inline void pci_read_dword_ptr(void *ptr, int offset)
 {
 	u32 dword;
 
-	dword = pci_read_config32(PCH_ME_DEV, offset);
+	dword = x86_pci_read_config32(PCH_ME_DEV, offset);
 	memcpy(ptr, &dword, sizeof(dword));
 }
 
@@ -37,7 +37,7 @@ static inline void pci_write_dword_ptr(void *ptr, int offset)
 {
 	u32 dword = 0;
 	memcpy(&dword, ptr, sizeof(dword));
-	pci_write_config32(PCH_ME_DEV, offset, dword);
+	x86_pci_write_config32(PCH_ME_DEV, offset, dword);
 }
 
 void intel_early_me_status(void)
@@ -101,7 +101,7 @@ static inline void set_global_reset(int enable)
 {
 	u32 etr3;
 
-	etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+	etr3 = x86_pci_read_config32(PCH_LPC_DEV, ETR3);
 
 	/* Clear CF9 Without Resume Well Reset Enable */
 	etr3 &= ~ETR3_CWORWRE;
@@ -112,7 +112,7 @@ static inline void set_global_reset(int enable)
 	else
 		etr3 &= ~ETR3_CF9GR;
 
-	pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+	x86_pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
 }
 
 int intel_early_me_init_done(u8 status)
@@ -127,8 +127,8 @@ int intel_early_me_init_done(u8 status)
 	};
 
 	/* MEBASE from MESEG_BASE[35:20] */
-	mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
-	mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
+	mebase_l = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
+	mebase_h = x86_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
 	mebase_h &= 0xf;
 	did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
 
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
index 821ea25..ea169b0 100644
--- a/arch/x86/cpu/ivybridge/gma.c
+++ b/arch/x86/cpu/ivybridge/gma.c
@@ -741,9 +741,9 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
 	int ret;
 
 	/* IGD needs to be Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	x86_pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	/* Use write-combining for the graphics memory, 256MB */
 	base = pci_read_bar32(hose, dev, 2);
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index 43fdd31..bc1a0f0 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <rtc.h>
@@ -29,7 +30,7 @@ static int pch_enable_apic(pci_dev_t dev)
 	int i;
 
 	/* Enable ACPI I/O and power management. Set SCI IRQ to IRQ9 */
-	pci_write_config8(dev, ACPI_CNTL, 0x80);
+	x86_pci_write_config8(dev, ACPI_CNTL, 0x80);
 
 	writel(0, IO_APIC_INDEX);
 	writel(1 << 25, IO_APIC_DATA);
@@ -72,9 +73,9 @@ static void pch_enable_serial_irqs(pci_dev_t dev)
 	/* Set packet length and toggle silent mode bit for one frame. */
 	value = (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0);
 #ifdef CONFIG_SERIRQ_CONTINUOUS_MODE
-	pci_write_config8(dev, SERIRQ_CNTL, value);
+	x86_pci_write_config8(dev, SERIRQ_CNTL, value);
 #else
-	pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
+	x86_pci_write_config8(dev, SERIRQ_CNTL, value | (1 << 6));
 #endif
 }
 
@@ -86,15 +87,15 @@ static int pch_pirq_init(const void *blob, int node, pci_dev_t dev)
 				  sizeof(route)))
 		return -EINVAL;
 	ptr = route;
-	pci_write_config8(dev, PIRQA_ROUT, *ptr++);
-	pci_write_config8(dev, PIRQB_ROUT, *ptr++);
-	pci_write_config8(dev, PIRQC_ROUT, *ptr++);
-	pci_write_config8(dev, PIRQD_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQA_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQB_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQC_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQD_ROUT, *ptr++);
 
-	pci_write_config8(dev, PIRQE_ROUT, *ptr++);
-	pci_write_config8(dev, PIRQF_ROUT, *ptr++);
-	pci_write_config8(dev, PIRQG_ROUT, *ptr++);
-	pci_write_config8(dev, PIRQH_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQE_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQF_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQG_ROUT, *ptr++);
+	x86_pci_write_config8(dev, PIRQH_ROUT, *ptr++);
 
 	/*
 	 * TODO(sjg@chromium.org): U-Boot does not set up the interrupts
@@ -116,7 +117,7 @@ static int pch_gpi_routing(const void *blob, int node, pci_dev_t dev)
 	for (reg = 0, gpi = 0; gpi < ARRAY_SIZE(route); gpi++)
 		reg |= route[gpi] << (gpi * 2);
 
-	pci_write_config32(dev, 0xb8, reg);
+	x86_pci_write_config32(dev, 0xb8, reg);
 
 	return 0;
 }
@@ -141,7 +142,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
 	 */
 	pwr_on = MAINBOARD_POWER_ON;
 
-	reg16 = pci_read_config16(dev, GEN_PMCON_3);
+	reg16 = x86_pci_read_config16(dev, GEN_PMCON_3);
 	reg16 &= 0xfffe;
 	switch (pwr_on) {
 	case MAINBOARD_POWER_OFF:
@@ -168,7 +169,7 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
 
 	reg16 |= (1 << 12);	/* Disable SLP stretch after SUS well */
 
-	pci_write_config16(dev, GEN_PMCON_3, reg16);
+	x86_pci_write_config16(dev, GEN_PMCON_3, reg16);
 	debug("Set power %s after power failure.\n", state);
 
 	/* Set up NMI on errors. */
@@ -192,21 +193,21 @@ static int pch_power_options(const void *blob, int node, pci_dev_t dev)
 	outb(reg8, 0x70);
 
 	/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
-	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
 	reg16 &= ~(3 << 0);	/* SMI# rate 1 minute */
 	reg16 &= ~(1 << 10);	/* Disable BIOS_PCI_EXP_EN for native PME */
 #if DEBUG_PERIODIC_SMIS
 	/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using periodic SMIs */
 	reg16 |= (3 << 0);	/* Periodic SMI every 8s */
 #endif
-	pci_write_config16(dev, GEN_PMCON_1, reg16);
+	x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
 
 	/* Set the board's GPI routing. */
 	ret = pch_gpi_routing(blob, node, dev);
 	if (ret)
 		return ret;
 
-	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+	pmbase = x86_pci_read_config16(dev, 0x40) & 0xfffe;
 
 	writel(pmbase + GPE0_EN, fdtdec_get_int(blob, node,
 						"intel,gpe0-enable", 0));
@@ -231,11 +232,11 @@ static void pch_rtc_init(pci_dev_t dev)
 	int rtc_failed;
 	u8 reg8;
 
-	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	reg8 = x86_pci_read_config8(dev, GEN_PMCON_3);
 	rtc_failed = reg8 & RTC_BATTERY_DEAD;
 	if (rtc_failed) {
 		reg8 &= ~RTC_BATTERY_DEAD;
-		pci_write_config8(dev, GEN_PMCON_3, reg8);
+		x86_pci_write_config8(dev, GEN_PMCON_3, reg8);
 	}
 	debug("rtc_failed = 0x%x\n", rtc_failed);
 
@@ -258,7 +259,7 @@ static void pch_rtc_init(pci_dev_t dev)
 static void cpt_pm_init(pci_dev_t dev)
 {
 	debug("CougarPoint PM init\n");
-	pci_write_config8(dev, 0xa9, 0x47);
+	x86_pci_write_config8(dev, 0xa9, 0x47);
 	setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0));
 
 	setbits_le32(RCB_REG(0x228c), 1 << 0);
@@ -302,7 +303,7 @@ static void cpt_pm_init(pci_dev_t dev)
 static void ppt_pm_init(pci_dev_t dev)
 {
 	debug("PantherPoint PM init\n");
-	pci_write_config8(dev, 0xa9, 0x47);
+	x86_pci_write_config8(dev, 0xa9, 0x47);
 	setbits_le32(RCB_REG(0x2238), 1 << 0);
 	setbits_le32(RCB_REG(0x228c), 1 << 0);
 	setbits_le16(RCB_REG(0x1100), (1 << 13) | (1 << 14));
@@ -356,9 +357,9 @@ static void enable_clock_gating(pci_dev_t dev)
 
 	setbits_le32(RCB_REG(0x2234), 0xf);
 
-	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 = x86_pci_read_config16(dev, GEN_PMCON_1);
 	reg16 |= (1 << 2) | (1 << 11);
-	pci_write_config16(dev, GEN_PMCON_1, reg16);
+	x86_pci_write_config16(dev, GEN_PMCON_1, reg16);
 
 	pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
 	pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
@@ -412,15 +413,15 @@ static void pch_lock_smm(pci_dev_t dev)
 #if TEST_SMM_FLASH_LOCKDOWN
 	/* Now try this: */
 	debug("Locking BIOS to RO... ");
-	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	reg8 = x86_pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
 	debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
 	      (reg8 & 1) ? "rw" : "ro");
 	reg8 &= ~(1 << 0);			/* clear BIOSWE */
-	pci_write_config8(dev, 0xdc, reg8);
+	x86_pci_write_config8(dev, 0xdc, reg8);
 	reg8 |= (1 << 1);			/* set BLE */
-	pci_write_config8(dev, 0xdc, reg8);
+	x86_pci_write_config8(dev, 0xdc, reg8);
 	debug("ok.\n");
-	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	reg8 = x86_pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
 	debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
 	      (reg8 & 1) ? "rw" : "ro");
 
@@ -428,9 +429,9 @@ static void pch_lock_smm(pci_dev_t dev)
 	writeb(0, 0xfff00000);
 	debug("Testing:\n");
 	reg8 |= (1 << 0);			/* set BIOSWE */
-	pci_write_config8(dev, 0xdc, reg8);
+	x86_pci_write_config8(dev, 0xdc, reg8);
 
-	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	reg8 = x86_pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
 	debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
 	      (reg8 & 1) ? "rw" : "ro");
 	debug("Done.\n");
@@ -443,9 +444,9 @@ static void pch_disable_smm_only_flashing(pci_dev_t dev)
 	u8 reg8;
 
 	debug("Enabling BIOS updates outside of SMM... ");
-	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	reg8 = x86_pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
 	reg8 &= ~(1 << 5);
-	pci_write_config8(dev, 0xdc, reg8);
+	x86_pci_write_config8(dev, 0xdc, reg8);
 }
 
 static void pch_fixups(pci_dev_t dev)
@@ -453,9 +454,9 @@ static void pch_fixups(pci_dev_t dev)
 	u8 gen_pmcon_2;
 
 	/* Indicate DRAM init done for MRC S3 to know it can resume */
-	gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
+	gen_pmcon_2 = x86_pci_read_config8(dev, GEN_PMCON_2);
 	gen_pmcon_2 |= (1 << 7);
-	pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+	x86_pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
 
 	/* Enable DMI ASPM in the PCH */
 	clrbits_le32(RCB_REG(0x2304), 1 << 10);
@@ -478,10 +479,10 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
 		return -EINVAL;
 
 	/* Set COM1/COM2 decode range */
-	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+	x86_pci_write_config16(dev, LPC_IO_DEC, 0x0010);
 
 	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
-	pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+	x86_pci_write_config16(dev, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
 			   GAMEL_LPC_EN | COMA_LPC_EN);
 
 	/* Write all registers but use 0 if we run out of data */
@@ -491,7 +492,7 @@ int lpc_early_init(const void *blob, int node, pci_dev_t dev)
 
 		if (i < count)
 			reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16);
-		pci_write_config32(dev, LPC_GENX_DEC(i), reg);
+		x86_pci_write_config32(dev, LPC_GENX_DEC(i), reg);
 	}
 
 	return 0;
@@ -509,12 +510,12 @@ int lpc_init(struct pci_controller *hose, pci_dev_t dev)
 	pci_write_bar32(hose, dev, 3, 0x800);
 	pci_write_bar32(hose, dev, 4, 0x900);
 
-	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
 	if (node < 0)
 		return -ENOENT;
 
 	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+	x86_pci_write_config16(dev, PCI_COMMAND, 0x000f);
 
 	/* IO APIC initialization. */
 	pch_enable_apic(dev);
@@ -567,3 +568,14 @@ void lpc_enable(pci_dev_t dev)
 	writew(0x0010, RCB_REG(DISPBDF));
 	setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
 }
+
+static const struct udevice_id bd82x6x_lpc_ids[] = {
+	{ .compatible = "intel,bd82x6x-lpc" },
+	{ }
+};
+
+U_BOOT_DRIVER(bd82x6x_lpc_drv) = {
+	.name		= "lpc",
+	.id		= UCLASS_LPC,
+	.of_match	= bd82x6x_lpc_ids,
+};
diff --git a/arch/x86/cpu/ivybridge/mrccache.c b/arch/x86/cpu/ivybridge/mrccache.c
index 0f1a64b..9205494 100644
--- a/arch/x86/cpu/ivybridge/mrccache.c
+++ b/arch/x86/cpu/ivybridge/mrccache.c
@@ -105,7 +105,7 @@ static struct mrc_data_container *find_next_mrc_cache(struct fmap_entry *entry,
 	return cache;
 }
 
-int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry,
+int mrccache_update(struct udevice *sf, struct fmap_entry *entry,
 		    struct mrc_data_container *cur)
 {
 	struct mrc_data_container *cache;
@@ -135,7 +135,7 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry,
 		debug("Erasing the MRC cache region of %x bytes at %x\n",
 		      entry->length, entry->offset);
 
-		ret = spi_flash_erase(sf, entry->offset, entry->length);
+		ret = spi_flash_erase_dm(sf, entry->offset, entry->length);
 		if (ret) {
 			debug("Failed to erase flash region\n");
 			return ret;
@@ -146,7 +146,8 @@ int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry,
 	/* Write the data out */
 	offset = (ulong)cache - base_addr + entry->offset;
 	debug("Write MRC cache update to flash at %lx\n", offset);
-	ret = spi_flash_write(sf, offset, cur->data_size + sizeof(*cur), cur);
+	ret = spi_flash_write_dm(sf, offset, cur->data_size + sizeof(*cur),
+				 cur);
 	if (ret) {
 		debug("Failed to write to SPI flash\n");
 		return ret;
diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c
index c50b5de..e95e60e 100644
--- a/arch/x86/cpu/ivybridge/northbridge.c
+++ b/arch/x86/cpu/ivybridge/northbridge.c
@@ -30,7 +30,7 @@ int bridge_silicon_revision(void)
 		result = cpuid(1);
 		stepping = result.eax & 0xf;
 		dev = PCI_BDF(0, 0, 0);
-		bridge_id = pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
+		bridge_id = x86_pci_read_config16(dev, PCI_DEVICE_ID) & 0xf0;
 		bridge_revision_id = bridge_id | stepping;
 	}
 
@@ -55,7 +55,7 @@ static int get_pcie_bar(u32 *base, u32 *len)
 	*base = 0;
 	*len = 0;
 
-	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+	pciexbar_reg = x86_pci_read_config32(dev, PCIEXBAR);
 
 	if (!(pciexbar_reg & (1 << 0)))
 		return 0;
@@ -170,7 +170,7 @@ void northbridge_init(pci_dev_t dev)
 void northbridge_enable(pci_dev_t dev)
 {
 #if CONFIG_HAVE_ACPI_RESUME
-	switch (pci_read_config32(dev, SKPAD)) {
+	switch (x86_pci_read_config32(dev, SKPAD)) {
 	case 0xcafebabe:
 		debug("Normal boot.\n");
 		apci_set_slp_type(0);
diff --git a/arch/x86/cpu/ivybridge/pch.c b/arch/x86/cpu/ivybridge/pch.c
index fa04d48..bbab646 100644
--- a/arch/x86/cpu/ivybridge/pch.c
+++ b/arch/x86/cpu/ivybridge/pch.c
@@ -21,7 +21,7 @@ int pch_silicon_revision(void)
 	dev = PCH_LPC_DEV;
 
 	if (pch_revision_id < 0)
-		pch_revision_id = pci_read_config8(dev, PCI_REVISION_ID);
+		pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
 	return pch_revision_id;
 }
 
@@ -32,7 +32,7 @@ int pch_silicon_type(void)
 	dev = PCH_LPC_DEV;
 
 	if (pch_type < 0)
-		pch_type = pci_read_config8(dev, PCI_DEVICE_ID + 1);
+		pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1);
 	return pch_type;
 }
 
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
index 452d1c3..5e90f30 100644
--- a/arch/x86/cpu/ivybridge/pci.c
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -10,69 +10,30 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <pci.h>
 #include <asm/pci.h>
+#include <asm/post.h>
 #include <asm/arch/bd82x6x.h>
 #include <asm/arch/pch.h>
 
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-			      struct pci_config_table *table)
-{
-	u8 secondary;
-
-	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-	if (secondary != 0)
-		pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_ivybridge_config_table[] = {
-	/* vendor, device, class, bus, dev, func */
-	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-	{}
-};
-
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-	hose->config_table = pci_ivybridge_config_table;
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		       CONFIG_PCI_MEM_BUS,
-		       CONFIG_PCI_MEM_PHYS,
-		       CONFIG_PCI_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		       CONFIG_PCI_IO_BUS,
-		       CONFIG_PCI_IO_PHYS,
-		       CONFIG_PCI_IO_SIZE,
-		       PCI_REGION_IO);
-
-	pci_set_region(hose->regions + 2,
-		       CONFIG_PCI_PREF_BUS,
-		       CONFIG_PCI_PREF_PHYS,
-		       CONFIG_PCI_PREF_SIZE,
-		       PCI_REGION_PREFETCH);
-
-	hose->region_count = 3;
-}
-
-int board_pci_pre_scan(struct pci_controller *hose)
+static int pci_ivybridge_probe(struct udevice *bus)
 {
+	struct pci_controller *hose = dev_get_uclass_priv(bus);
 	pci_dev_t dev;
 	u16 reg16;
 
+	if (!(gd->flags & GD_FLG_RELOC))
+		return 0;
+	post_code(0x50);
 	bd82x6x_init();
+	post_code(0x51);
 
 	reg16 = 0xff;
 	dev = PCH_DEV;
-	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config16(dev, PCI_COMMAND, reg16);
+	x86_pci_write_config16(dev, PCI_COMMAND, reg16);
 
 	/*
 	* Clear non-reserved bits in status register.
@@ -82,19 +43,25 @@ int board_pci_pre_scan(struct pci_controller *hose)
 	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 
 	pci_write_bar32(hose, dev, 0, 0xf0000000);
+	post_code(0x52);
 
 	return 0;
 }
 
-int board_pci_post_scan(struct pci_controller *hose)
-{
-	int ret;
+static const struct dm_pci_ops pci_ivybridge_ops = {
+	.read_config	= pci_x86_read_config,
+	.write_config	= pci_x86_write_config,
+};
 
-	ret = bd82x6x_init_pci_devices();
-	if (ret) {
-		printf("bd82x6x_init_pci_devices() failed: %d\n", ret);
-		return ret;
-	}
+static const struct udevice_id pci_ivybridge_ids[] = {
+	{ .compatible = "intel,pci-ivybridge" },
+	{ }
+};
 
-	return 0;
-}
+U_BOOT_DRIVER(pci_ivybridge_drv) = {
+	.name		= "pci_ivybridge",
+	.id		= UCLASS_PCI,
+	.of_match	= pci_ivybridge_ids,
+	.ops		= &pci_ivybridge_ops,
+	.probe		= pci_ivybridge_probe,
+};
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c
index 69e31b3..4493870 100644
--- a/arch/x86/cpu/ivybridge/report_platform.c
+++ b/arch/x86/cpu/ivybridge/report_platform.c
@@ -70,14 +70,14 @@ static void report_pch_info(void)
 	u16 dev_id;
 	uint8_t rev_id;
 
-	dev_id = pci_read_config16(PCH_LPC_DEV, 2);
+	dev_id = x86_pci_read_config16(PCH_LPC_DEV, 2);
 	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
 		if (pch_table[i].dev_id == dev_id) {
 			pch_type = pch_table[i].dev_name;
 			break;
 		}
 	}
-	rev_id = pci_read_config8(PCH_LPC_DEV, 8);
+	rev_id = x86_pci_read_config8(PCH_LPC_DEV, 8);
 	debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
 	      rev_id);
 }
diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c
index bbcd47d..e7bf03c 100644
--- a/arch/x86/cpu/ivybridge/sata.c
+++ b/arch/x86/cpu/ivybridge/sata.c
@@ -14,14 +14,14 @@
 
 static inline u32 sir_read(pci_dev_t dev, int idx)
 {
-	pci_write_config32(dev, SATA_SIRI, idx);
-	return pci_read_config32(dev, SATA_SIRD);
+	x86_pci_write_config32(dev, SATA_SIRI, idx);
+	return x86_pci_read_config32(dev, SATA_SIRD);
 }
 
 static inline void sir_write(pci_dev_t dev, int idx, u32 value)
 {
-	pci_write_config32(dev, SATA_SIRI, idx);
-	pci_write_config32(dev, SATA_SIRD, value);
+	x86_pci_write_config32(dev, SATA_SIRI, idx);
+	x86_pci_write_config32(dev, SATA_SIRD, value);
 }
 
 static void common_sata_init(pci_dev_t dev, unsigned int port_map)
@@ -31,17 +31,17 @@ static void common_sata_init(pci_dev_t dev, unsigned int port_map)
 
 	/* Set IDE I/O Configuration */
 	reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
-	pci_write_config32(dev, IDE_CONFIG, reg32);
+	x86_pci_write_config32(dev, IDE_CONFIG, reg32);
 
 	/* Port enable */
-	reg16 = pci_read_config16(dev, 0x92);
+	reg16 = x86_pci_read_config16(dev, 0x92);
 	reg16 &= ~0x3f;
 	reg16 |= port_map;
-	pci_write_config16(dev, 0x92, reg16);
+	x86_pci_write_config16(dev, 0x92, reg16);
 
 	/* SATA Initialization register */
 	port_map &= 0xff;
-	pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
+	x86_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
 }
 
 void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
@@ -60,7 +60,7 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
 				       "sata_interface_speed_support", 0);
 
 	/* Enable BARs */
-	pci_write_config16(dev, PCI_COMMAND, 0x0007);
+	x86_pci_write_config16(dev, PCI_COMMAND, 0x0007);
 
 	mode = fdt_getprop(blob, node, "intel,sata-mode", NULL);
 	if (!mode || !strcmp(mode, "ahci")) {
@@ -69,18 +69,18 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
 		debug("SATA: Controller in AHCI mode\n");
 
 		/* Set Interrupt Line, Interrupt Pin is set by D31IP.PIP */
-		pci_write_config8(dev, INTR_LN, 0x0a);
+		x86_pci_write_config8(dev, INTR_LN, 0x0a);
 
 		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+		x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+		x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
 
 		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+		x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+		x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
 
 		common_sata_init(dev, 0x8000 | port_map);
 
@@ -115,22 +115,22 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
 		/* No AHCI: clear AHCI base */
 		pci_write_bar32(hose, dev, 5, 0x00000000);
 		/* And without AHCI BAR no memory decoding */
-		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
 		reg16 &= ~PCI_COMMAND_MEMORY;
-		pci_write_config16(dev, PCI_COMMAND, reg16);
+		x86_pci_write_config16(dev, PCI_COMMAND, reg16);
 
-		pci_write_config8(dev, 0x09, 0x80);
+		x86_pci_write_config8(dev, 0x09, 0x80);
 
 		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+		x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+		x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
 
 		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+		x86_pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+		x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
 
 		common_sata_init(dev, port_map);
 	} else {
@@ -140,31 +140,32 @@ void bd82x6x_sata_init(pci_dev_t dev, const void *blob, int node)
 		pci_write_bar32(hose, dev, 5, 0x00000000);
 
 		/* And without AHCI BAR no memory decoding */
-		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 = x86_pci_read_config16(dev, PCI_COMMAND);
 		reg16 &= ~PCI_COMMAND_MEMORY;
-		pci_write_config16(dev, PCI_COMMAND, reg16);
+		x86_pci_write_config16(dev, PCI_COMMAND, reg16);
 
 		/*
 		 * Native mode capable on both primary and secondary (0xa)
 		 * OR'ed with enabled (0x50) = 0xf
 		 */
-		pci_write_config8(dev, 0x09, 0x8f);
+		x86_pci_write_config8(dev, 0x09, 0x8f);
 
 		/* Set Interrupt Line */
 		/* Interrupt Pin is set by D31IP.PIP */
-		pci_write_config8(dev, INTR_LN, 0xff);
+		x86_pci_write_config8(dev, INTR_LN, 0xff);
 
 		/* Set timings */
-		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+		x86_pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
 				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
 				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
-		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+		x86_pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
 				IDE_SITRE | IDE_ISP_3_CLOCKS |
 				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
 
 		/* Sync DMA */
-		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
-		pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+		x86_pci_write_config16(dev, IDE_SDMA_CNT,
+				       IDE_SSDE0 | IDE_PSDE0);
+		x86_pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
 
 		common_sata_init(dev, port_map);
 	}
@@ -221,5 +222,5 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node)
 	port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0);
 
 	map |= (port_map ^ 0x3f) << 8;
-	pci_write_config16(dev, 0x90, map);
+	x86_pci_write_config16(dev, 0x90, map);
 }
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 766b385..9a6da37 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -89,11 +89,12 @@ void dram_init_banksize(void)
 	}
 }
 
-static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry)
+static int get_mrc_entry(struct udevice **devp, struct fmap_entry *entry)
 {
 	const void *blob = gd->fdt_blob;
 	int node, spi_node, mrc_node;
 	int upto;
+	int ret;
 
 	/* Find the flash chip within the SPI controller node */
 	upto = 0;
@@ -112,10 +113,13 @@ static int get_mrc_entry(struct spi_flash **sfp, struct fmap_entry *entry)
 	if (fdtdec_read_fmap_entry(blob, mrc_node, "rm-mrc-cache", entry))
 		return -EINVAL;
 
-	if (sfp) {
-		*sfp = spi_flash_probe_fdt(blob, node, spi_node);
-		if (!*sfp)
-			return -EBADF;
+	if (devp) {
+		debug("getting sf\n");
+		ret = uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node,
+						     devp);
+		debug("ret = %d\n", ret);
+		if (ret)
+			return ret;
 	}
 
 	return 0;
@@ -246,7 +250,7 @@ static int sdram_save_mrc_data(void)
 {
 	struct mrc_data_container *data;
 	struct fmap_entry entry;
-	struct spi_flash *sf;
+	struct udevice *sf;
 	int ret;
 
 	if (!gd->arch.mrc_output_len)
@@ -266,7 +270,6 @@ static int sdram_save_mrc_data(void)
 
 	free(data);
 err_data:
-	spi_flash_free(sf);
 err_entry:
 	if (ret)
 		debug("%s: Failed: %d\n", __func__, ret);
@@ -444,7 +447,7 @@ int sdram_initialise(struct pei_data *pei_data)
 	 * Send ME init done for SandyBridge here.  This is done inside the
 	 * SystemAgent binary on IvyBridge
 	 */
-	done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
+	done = x86_pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
 	done &= BASE_REV_MASK;
 	if (BASE_REV_SNB == done)
 		intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
@@ -615,24 +618,24 @@ static int sdram_find(pci_dev_t dev)
 	 */
 
 	/* Top of Upper Usable DRAM, including remap */
-	touud = pci_read_config32(dev, TOUUD+4);
+	touud = x86_pci_read_config32(dev, TOUUD+4);
 	touud <<= 32;
-	touud |= pci_read_config32(dev, TOUUD);
+	touud |= x86_pci_read_config32(dev, TOUUD);
 
 	/* Top of Lower Usable DRAM */
-	tolud = pci_read_config32(dev, TOLUD);
+	tolud = x86_pci_read_config32(dev, TOLUD);
 
 	/* Top of Memory - does not account for any UMA */
-	tom = pci_read_config32(dev, 0xa4);
+	tom = x86_pci_read_config32(dev, 0xa4);
 	tom <<= 32;
-	tom |= pci_read_config32(dev, 0xa0);
+	tom |= x86_pci_read_config32(dev, 0xa0);
 
 	debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
 
 	/* ME UMA needs excluding if total memory <4GB */
-	me_base = pci_read_config32(dev, 0x74);
+	me_base = x86_pci_read_config32(dev, 0x74);
 	me_base <<= 32;
-	me_base |= pci_read_config32(dev, 0x70);
+	me_base |= x86_pci_read_config32(dev, 0x70);
 
 	debug("MEBASE %llx\n", me_base);
 
@@ -650,7 +653,7 @@ static int sdram_find(pci_dev_t dev)
 	}
 
 	/* Graphics memory comes next */
-	ggc = pci_read_config16(dev, GGC);
+	ggc = x86_pci_read_config16(dev, GGC);
 	if (!(ggc & 2)) {
 		debug("IGD decoded, subtracting ");
 
@@ -670,7 +673,7 @@ static int sdram_find(pci_dev_t dev)
 	}
 
 	/* Calculate TSEG size from its base which must be below GTT */
-	tseg_base = pci_read_config32(dev, 0xb8);
+	tseg_base = x86_pci_read_config32(dev, 0xb8);
 	uma_size = (uma_memory_base - tseg_base) >> 10;
 	tomk -= uma_size;
 	uma_memory_base = tomk * 1024ULL;
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c
index 291c971..da11aee 100644
--- a/arch/x86/cpu/ivybridge/usb_ehci.c
+++ b/arch/x86/cpu/ivybridge/usb_ehci.c
@@ -20,10 +20,10 @@ void bd82x6x_usb_ehci_init(pci_dev_t dev)
 	writel(reg32, RCB_REG(0x35b0));
 
 	debug("EHCI: Setting up controller.. ");
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
 	reg32 |= PCI_COMMAND_MASTER;
 	/* reg32 |= PCI_COMMAND_SERR; */
-	pci_write_config32(dev, PCI_COMMAND, reg32);
+	x86_pci_write_config32(dev, PCI_COMMAND, reg32);
 
 	debug("done.\n");
 }
diff --git a/arch/x86/cpu/ivybridge/usb_xhci.c b/arch/x86/cpu/ivybridge/usb_xhci.c
index 4a32a7e..f77b804 100644
--- a/arch/x86/cpu/ivybridge/usb_xhci.c
+++ b/arch/x86/cpu/ivybridge/usb_xhci.c
@@ -16,17 +16,17 @@ void bd82x6x_usb_xhci_init(pci_dev_t dev)
 	debug("XHCI: Setting up controller.. ");
 
 	/* lock overcurrent map */
-	reg32 = pci_read_config32(dev, 0x44);
+	reg32 = x86_pci_read_config32(dev, 0x44);
 	reg32 |= 1;
-	pci_write_config32(dev, 0x44, reg32);
+	x86_pci_write_config32(dev, 0x44, reg32);
 
 	/* Enable clock gating */
-	reg32 = pci_read_config32(dev, 0x40);
+	reg32 = x86_pci_read_config32(dev, 0x40);
 	reg32 &= ~((1 << 20) | (1 << 21));
 	reg32 |= (1 << 19) | (1 << 18) | (1 << 17);
 	reg32 |= (1 << 10) | (1 << 9) | (1 << 8);
 	reg32 |= (1 << 31); /* lock */
-	pci_write_config32(dev, 0x40, reg32);
+	x86_pci_write_config32(dev, 0x40, reg32);
 
 	debug("done.\n");
 }
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index ab1aaaa..e23b233 100644
--- a/arch/x86/cpu/pci.c
+++ b/arch/x86/cpu/pci.c
@@ -10,9 +10,11 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <malloc.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -70,7 +72,7 @@ static struct pci_controller *get_hose(void)
 	return pci_bus_to_hose(0);
 }
 
-unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where)
 {
 	uint8_t value;
 
@@ -79,7 +81,7 @@ unsigned int pci_read_config8(pci_dev_t dev, unsigned where)
 	return value;
 }
 
-unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where)
 {
 	uint16_t value;
 
@@ -88,7 +90,7 @@ unsigned int pci_read_config16(pci_dev_t dev, unsigned where)
 	return value;
 }
 
-unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
+unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where)
 {
 	uint32_t value;
 
@@ -97,17 +99,55 @@ unsigned int pci_read_config32(pci_dev_t dev, unsigned where)
 	return value;
 }
 
-void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value)
 {
 	pci_hose_write_config_byte(get_hose(), dev, where, value);
 }
 
-void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value)
 {
 	pci_hose_write_config_word(get_hose(), dev, where, value);
 }
 
-void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
+void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value)
 {
 	pci_hose_write_config_dword(get_hose(), dev, where, value);
 }
+
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+			ulong *valuep, enum pci_size_t size)
+{
+	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+	switch (size) {
+	case PCI_SIZE_8:
+		*valuep = inb(PCI_REG_DATA + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		*valuep = inw(PCI_REG_DATA + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		*valuep = inl(PCI_REG_DATA);
+		break;
+	}
+
+	return 0;
+}
+
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+			 ulong value, enum pci_size_t size)
+{
+	outl(bdf | (offset & 0xfc) | PCI_CFG_EN, PCI_REG_ADDR);
+	switch (size) {
+	case PCI_SIZE_8:
+		outb(value, PCI_REG_DATA + (offset & 3));
+		break;
+	case PCI_SIZE_16:
+		outw(value, PCI_REG_DATA + (offset & 2));
+		break;
+	case PCI_SIZE_32:
+		outl(value, PCI_REG_DATA);
+		break;
+	}
+
+	return 0;
+}
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index 25edcf7..e4b19c2 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -30,9 +30,9 @@ static void unprotect_spi_flash(void)
 {
 	u32 bc;
 
-	bc = pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
+	bc = x86_pci_read_config32(QUARK_LEGACY_BRIDGE, 0xd8);
 	bc |= 0x1;	/* unprotect the flash */
-	pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
+	x86_pci_write_config32(QUARK_LEGACY_BRIDGE, 0xd8, bc);
 }
 
 static void quark_setup_bars(void)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 30ab725..b7236e7 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -16,9 +16,9 @@ static void unprotect_spi_flash(void)
 {
 	u32 bc;
 
-	bc = pci_read_config32(PCH_LPC_DEV, 0xd8);
+	bc = x86_pci_read_config32(PCH_LPC_DEV, 0xd8);
 	bc |= 0x1;	/* unprotect the flash */
-	pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
+	x86_pci_write_config32(PCH_LPC_DEV, 0xd8, bc);
 }
 
 int arch_cpu_init(void)
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 7a66133..431bbd8 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,4 +1,5 @@
 dtb-y += chromebook_link.dtb \
+	chromebox_panther.dtb \
 	crownbay.dtb \
 	galileo.dtb \
 	minnowmax.dtb
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index 45ada61..b450c3c 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -8,7 +8,7 @@
 	compatible = "google,link", "intel,celeron-ivybridge";
 
 	aliases {
-		spi0 = "/spi";
+		spi0 = "/pci/pch/spi";
 	};
 
 	config {
@@ -151,27 +151,14 @@
 		};
 	};
 
-	spi {
-		#address-cells = <1>;
-		#size-cells = <0>;
-		compatible = "intel,ich-spi";
-		spi-flash@0 {
-			#size-cells = <1>;
-			#address-cells = <1>;
-			reg = <0>;
-			compatible = "winbond,w25q64", "spi-flash";
-			memory-map = <0xff800000 0x00800000>;
-			rw-mrc-cache {
-				label = "rw-mrc-cache";
-				/* Alignment: 4k (for updating) */
-				reg = <0x003e0000 0x00010000>;
-				type = "wiped";
-				wipe-value = [ff];
-			};
-		};
-	};
-
 	pci {
+		compatible = "intel,pci-ivybridge", "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
+			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
+			0x01000000 0x0 0x1000 0x1000 0 0xefff>;
 		sata {
 			compatible = "intel,pantherpoint-ahci";
 			intel,sata-mode = "ahci";
@@ -192,8 +179,10 @@
 			intel,pch-backlight = <0x04000000>;
 		};
 
-		lpc {
-			compatible = "intel,lpc";
+		pch {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,bd82x6x";
+			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			gen-dec = <0x800 0xfc 0x900 0xfc>;
@@ -204,17 +193,44 @@
 						1 0 0 0 0 0 0 0>;
 			/* Enable EC SMI source */
 			intel,alt-gp-smi-enable = <0x0100>;
+			spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich-spi";
+				spi-flash@0 {
+					#size-cells = <1>;
+					#address-cells = <1>;
+					reg = <0>;
+					compatible = "winbond,w25q64",
+							"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x003e0000 0x00010000>;
+						type = "wiped";
+						wipe-value = [ff];
+					};
+				};
+			};
 
-			cros-ec@200 {
-				compatible = "google,cros-ec";
-				reg = <0x204 1 0x200 1 0x880 0x80>;
-
-				/* Describes the flash memory within the EC */
+			lpc {
+				compatible = "intel,bd82x6x-lpc";
 				#address-cells = <1>;
-				#size-cells = <1>;
-				flash@8000000 {
-					reg = <0x08000000 0x20000>;
-					erase-value = <0xff>;
+				#size-cells = <0>;
+				cros-ec@200 {
+					compatible = "google,cros-ec";
+					reg = <0x204 1 0x200 1 0x880 0x80>;
+
+					/*
+					 * Describes the flash memory within
+					 * the EC
+					 */
+					#address-cells = <1>;
+					#size-cells = <1>;
+					flash@8000000 {
+						reg = <0x08000000 0x20000>;
+						erase-value = <0xff>;
+					};
 				};
 			};
 		};
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
new file mode 100644
index 0000000..4eccefd
--- /dev/null
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -0,0 +1,64 @@
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+/include/ "serial.dtsi"
+
+/ {
+	model = "Google Panther";
+	compatible = "google,panther", "intel,haswell";
+
+	aliases {
+		spi0 = "/spi";
+	};
+
+	config {
+		silent-console = <0>;
+		no-keyboard;
+	};
+
+	gpioa {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0 0x10>;
+		bank-name = "A";
+	};
+
+	gpiob {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0x30 0x10>;
+		bank-name = "B";
+	};
+
+	gpioc {
+		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
+		reg = <0x40 0x10>;
+		bank-name = "C";
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	spi {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "intel,ich-spi";
+		spi-flash@0 {
+			#size-cells = <1>;
+			#address-cells = <1>;
+			reg = <0>;
+			compatible = "winbond,w25q64", "spi-flash";
+			memory-map = <0xff800000 0x00800000>;
+			rw-mrc-cache {
+				label = "rw-mrc-cache";
+				/* Alignment: 4k (for updating) */
+				reg = <0x003e0000 0x00010000>;
+				type = "wiped";
+				wipe-value = [ff];
+			};
+		};
+	};
+
+};
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index e1d9a9b..5ae32f7 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -12,7 +12,6 @@ void bd82x6x_sata_enable(pci_dev_t dev, const void *blob, int node);
 void bd82x6x_pci_init(pci_dev_t dev);
 void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
-int bd82x6x_init_pci_devices(void);
 int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
 		   const void *blob, int node);
 int bd82x6x_init(void);
diff --git a/arch/x86/include/asm/arch-ivybridge/mrccache.h b/arch/x86/include/asm/arch-ivybridge/mrccache.h
index 968b2ef..1d50ebb 100644
--- a/arch/x86/include/asm/arch-ivybridge/mrccache.h
+++ b/arch/x86/include/asm/arch-ivybridge/mrccache.h
@@ -20,7 +20,7 @@ __packed struct mrc_data_container {
 };
 
 struct fmap_entry;
-struct spi_flash;
+struct udevice;
 
 /**
  * mrccache_find_current() - find the latest MRC cache record
@@ -45,7 +45,7 @@ struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry);
  * @return 0 if updated, -EEXIST if the record is the same as the latest
  * record, other error if SPI write failed
  */
-int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry,
+int mrccache_update(struct udevice *sf, struct fmap_entry *entry,
 		    struct mrc_data_container *cur);
 
 #endif
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index a153dd1..a1969ed 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -8,6 +8,8 @@
 #ifndef _PCI_I386_H_
 #define _PCI_I386_H_
 
+#include <pci.h>
+
 /* bus mapping constants (used for PCI core initialization) */
 #define PCI_REG_ADDR	0xcf8
 #define PCI_REG_DATA	0xcfc
@@ -48,13 +50,19 @@ int board_pci_post_scan(struct pci_controller *hose);
  * Simple PCI access routines - these work from either the early PCI hose
  * or the 'real' one, created after U-Boot has memory available
  */
-unsigned int pci_read_config8(pci_dev_t dev, unsigned where);
-unsigned int pci_read_config16(pci_dev_t dev, unsigned where);
-unsigned int pci_read_config32(pci_dev_t dev, unsigned where);
+unsigned int x86_pci_read_config8(pci_dev_t dev, unsigned where);
+unsigned int x86_pci_read_config16(pci_dev_t dev, unsigned where);
+unsigned int x86_pci_read_config32(pci_dev_t dev, unsigned where);
+
+void x86_pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
+void x86_pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
+void x86_pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+
+int pci_x86_read_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+			ulong *valuep, enum pci_size_t size);
 
-void pci_write_config8(pci_dev_t dev, unsigned where, unsigned value);
-void pci_write_config16(pci_dev_t dev, unsigned where, unsigned value);
-void pci_write_config32(pci_dev_t dev, unsigned where, unsigned value);
+int pci_x86_write_config(struct udevice *bus, pci_dev_t bdf, uint offset,
+			 ulong value, enum pci_size_t size);
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index c17f7f0..6c571dd 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -14,10 +14,14 @@ obj-$(CONFIG_HAVE_FSP) += cmd_hob.o
 obj-y	+= gcc.o
 obj-y	+= init_helpers.o
 obj-y	+= interrupts.o
+obj-y	+= lpc-uclass.o
 obj-y += cmd_mtrr.o
 obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o
 obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
+ifndef CONFIG_DM_PCI
 obj-$(CONFIG_PCI) += pci_type1.o
+endif
+obj-y	+= pch-uclass.o
 obj-y	+= relocate.o
 obj-y += physmem.o
 obj-$(CONFIG_X86_RAMTEST) += ramtest.o
diff --git a/arch/x86/lib/bios_interrupts.c b/arch/x86/lib/bios_interrupts.c
index b0e2ecb..290990a 100644
--- a/arch/x86/lib/bios_interrupts.c
+++ b/arch/x86/lib/bios_interrupts.c
@@ -172,28 +172,28 @@ int int1a_handler(void)
 		}
 		switch (func) {
 		case 0xb108: /* Read Config Byte */
-			byte = pci_read_config8(dev, reg);
+			byte = x86_pci_read_config8(dev, reg);
 			M.x86.R_ECX = byte;
 			break;
 		case 0xb109: /* Read Config Word */
-			word = pci_read_config16(dev, reg);
+			word = x86_pci_read_config16(dev, reg);
 			M.x86.R_ECX = word;
 			break;
 		case 0xb10a: /* Read Config Dword */
-			dword = pci_read_config32(dev, reg);
+			dword = x86_pci_read_config32(dev, reg);
 			M.x86.R_ECX = dword;
 			break;
 		case 0xb10b: /* Write Config Byte */
 			byte = M.x86.R_ECX;
-			pci_write_config8(dev, reg, byte);
+			x86_pci_write_config8(dev, reg, byte);
 			break;
 		case 0xb10c: /* Write Config Word */
 			word = M.x86.R_ECX;
-			pci_write_config16(dev, reg, word);
+			x86_pci_write_config16(dev, reg, word);
 			break;
 		case 0xb10d: /* Write Config Dword */
 			dword = M.x86.R_ECX;
-			pci_write_config32(dev, reg, dword);
+			x86_pci_write_config32(dev, reg, dword);
 			break;
 		}
 
diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c
index 5097ca2..4fd47fc 100644
--- a/arch/x86/lib/init_helpers.c
+++ b/arch/x86/lib/init_helpers.c
@@ -89,11 +89,3 @@ int init_bd_struct_r(void)
 
 	return 0;
 }
-
-int init_func_spi(void)
-{
-	puts("SPI:   ");
-	spi_init();
-	puts("ready\n");
-	return 0;
-}
diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c
new file mode 100644
index 0000000..6aeb4d4
--- /dev/null
+++ b/arch/x86/lib/lpc-uclass.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/root.h>
+
+static int lpc_uclass_post_bind(struct udevice *bus)
+{
+	/*
+	 * Scan the device tree for devices
+	 *
+	 * Before relocation, only bind devices marked for pre-relocation
+	 * use.
+	 */
+	return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
+				gd->flags & GD_FLG_RELOC ? false : true);
+}
+
+UCLASS_DRIVER(lpc) = {
+	.id		= UCLASS_LPC,
+	.name		= "lpc",
+	.post_bind	= lpc_uclass_post_bind,
+};
diff --git a/arch/x86/lib/pch-uclass.c b/arch/x86/lib/pch-uclass.c
new file mode 100644
index 0000000..d1082e1
--- /dev/null
+++ b/arch/x86/lib/pch-uclass.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/root.h>
+
+static int pch_uclass_post_bind(struct udevice *bus)
+{
+	/*
+	 * Scan the device tree for devices
+	 *
+	 * Before relocation, only bind devices marked for pre-relocation
+	 * use.
+	 */
+	return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
+				gd->flags & GD_FLG_RELOC ? false : true);
+}
+
+UCLASS_DRIVER(pch) = {
+	.id		= UCLASS_PCH,
+	.name		= "pch",
+	.post_bind	= pch_uclass_post_bind,
+};
author	Albert ARIBAUD <albert.u.boot@aribaud.net>	2015-05-05 10:09:06 +0200
committer	Albert ARIBAUD <albert.u.boot@aribaud.net>	2015-05-05 10:09:06 +0200
commit	b939689c7b87773c44275a578ffc8674a867e39d (patch)
tree	785d71eb0bbc707385e4456a14b21706223d99a3 /arch
parent	97840b5d1fe0960134c3553a9d9d1c1cd1be784d (diff)
parent	ace97d26176a3ebc9ec07738450de93eea35975c (diff)
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