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| author | VNSL Durga <vnsl.durga.challa@xilinx.com> | 2016-03-24 22:45:12 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2016-04-13 18:29:04 +0200 |
| commit | b34d11de188186e8ca39de6b4f7453823ab20820 (patch) | |
| tree | aba01821d6e5a881e2d788ea6a815bf11991826e /arch | |
| parent | ff50d21bd23b4d8a579100a790f5db81498e2d07 (diff) | |
| download | u-boot-imx-b34d11de188186e8ca39de6b4f7453823ab20820.zip u-boot-imx-b34d11de188186e8ca39de6b4f7453823ab20820.tar.gz u-boot-imx-b34d11de188186e8ca39de6b4f7453823ab20820.tar.bz2 | |
ARM64: zynqmp: Added clocks to DT
ZynqMP DMA's main clock and apb clock are added
in zynqmp DT.
Signed-off-by: VNSL Durga <vnsldurg@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/dts/zynqmp.dtsi | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 48505fa..4520930 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -318,6 +318,7 @@ reg = <0x0 0xfd500000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 124 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <0>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -329,6 +330,7 @@ reg = <0x0 0xfd510000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 125 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <1>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -340,6 +342,7 @@ reg = <0x0 0xfd520000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 126 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <2>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -351,6 +354,7 @@ reg = <0x0 0xfd530000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 127 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <3>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -362,6 +366,7 @@ reg = <0x0 0xfd540000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 128 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <4>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -373,6 +378,7 @@ reg = <0x0 0xfd550000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 129 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <5>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -384,6 +390,7 @@ reg = <0x0 0xfd560000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 130 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <6>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; @@ -395,6 +402,7 @@ reg = <0x0 0xfd570000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 131 4>; + clock-names = "clk_main", "clk_apb"; xlnx,id = <7>; xlnx,bus-width = <128>; power-domains = <&pd_gdma>; |