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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-07-20 19:28:28 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-08-02 11:05:08 +0200 |
| commit | a2c74aaf51171fbdfab725c4dd05b58b1ce45070 (patch) | |
| tree | 4a42ddb2bb0954063819ee3f895e6cf05d10b45f /arch | |
| parent | 43cb127b75d7511705e14d4d8b761f61d102bde7 (diff) | |
| download | u-boot-imx-a2c74aaf51171fbdfab725c4dd05b58b1ce45070.zip u-boot-imx-a2c74aaf51171fbdfab725c4dd05b58b1ce45070.tar.gz u-boot-imx-a2c74aaf51171fbdfab725c4dd05b58b1ce45070.tar.bz2 | |
imx: mx6ul select SYS_L2CACHE_OFF
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/Kconfig | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 68b46c1..dce7ffc 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -25,6 +25,10 @@ config MX6SL config MX6SX bool +config MX6UL + select SYS_L2CACHE_OFF + bool + choice prompt "MX6 board select" optional |