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| author | Chen-Yu Tsai <wens@csie.org> | 2015-05-28 21:25:33 +0800 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-05-29 13:46:36 +0200 |
| commit | 98167430317a6275e582def8cb4aee76799789af (patch) | |
| tree | 5c252e4d066be14254f602bd9bac15a7dab1f5a6 /arch | |
| parent | cc08ea4cff827f0929744d8d0134422e01c1f2b5 (diff) | |
| download | u-boot-imx-98167430317a6275e582def8cb4aee76799789af.zip u-boot-imx-98167430317a6275e582def8cb4aee76799789af.tar.gz u-boot-imx-98167430317a6275e582def8cb4aee76799789af.tar.bz2 | |
ARM: sunxi: Share sun6i PSCI backend with sun8i
sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 4b783e0..76c7e55 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -37,6 +37,7 @@ ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARMV7_PSCI obj-$(CONFIG_MACH_SUN6I) += psci_sun6i.o obj-$(CONFIG_MACH_SUN7I) += psci_sun7i.o +obj-$(CONFIG_MACH_SUN8I) += psci_sun6i.o endif endif diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index 2516804..d4cb51e 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -124,11 +124,13 @@ psci_fiq_enter: str r10, [r8, #0x100] timer_wait r10, ONE_MS +#ifdef CONFIG_MACH_SUN6I @ Activate power clamp lsl r12, r9, #2 @ x4 add r12, r12, r8 mov r10, #0xff str r10, [r12, #0x140] +#endif movw r8, #(SUN6I_CPUCFG_BASE & 0xffff) movt r8, #(SUN6I_CPUCFG_BASE >> 16) @@ -186,6 +188,7 @@ psci_cpu_on: movw r0, #(SUNXI_PRCM_BASE & 0xffff) movt r0, #(SUNXI_PRCM_BASE >> 16) +#ifdef CONFIG_MACH_SUN6I @ Release power clamp lsl r5, r1, #2 @ 1 register per CPU add r5, r5, r0 @ PRCM @@ -194,6 +197,7 @@ psci_cpu_on: 1: lsrs r6, r6, #1 str r6, [r5, #0x140] @ CPUx_PWR_CLAMP bne 1b +#endif timer_wait r6, TEN_MS |