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author | Chris Zankel <chris@zankel.net> | 2016-08-10 18:36:48 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2016-08-15 18:46:40 -0400 |
commit | 7e270ec3af02d2358f9a454ba0d0bb39f07d14b6 (patch) | |
tree | 6d60ccd942f2dccb9017550e988a446de7351781 /arch | |
parent | 28b48a0710cde7270bca423cee8ed12b0c54eb01 (diff) | |
download | u-boot-imx-7e270ec3af02d2358f9a454ba0d0bb39f07d14b6.zip u-boot-imx-7e270ec3af02d2358f9a454ba0d0bb39f07d14b6.tar.gz u-boot-imx-7e270ec3af02d2358f9a454ba0d0bb39f07d14b6.tar.bz2 |
xtensa: add support for the 'xtfpga' evaluation board
The 'xtfpga' board is actually a set of FPGA evaluation boards that
can be configured to run an Xtensa processor.
- Avnet Xilinx LX60
- Avnet Xilinx LX110
- Avnet Xilinx LX200
- Xilinx ML605
- Xilinx KC705
These boards share the same components (open-ethernet, ns16550 serial,
lcd display, flash, etc.).
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/xtensa/Kconfig | 3 | ||||
-rw-r--r-- | arch/xtensa/dts/Makefile | 2 | ||||
-rw-r--r-- | arch/xtensa/dts/kc705.dts | 15 | ||||
-rw-r--r-- | arch/xtensa/dts/kc705_nommu.dts | 17 | ||||
-rw-r--r-- | arch/xtensa/dts/ml605.dts | 15 | ||||
-rw-r--r-- | arch/xtensa/dts/ml605_nommu.dts | 18 | ||||
-rw-r--r-- | arch/xtensa/dts/xtfpga-flash-128m.dtsi | 28 | ||||
-rw-r--r-- | arch/xtensa/dts/xtfpga-flash-16m.dtsi | 28 | ||||
-rw-r--r-- | arch/xtensa/dts/xtfpga.dtsi | 137 |
9 files changed, 263 insertions, 0 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index bb6a678..2ba7132 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -11,8 +11,11 @@ config SYS_CPU choice prompt "Target select" +config TARGET_XTFPGA + bool "Support XTFPGA" endchoice +source "board/cadence/xtfpga/Kconfig" endmenu diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile index eacf6f3..e14cdac 100644 --- a/arch/xtensa/dts/Makefile +++ b/arch/xtensa/dts/Makefile @@ -2,6 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb + targets += $(dtb-y) DTC_FLAGS += diff --git a/arch/xtensa/dts/kc705.dts b/arch/xtensa/dts/kc705.dts new file mode 100644 index 0000000..3b89e83 --- /dev/null +++ b/arch/xtensa/dts/kc705.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-128m.dtsi" + +/ { + compatible = "cdns,xtensa-kc705"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + stdout-path = &serial0; + }; + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x38000000>; + }; +}; diff --git a/arch/xtensa/dts/kc705_nommu.dts b/arch/xtensa/dts/kc705_nommu.dts new file mode 100644 index 0000000..57f0dab --- /dev/null +++ b/arch/xtensa/dts/kc705_nommu.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-128m.dtsi" + +/ { + compatible = "cdns,xtensa-kc705"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + }; + memory@0 { + device_type = "memory"; + reg = <0x60000000 0x10000000>; + }; + soc { + ranges = <0x00000000 0x90000000 0x10000000>; + }; +}; diff --git a/arch/xtensa/dts/ml605.dts b/arch/xtensa/dts/ml605.dts new file mode 100644 index 0000000..f323f96 --- /dev/null +++ b/arch/xtensa/dts/ml605.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-16m.dtsi" + +/ { + compatible = "cdns,xtensa-ml605"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + stdout-path = &serial0; + }; + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x18000000>; + }; +}; diff --git a/arch/xtensa/dts/ml605_nommu.dts b/arch/xtensa/dts/ml605_nommu.dts new file mode 100644 index 0000000..6bdf400 --- /dev/null +++ b/arch/xtensa/dts/ml605_nommu.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-16m.dtsi" + +/ { + compatible = "cdns,xtensa-ml605"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + stdout-path = &serial0; + }; + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + soc { + ranges = <0x00000000 0x90000000 0x10000000>; + }; +}; diff --git a/arch/xtensa/dts/xtfpga-flash-128m.dtsi b/arch/xtensa/dts/xtfpga-flash-128m.dtsi new file mode 100644 index 0000000..d3a88e0 --- /dev/null +++ b/arch/xtensa/dts/xtfpga-flash-128m.dtsi @@ -0,0 +1,28 @@ +/ { + soc { + flash: flash@00000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x00000000 0x08000000>; + bank-width = <2>; + device-width = <2>; + partition@0x0 { + label = "data"; + reg = <0x00000000 0x06000000>; + }; + partition@0x6000000 { + label = "boot loader area"; + reg = <0x06000000 0x00800000>; + }; + partition@0x6800000 { + label = "kernel image"; + reg = <0x06800000 0x017e0000>; + }; + partition@0x7fe0000 { + label = "boot environment"; + reg = <0x07fe0000 0x00020000>; + }; + }; + }; +}; diff --git a/arch/xtensa/dts/xtfpga-flash-16m.dtsi b/arch/xtensa/dts/xtfpga-flash-16m.dtsi new file mode 100644 index 0000000..1d97203 --- /dev/null +++ b/arch/xtensa/dts/xtfpga-flash-16m.dtsi @@ -0,0 +1,28 @@ +/ { + soc { + flash: flash@08000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x08000000 0x01000000>; + bank-width = <2>; + device-width = <2>; + partition@0x0 { + label = "boot loader area"; + reg = <0x00000000 0x00400000>; + }; + partition@0x400000 { + label = "kernel image"; + reg = <0x00400000 0x00600000>; + }; + partition@0xa00000 { + label = "data"; + reg = <0x00a00000 0x005e0000>; + }; + partition@0xfe0000 { + label = "boot environment"; + reg = <0x00fe0000 0x00020000>; + }; + }; + }; +}; diff --git a/arch/xtensa/dts/xtfpga.dtsi b/arch/xtensa/dts/xtfpga.dtsi new file mode 100644 index 0000000..cd45f9c --- /dev/null +++ b/arch/xtensa/dts/xtfpga.dtsi @@ -0,0 +1,137 @@ +/ { + compatible = "cdns,xtensa-xtfpga"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x06000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "cdns,xtensa-cpu"; + reg = <0>; + /* Filled in by platform_setup from FPGA register + * clock-frequency = <100000000>; + */ + }; + }; + + pic: pic { + compatible = "cdns,xtensa-pic"; + /* one cell: internal irq number, + * two cells: second cell == 0: internal irq number + * second cell == 1: external irq number + */ + #interrupt-cells = <2>; + interrupt-controller; + }; + + clocks { + osc: main-oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + clk54: clk54 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + + serial0: serial@0d050020 { + device_type = "serial"; + compatible = "ns16550a"; + no-loopback-test; + reg = <0x0d050020 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + native-endian; + interrupts = <0 1>; /* external irq 0 */ + clocks = <&osc>; + }; + + enet0: ethoc@0d030000 { + compatible = "opencores,ethoc"; + reg = <0x0d030000 0x4000 0x0d800000 0x4000>; + native-endian; + interrupts = <1 1>; /* external irq 1 */ + local-mac-address = [00 50 c2 13 6f 00]; + clocks = <&osc>; + }; + + i2s0: xtfpga-i2s@0d080000 { + #sound-dai-cells = <0>; + compatible = "cdns,xtfpga-i2s"; + reg = <0x0d080000 0x40>; + interrupts = <2 1>; /* external irq 2 */ + clocks = <&cdce706 4>; + }; + + i2c0: i2c-master@0d090000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0d090000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + native-endian; + interrupts = <4 1>; + clocks = <&osc>; + + cdce706: clock-synth@69 { + compatible = "ti,cdce706"; + #clock-cells = <1>; + reg = <0x69>; + clocks = <&clk54>; + clock-names = "clk_in0"; + }; + }; + + spi0: spi-master@0d0a0000 { + compatible = "cdns,xtfpga-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0d0a0000 0xc>; + + tlv320aic23: sound-codec@0 { + #sound-dai-cells = <0>; + compatible = "tlv320aic23"; + reg = <0>; + spi-max-frequency = <12500000>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic23>; + simple-audio-card,bitclock-master = <0>; + simple-audio-card,frame-master = <0>; + clocks = <&cdce706 4>; + }; + }; +}; |