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| author | Ajay Kumar <ajaykumar.rs@samsung.com> | 2015-03-04 19:05:25 +0530 |
|---|---|---|
| committer | Minkyu Kang <mk7.kang@samsung.com> | 2015-04-06 14:34:40 +0900 |
| commit | 6102560891d09db79196654aa414afc5acfa7911 (patch) | |
| tree | 2b1dd6a626e369c4da48d579fb3038b2cbb0de7e /arch | |
| parent | 70b4fb660df25d4a150833f7487a0059d1827fee (diff) | |
| download | u-boot-imx-6102560891d09db79196654aa414afc5acfa7911.zip u-boot-imx-6102560891d09db79196654aa414afc5acfa7911.tar.gz u-boot-imx-6102560891d09db79196654aa414afc5acfa7911.tar.bz2 | |
Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panels
The existing setting for rpll_sdiv generates 70.5Mhz RPLL
video clock to drive 1366x768 panel on peach_pit.
This clock rate is not sufficient to drive 1920x1080 panel on peach-pi.
So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock
which can drive peach-pi LCD.
This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD
divider at IP level will get set to 1(the required divider setting
will be calculated and set by exynos_fimd_set_clock()) and hence
peach-pit LCD still works fine.
Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c index 0aff3d0..0200fd1 100644 --- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c @@ -179,10 +179,10 @@ struct mem_timings mem_timings[] = { .spll_mdiv = 0xc8, .spll_pdiv = 0x3, .spll_sdiv = 0x2, - /* RPLL @70.5Mhz */ + /* RPLL @141Mhz */ .rpll_mdiv = 0x5E, .rpll_pdiv = 0x2, - .rpll_sdiv = 0x4, + .rpll_sdiv = 0x3, .direct_cmd_msr = { 0x00020018, 0x00030000, 0x00010046, 0x00000d70, |