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authorPeng Fan <Peng.Fan@freescale.com>2015-09-06 17:15:47 +0800
committerStefano Babic <sbabic@denx.de>2015-10-02 10:42:31 +0200
commite2748b416798be31f035c8314787bf1867005b57 (patch)
tree291846157cc479fd821710e176822f877a8d2ec9 /arch
parent1f8836396de8215b7f460616926052b32597bb29 (diff)
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imx: mx6: correct enable_fec_anatop_clock
We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock, otherwise we may overridden configuration before enable_fec_anatop_clock. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/clock.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ba6cc75..11efd12 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -535,6 +535,8 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
+ reg = readl(&anatop->pll_enet);
+
if (fec_id == 0) {
reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);