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authorBai Ping <ping.bai@nxp.com>2016-06-08 14:50:04 +0800
committerBai Ping <ping.bai@nxp.com>2016-06-08 15:25:01 +0800
commit91703d0672342145da32d4e1bc1f42436dbae6cf (patch)
treebab8e8724cc02489a2dfbb2b40ed94dfed46df9c /arch
parentc5dc9e64ff56761f8742c47cc1975d2d48b0cf17 (diff)
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MLK-12894 imx6ull: adjust the ldo 1.2v bandgap voltage on i.mx6ull
Per to design team, on i.MX6UL, the LDO 1.2V bandgap voltage is 30mV higher, so we need to adjust the REFTOP_VBGADJ(anatop MISC0 bit[6:4]) setting to 2b'110. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c6
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h1
2 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index d54b581..1f3e145 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -324,6 +324,12 @@ static void init_bandgap(void)
* be set.
*/
writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
+ /*
+ * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
+ * VBGADJ bits to 2b'110 to adjust it.
+ */
+ if (is_cpu_type(MXC_CPU_MX6ULL))
+ writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
}
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 0999055..bc4f39e 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1272,6 +1272,7 @@ struct mxc_ccm_reg {
(((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
#define BP_PMU_MISC2_AUDIO_DIV_MSB 23