ENGR00319965 pcie: mask the imx6sl out

imx6sl doesn't have the pcie module, mask the pcie
related codes from imx6sl.

Signed-off-by: Richard Zhu <r65037@freescale.com>
(cherry picked from commit acaff11da33f8f0cb1521d3c48e64e7ed9a87bec)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

1 files changed, 19 insertions, 15 deletions

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ba8853e..c8bb203 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -413,23 +413,27 @@ static void imx_set_pcie_phy_power_down(void)
 
 int arch_cpu_init(void)
 {
-#ifndef CONFIG_MX6SX
-	/* this bit is not used by imx6sx anymore */
-	u32 val;
+	if (!is_cpu_type(MXC_CPU_MX6SL) && !!is_cpu_type(MXC_CPU_MX6SX)
+		&& !is_cpu_type(MXC_CPU_MX6UL)) {
+		/*
+		 * imx6sl doesn't have pcie at all.
+		 * this bit is not used by imx6sx anymore
+		 */
+		u32 val;
 
-	/*
-	 * There are about 0.02% percentage, random pcie link down
-	 * when warm-reset is used.
-	 * clear the ref_ssp_en bit16 of gpr1 to workaround it.
-	 * then warm-reset imx6q/dl/solo again.
-	 */
-	val = readl(IOMUXC_BASE_ADDR + 0x4);
-	if (val & (0x1 << 16)) {
-		val &= ~(0x1 << 16);
-		writel(val, IOMUXC_BASE_ADDR + 0x4);
-		reset_cpu(0);
+		/*
+		 * There are about 0.02% percentage, random pcie link down
+		 * when warm-reset is used.
+		 * clear the ref_ssp_en bit16 of gpr1 to workaround it.
+		 * then warm-reset imx6q/dl/solo again.
+		 */
+		val = readl(IOMUXC_BASE_ADDR + 0x4);
+		if (val & (0x1 << 16)) {
+			val &= ~(0x1 << 16);
+			writel(val, IOMUXC_BASE_ADDR + 0x4);
+			reset_cpu(0);
+		}
 	}
-#endif
 
 	init_aips();