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| author | Prabhakar Kushwaha <prabhakar@freescale.com> | 2014-04-08 19:12:31 +0530 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-04-22 17:58:50 -0700 |
| commit | 651fcf6019eec1a65d4227082e12bc6ad4576f41 (patch) | |
| tree | b540b53b7f9a4e7b70737dc0bd73c3791a655b20 /arch | |
| parent | 49efe85b35e61fb50b00ca02354dfca0d3c5c46c (diff) | |
| download | u-boot-imx-651fcf6019eec1a65d4227082e12bc6ad4576f41.zip u-boot-imx-651fcf6019eec1a65d4227082e12bc6ad4576f41.tar.gz u-boot-imx-651fcf6019eec1a65d4227082e12bc6ad4576f41.tar.bz2 | |
powerpc:Add support of SPL non-relocation
Current SPL code base has BSS section placed after reset_vector. This means
they have to relocate to use the global variables. This put an implicit
requirement of having SPL size = Memory/2.
To avoid relocation:
- Move bss_section within SPL range
- Modify relocate_code()
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 2 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 12 |
2 files changed, 14 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 02f5076..0e3c86a 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1652,6 +1652,7 @@ relocate_code: mr r10,r5 /* Save copy of Destination Address */ GET_GOT +#ifndef CONFIG_SPL_SKIP_RELOCATE mr r3,r5 /* Destination Address */ lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */ ori r4,r4,CONFIG_SYS_MONITOR_BASE@l @@ -1742,6 +1743,7 @@ relocate_code: mtlr r0 blr /* NEVER RETURNS! */ +#endif .globl in_ram in_ram: diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds index 4fad68b..8453f3a 100644 --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds @@ -57,6 +57,16 @@ SECTIONS . = ALIGN(8); __init_begin = .; __init_end = .; +#ifdef CONFIG_SPL_SKIP_RELOCATE + . = ALIGN(4); + __bss_start = .; + .bss : { + *(.sbss*) + *(.bss*) + } + . = ALIGN(4); + __bss_end = .; +#endif /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */ #ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC @@ -86,6 +96,7 @@ SECTIONS } = 0xffff #endif +#ifndef CONFIG_SPL_SKIP_RELOCATE /* * Make sure that the bss segment isn't linked at 0x0, otherwise its * address won't be updated during relocation fixups. @@ -100,4 +111,5 @@ SECTIONS } . = ALIGN(4); __bss_end = .; +#endif } |