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authorgaurav rana <gaurav.rana@freescale.com>2015-02-27 09:43:49 +0530
committerYork Sun <yorksun@freescale.com>2015-03-05 12:04:59 -0800
commita2e225e65df3d0fe0ddefec77a3db05b881d1e68 (patch)
treeec573eb50deb5053a8aee788b008c188ecf1caee /arch
parentccf288612f9c66d592df241ba3c05ead92a45972 (diff)
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fsl_sfp : Move ccsr_sfp_regs definition to common include
Freescale sfp has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the CCSR defintion of sfp_regs to common include. This patch also defines ccsr_sfp_regs definition for newer versions of SFP. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/config_mpc85xx.h1
-rw-r--r--arch/powerpc/include/asm/immap_85xx.h16
2 files changed, 2 insertions, 15 deletions
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 0e25f3b..cb0f441 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -25,6 +25,7 @@
/* IP endianness */
#define CONFIG_SYS_FSL_IFC_BE
#define CONFIG_SYS_FSL_SEC_BE
+#define CONFIG_SYS_FSL_SFP_BE
/* Number of TLB CAM entries we have on FSL Book-E chips */
#if defined(CONFIG_E500MC)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index ace1d12..f89b90b 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -17,6 +17,7 @@
#include <asm/fsl_i2c.h>
#include <fsl_ifc.h>
#include <fsl_sec.h>
+#include <fsl_sfp.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
#include <fsl_immap.h>
@@ -2823,21 +2824,6 @@ struct ccsr_pman {
u8 res_f4[0xf0c];
};
#endif
-#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
-struct ccsr_sfp_regs {
- u32 ospr; /* 0x200 */
- u32 reserved0[14];
- u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
- u32 oem_uid; /* 0x9c OEM Unique ID */
- u8 reserved2[0x04];
- u32 ovpr; /* 0xA4 Intent To Secure */
- u8 reserved4[0x08];
- u32 fsl_uid; /* 0xB0 FSL Unique ID */
- u8 reserved5[0x04];
- u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
- u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
-};
-#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000