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authorTom Rini <trini@ti.com>2015-01-22 09:51:50 -0500
committerTom Rini <trini@ti.com>2015-01-22 09:51:50 -0500
commit9d86c8dc960c6f4e7e349a41cd2757098da6a92f (patch)
tree908d2396bf753f55f8edab3009d79dd7d72909f5 /arch
parent65afbbde6bd4429add8a644d8e2adbdbb812f7ec (diff)
parentda931af1b5eaae36dd9e3fb2eaf6b62201ed3a43 (diff)
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Merge branch 'next' of git://www.denx.de/git/u-boot-microblaze
Diffstat (limited to 'arch')
-rw-r--r--arch/microblaze/cpu/start.S6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S
index 1757bbf..84c29e5 100644
--- a/arch/microblaze/cpu/start.S
+++ b/arch/microblaze/cpu/start.S
@@ -23,11 +23,15 @@ _start:
mts rmsr, r0 /* disable cache */
+ addi r8, r0, __end
+ mts rslr, r8
#if defined(CONFIG_SPL_BUILD)
addi r1, r0, CONFIG_SPL_STACK_ADDR
+ mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
#else
addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
+ mts rshr, r1
addi r1, r1, -4 /* Decrement SP to top of memory */
/* Find-out if u-boot is running on BIG/LITTLE endian platform
@@ -130,7 +134,7 @@ flush: bralid r15, flush_cache
/* enable instruction and data cache */
mfs r12, rmsr
- ori r12, r12, 0xa0
+ ori r12, r12, 0x1a0
mts rmsr, r12
clear_bss: