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authorSoeren Moch <smoch@web.de>2014-10-24 16:33:28 +0200
committerStefano Babic <sbabic@denx.de>2014-10-30 11:58:18 +0100
commit4bfa2db8e19d5e500d75ac71f3faacb7614df24b (patch)
treece97e7f6b2e8df699ff579c66ed5a15f0a2a9f65 /arch
parentf9cfe17b3d145edd2a308a934594d659ffc69439 (diff)
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arm: arch-mx6: typo fixes in crm_regs.h
fix typos in video pll related register names and bit defines Signed-off-by: Soeren Moch <smoch@web.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-mx6/crm_regs.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 85e301c..92f9b21 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -931,10 +931,10 @@ struct mxc_ccm_reg {
#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
(((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
- (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \
+ (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000