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authorMarek Vasut <marek.vasut@gmail.com>2011-08-28 03:35:13 +0200
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-11-15 22:24:50 +0100
commit237ce0fe97f9d4206011fcb9f509e50fef4ef2f0 (patch)
tree4f6435c5725ce0504d7ecd3096c65784a1b57039 /arch
parentdd36d806fe549f40e059dd9d5072f8e017ed30dd (diff)
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PXA: Cleanup serial_pxa
* Cleanup register definitions by introducing new regs-uart.h, compliant with rest of U-Boot. * Remove old register definitions from pxa-regs.h * Convert serial_pxa to new regs-uart.h * Cleanup serial_pxa Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-pxa/pxa-regs.h111
-rw-r--r--arch/arm/include/asm/arch-pxa/regs-uart.h109
2 files changed, 109 insertions, 111 deletions
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 109fdc0..52c79a9 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -315,117 +315,6 @@ typedef void (*ExcpHndlr) (void) ;
/******************************************************************************/
/*
- * UARTs
- */
-/* Full Function UART (FFUART) */
-#define FFUART FFRBR
-#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
-#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
-#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
-#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
-#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
-#define FFLCR 0x4010000C /* Line Control Register (read/write) */
-#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
-#define FFLSR 0x40100014 /* Line Status Register (read only) */
-#define FFMSR 0x40100018 /* Modem Status Register (read only) */
-#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
-#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
-#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Bluetooth UART (BTUART) */
-#define BTUART BTRBR
-#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
-#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
-#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
-#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
-#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
-#define BTLCR 0x4020000C /* Line Control Register (read/write) */
-#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
-#define BTLSR 0x40200014 /* Line Status Register (read only) */
-#define BTMSR 0x40200018 /* Modem Status Register (read only) */
-#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
-#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
-#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-/* Standard UART (STUART) */
-#define STUART STRBR
-#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
-#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
-#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
-#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
-#define STFCR 0x40700008 /* FIFO Control Register (write only) */
-#define STLCR 0x4070000C /* Line Control Register (read/write) */
-#define STMCR 0x40700010 /* Modem Control Register (read/write) */
-#define STLSR 0x40700014 /* Line Status Register (read only) */
-#define STMSR 0x40700018 /* Reserved */
-#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
-#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
-#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
-#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
-
-#define IER_DMAE (1 << 7) /* DMA Requests Enable */
-#define IER_UUE (1 << 6) /* UART Unit Enable */
-#define IER_NRZE (1 << 5) /* NRZ coding Enable */
-#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
-#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
-#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
-#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
-#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
-
-#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
-#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
-#define IIR_TOD (1 << 3) /* Time Out Detected */
-#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
-#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
-#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
-
-#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
-#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
-#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
-#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
-#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
-#define FCR_ITL_1 (0)
-#define FCR_ITL_8 (FCR_ITL1)
-#define FCR_ITL_16 (FCR_ITL2)
-#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
-
-#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
-#define LCR_SB (1 << 6) /* Set Break */
-#define LCR_STKYP (1 << 5) /* Sticky Parity */
-#define LCR_EPS (1 << 4) /* Even Parity Select */
-#define LCR_PEN (1 << 3) /* Parity Enable */
-#define LCR_STB (1 << 2) /* Stop Bit */
-#define LCR_WLS1 (1 << 1) /* Word Length Select */
-#define LCR_WLS0 (1 << 0) /* Word Length Select */
-
-#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
-#define LSR_TEMT (1 << 6) /* Transmitter Empty */
-#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
-#define LSR_BI (1 << 4) /* Break Interrupt */
-#define LSR_FE (1 << 3) /* Framing Error */
-#define LSR_PE (1 << 2) /* Parity Error */
-#define LSR_OE (1 << 1) /* Overrun Error */
-#define LSR_DR (1 << 0) /* Data Ready */
-
-#define MCR_LOOP (1 << 4) /* */
-#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
-#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
-#define MCR_RTS (1 << 1) /* Request to Send */
-#define MCR_DTR (1 << 0) /* Data Terminal Ready */
-
-#define MSR_DCD (1 << 7) /* Data Carrier Detect */
-#define MSR_RI (1 << 6) /* Ring Indicator */
-#define MSR_DSR (1 << 5) /* Data Set Ready */
-#define MSR_CTS (1 << 4) /* Clear To Send */
-#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
-#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
-#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
-#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-
-/******************************************************************************/
-/*
* IrSR (Infrared Selection Register)
*/
#define IrSR_OFFSET 0x20
diff --git a/arch/arm/include/asm/arch-pxa/regs-uart.h b/arch/arm/include/asm/arch-pxa/regs-uart.h
new file mode 100644
index 0000000..355e892
--- /dev/null
+++ b/arch/arm/include/asm/arch-pxa/regs-uart.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __REGS_UART_H__
+#define __REGS_UART_H__
+
+#define FFUART_BASE 0x40100000
+#define BTUART_BASE 0x40200000
+#define STUART_BASE 0x40700000
+#define HWUART_BASE 0x41600000
+
+struct pxa_uart_regs {
+ union {
+ uint32_t thr;
+ uint32_t rbr;
+ uint32_t dll;
+ };
+ union {
+ uint32_t ier;
+ uint32_t dlh;
+ };
+ union {
+ uint32_t fcr;
+ uint32_t iir;
+ };
+ uint32_t lcr;
+ uint32_t mcr;
+ uint32_t lsr;
+ uint32_t msr;
+ uint32_t spr;
+ uint32_t isr;
+};
+
+#define IER_DMAE (1 << 7)
+#define IER_UUE (1 << 6)
+#define IER_NRZE (1 << 5)
+#define IER_RTIOE (1 << 4)
+#define IER_MIE (1 << 3)
+#define IER_RLSE (1 << 2)
+#define IER_TIE (1 << 1)
+#define IER_RAVIE (1 << 0)
+
+#define IIR_FIFOES1 (1 << 7)
+#define IIR_FIFOES0 (1 << 6)
+#define IIR_TOD (1 << 3)
+#define IIR_IID2 (1 << 2)
+#define IIR_IID1 (1 << 1)
+#define IIR_IP (1 << 0)
+
+#define FCR_ITL2 (1 << 7)
+#define FCR_ITL1 (1 << 6)
+#define FCR_RESETTF (1 << 2)
+#define FCR_RESETRF (1 << 1)
+#define FCR_TRFIFOE (1 << 0)
+#define FCR_ITL_1 0
+#define FCR_ITL_8 (FCR_ITL1)
+#define FCR_ITL_16 (FCR_ITL2)
+#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB (1 << 7)
+#define LCR_SB (1 << 6)
+#define LCR_STKYP (1 << 5)
+#define LCR_EPS (1 << 4)
+#define LCR_PEN (1 << 3)
+#define LCR_STB (1 << 2)
+#define LCR_WLS1 (1 << 1)
+#define LCR_WLS0 (1 << 0)
+
+#define LSR_FIFOE (1 << 7)
+#define LSR_TEMT (1 << 6)
+#define LSR_TDRQ (1 << 5)
+#define LSR_BI (1 << 4)
+#define LSR_FE (1 << 3)
+#define LSR_PE (1 << 2)
+#define LSR_OE (1 << 1)
+#define LSR_DR (1 << 0)
+
+#define MCR_LOOP (1 << 4)
+#define MCR_OUT2 (1 << 3)
+#define MCR_OUT1 (1 << 2)
+#define MCR_RTS (1 << 1)
+#define MCR_DTR (1 << 0)
+
+#define MSR_DCD (1 << 7)
+#define MSR_RI (1 << 6)
+#define MSR_DSR (1 << 5)
+#define MSR_CTS (1 << 4)
+#define MSR_DDCD (1 << 3)
+#define MSR_TERI (1 << 2)
+#define MSR_DDSR (1 << 1)
+#define MSR_DCTS (1 << 0)
+
+#endif /* __REGS_UART_H__ */