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| author | Simon Glass <sjg@chromium.org> | 2015-01-19 22:16:13 -0700 |
|---|---|---|
| committer | Simon Glass <sjg@chromium.org> | 2015-01-24 06:13:45 -0700 |
| commit | a9aff2f46a7f7d29a662531dbc181773f16a606d (patch) | |
| tree | 4c340ea0b74ccb57fae8987f13b1aae994ef77b3 /arch | |
| parent | 146251f87eaebbd77ca9596391890b44cbda47fb (diff) | |
| download | u-boot-imx-a9aff2f46a7f7d29a662531dbc181773f16a606d.zip u-boot-imx-a9aff2f46a7f7d29a662531dbc181773f16a606d.tar.gz u-boot-imx-a9aff2f46a7f7d29a662531dbc181773f16a606d.tar.bz2 | |
x86: dts: Add SPI flash MRC details for chromebook_link
Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/dts/chromebook_link.dts | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index 9490b16..45ada61 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -7,6 +7,10 @@ model = "Google Link"; compatible = "google,link", "intel,celeron-ivybridge"; + aliases { + spi0 = "/spi"; + }; + config { silent_console = <0>; }; @@ -150,11 +154,20 @@ spi { #address-cells = <1>; #size-cells = <0>; - compatible = "intel,ich9"; + compatible = "intel,ich-spi"; spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; reg = <0>; compatible = "winbond,w25q64", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + /* Alignment: 4k (for updating) */ + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; }; }; |