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authorStefan Roese <sr@denx.de>2010-05-25 16:13:41 +0200
committerStefan Roese <sr@denx.de>2010-07-01 10:26:20 +0200
commit2909ac03f4125c25903c2ac69a6ef0f6e807a53d (patch)
tree77a0a79b0f2ac69e1744ce1b09b14c94903dbc54 /arch
parente9c020df9608c58ccd35a000bceadbb91ffe5f23 (diff)
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ppc4xx: Add DDR1/2 macros in ppc4xx-sdram.h for non-405EX as well
This patch adds some DDR(2) macros to all PPC4xx's equipped with this IBM DDR1/2 controller. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/include/asm/ppc4xx-sdram.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h
index 66cf509..d9506e2 100644
--- a/arch/powerpc/include/asm/ppc4xx-sdram.h
+++ b/arch/powerpc/include/asm/ppc4xx-sdram.h
@@ -344,6 +344,9 @@
#define SDRAM_RXBAS_SDSZ_2048 SDRAM_RXBAS_SDSZ_2048MB
#define SDRAM_RXBAS_SDSZ_4096 SDRAM_RXBAS_SDSZ_4096MB
#define SDRAM_RXBAS_SDSZ_8192 SDRAM_RXBAS_SDSZ_8192MB
+#endif /* CONFIG_405EX */
+
+/* The mode definitions are the same for all PPC4xx variants */
#define SDRAM_RXBAS_SDAM_MODE0 PPC_REG_VAL(23, 0x0)
#define SDRAM_RXBAS_SDAM_MODE1 PPC_REG_VAL(23, 0x1)
#define SDRAM_RXBAS_SDAM_MODE2 PPC_REG_VAL(23, 0x2)
@@ -356,7 +359,6 @@
#define SDRAM_RXBAS_SDAM_MODE9 PPC_REG_VAL(23, 0x9)
#define SDRAM_RXBAS_SDBE_DISABLE PPC_REG_VAL(31, 0x0)
#define SDRAM_RXBAS_SDBE_ENABLE PPC_REG_VAL(31, 0x1)
-#endif /* CONFIG_405EX */
/*
* Memory controller registers