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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-05-06 16:44:04 +0800 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-05-06 16:44:04 +0800 |
| commit | 3f0eb9faac520e2f3e50214df34ef9d6c25e011a (patch) | |
| tree | 150fcebe814aa4b7cffbc9e992d9d8eeb1784d48 /arch | |
| parent | 87723f903454aaf17336e0fe9098ea7911c19f3c (diff) | |
| download | u-boot-imx-3f0eb9faac520e2f3e50214df34ef9d6c25e011a.zip u-boot-imx-3f0eb9faac520e2f3e50214df34ef9d6c25e011a.tar.gz u-boot-imx-3f0eb9faac520e2f3e50214df34ef9d6c25e011a.tar.bz2 | |
MLK-10829-1 imx:mx6sx correct i2c and video clock settings
Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx
Remove duplicated mxs_set_vadcclk
Correct enable_pll_video usage
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 4 |
2 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index bac45e0..1ef307a 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -598,16 +598,6 @@ void enable_lcdif_clock(uint32_t base_addr) reg |= (MXC_CCM_CCGR2_LCD_MASK); writel(reg, &imx_ccm->CCGR2); } - -void mxs_set_vadcclk(void) -{ - u32 reg = 0; - - reg = readl(&imx_ccm->cscmr2); - reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK; - reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET; - writel(reg, &imx_ccm->cscmr2); -} #endif #ifdef CONFIG_MX6UL @@ -776,7 +766,7 @@ void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) } #ifdef CONFIG_MX6SX else { - if (enable_pll_video(pll_div, pll_num, pll_denom)) + if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) return; /* Select pre-lcd clock to PLL5 */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 0412a11..0c79842 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -1113,8 +1113,8 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) #define MXC_CCM_CCGR6_GIS_OFFSET 22 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) -#define MXC_CCM_CCGR6_I2C4_OFFSET 24 -#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) +#define MXC_CCM_CCGR6_I2C4_SERIAL_OFFSET 24 +#define MXC_CCM_CCGR6_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR6_I2C4_SERIAL_OFFSET) #define MXC_CCM_CCGR6_PWM5_OFFSET 26 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) #define MXC_CCM_CCGR6_PWM6_OFFSET 28 |