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| author | Allen Xu <b45815@freescale.com> | 2014-12-16 20:30:08 -0600 |
|---|---|---|
| committer | Peng Fan <Peng.Fan@freescale.com> | 2015-04-29 14:46:01 +0800 |
| commit | 77ca54d246cf90af88afe4eb93e63823b1de1e4a (patch) | |
| tree | 921000930157c140529a8ea2930a85ca50be37d9 /arch | |
| parent | 823e4975ecf30c59d949fafae47d8a37dd82f36c (diff) | |
| download | u-boot-imx-77ca54d246cf90af88afe4eb93e63823b1de1e4a.zip u-boot-imx-77ca54d246cf90af88afe4eb93e63823b1de1e4a.tar.gz u-boot-imx-77ca54d246cf90af88afe4eb93e63823b1de1e4a.tar.bz2 | |
MLK-10035-2: supports NAND chips with oob size up to 744 byte
Update the u-boot code to support NAND chips with oob size up to 744
byte.
For the NAND flash MT29F32G08CBADA, which consists of 2 planes x 1064
blocks per plane. Obviously the block number is not power-of-2. But all
MTD driver assumes the page per block and block per plane must be a
power of 2 number. So the last 40 blocks in each plane must be
truncated.
Signed-off-by: Allen Xu <b45815@freescale.com>
(cherry picked from commit 9045626dbc7798cc340f64699bc9bd35c537498a)
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Conflicts:
include/linux/mtd/nand.h
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/include/asm/imx-common/regs-bch.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h index a33d341..1a60b15 100644 --- a/arch/arm/include/asm/imx-common/regs-bch.h +++ b/arch/arm/include/asm/imx-common/regs-bch.h @@ -5,7 +5,7 @@ * on behalf of DENX Software Engineering GmbH * * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -148,6 +148,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12) #define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10 #define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff #define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 @@ -178,6 +179,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12) #define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12) #define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10) +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10 #define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff #define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 |