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authorAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-02-24 10:29:59 +0100
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2014-02-24 10:29:59 +0100
commitfae56934a0744a4dd6981323ba8a966646fd7ca5 (patch)
treef1eab46cc702aee6c8cd2c2aaeda95d383ed02a6 /arch
parent9ed679aeeb9899123bf92ed1eafb7cf6965473dc (diff)
parent11f296870659e1375e7116a859458b254cc3156f (diff)
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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/am33xx/board.c6
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_am43xx.c2
-rw-r--r--arch/arm/cpu/armv7/am33xx/clock_ti814x.c5
-rw-r--r--arch/arm/cpu/armv7/omap4/hw_data.c18
-rw-r--r--arch/arm/cpu/armv7/omap5/prcm-regs.c2
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h12
-rw-r--r--arch/arm/include/asm/arch-am33xx/ddr_defs.h16
-rw-r--r--arch/arm/include/asm/arch-am33xx/gpio.h4
8 files changed, 54 insertions, 11 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index c7dad66..2b15a64 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -36,11 +36,15 @@
DECLARE_GLOBAL_DATA_PTR;
-static const struct gpio_bank gpio_bank_am33xx[4] = {
+static const struct gpio_bank gpio_bank_am33xx[] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+#ifdef CONFIG_AM43XX
+ { (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
+#endif
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 97c00b4..440cf8b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -94,6 +94,8 @@ void enable_basic_clocks(void)
&cmper->gpio1clkctrl,
&cmper->gpio2clkctrl,
&cmper->gpio3clkctrl,
+ &cmper->gpio4clkctrl,
+ &cmper->gpio5clkctrl,
&cmper->i2c1clkctrl,
&cmper->emiffwclkctrl,
&cmper->emifclkctrl,
diff --git a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
index ef14f47..9b5a47b 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_ti814x.c
@@ -211,11 +211,8 @@ static u32 pll_dco_freq_sel(u32 clkout_dco)
static u32 pll_sigma_delta_val(u32 clkout_dco)
{
u32 sig_val = 0;
- float frac_div;
- frac_div = (float) clkout_dco / 250;
- frac_div = frac_div + 0.90;
- sig_val = (int)frac_div;
+ sig_val = (clkout_dco + 225) / 250;
sig_val = sig_val << 24;
return sig_val;
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 4dec73e..029533c 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -172,6 +172,20 @@ struct dplls omap4430_dplls_es1 = {
.ddr = NULL
};
+struct dplls omap4430_dplls_es20 = {
+ .mpu = mpu_dpll_params_1200mhz,
+ .core = core_dpll_params_es2_1600mhz_ddr200mhz,
+ .per = per_dpll_params_1536mhz,
+ .iva = iva_dpll_params_1862mhz,
+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK
+ .abe = abe_dpll_params_sysclk_196608khz,
+#else
+ .abe = &abe_dpll_params_32k_196608khz,
+#endif
+ .usb = usb_dpll_params_1920mhz,
+ .ddr = NULL
+};
+
struct dplls omap4430_dplls = {
.mpu = mpu_dpll_params_1200mhz,
.core = core_dpll_params_1600mhz,
@@ -413,6 +427,10 @@ void hw_data_init(void)
break;
case OMAP4430_ES2_0:
+ *dplls_data = &omap4430_dplls_es20;
+ *omap_vcores = &omap4430_volts;
+ break;
+
case OMAP4430_ES2_1:
case OMAP4430_ES2_2:
case OMAP4430_ES2_3:
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index ff32807..7292161 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -432,7 +432,7 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = {
.control_srcomp_code_latch = 0x4A002E84,
.control_ddr_control_ext_0 = 0x4A002E88,
.control_padconf_core_base = 0x4A003400,
- .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B24,
+ .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20,
.control_port_emif1_sdram_config = 0x4AE0C110,
.control_port_emif1_lpddr2_nvm_config = 0x4AE0C114,
.control_port_emif2_sdram_config = 0x4AE0C118,
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 9febfa2..97e8702 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -171,7 +171,8 @@ struct cm_wkuppll {
unsigned int resv11[1];
unsigned int wkup_uart0ctrl; /* offset 0xB4 */
unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
- unsigned int resv12[7];
+ unsigned int wkup_adctscctrl; /* offset 0xBC */
+ unsigned int resv12[6];
unsigned int divm6dpllcore; /* offset 0xD8 */
};
@@ -221,7 +222,8 @@ struct cm_perpll {
unsigned int tpccclkctrl; /* offset 0xBC */
unsigned int dcan0clkctrl; /* offset 0xC0 */
unsigned int dcan1clkctrl; /* offset 0xC4 */
- unsigned int resv6[2];
+ unsigned int resv6;
+ unsigned int epwmss1clkctrl; /* offset 0xCC */
unsigned int emiffwclkctrl; /* offset 0xD0 */
unsigned int epwmss0clkctrl; /* offset 0xD4 */
unsigned int epwmss2clkctrl; /* offset 0xD8 */
@@ -351,7 +353,11 @@ struct cm_perpll {
unsigned int gpio2clkctrl; /* offset 0x480 */
unsigned int resv20;
unsigned int gpio3clkctrl; /* offset 0x488 */
- unsigned int resv21[7];
+ unsigned int resv41;
+ unsigned int gpio4clkctrl; /* offset 0x490 */
+ unsigned int resv42;
+ unsigned int gpio5clkctrl; /* offset 0x498 */
+ unsigned int resv21[3];
unsigned int i2c1clkctrl; /* offset 0x4A8 */
unsigned int resv22;
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fbe599d..4d89952 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -58,6 +58,22 @@
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
+#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
+#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
+#define MT41K128MJT187E_RATIO 0x40
+#define MT41K128MJT187E_INVERT_CLKOUT 0x1
+#define MT41K128MJT187E_RD_DQS 0x3B
+#define MT41K128MJT187E_WR_DQS 0x85
+#define MT41K128MJT187E_PHY_WR_DATA 0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE 0x100
+#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
+
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h
index a1ffd49..220603d 100644
--- a/arch/arm/include/asm/arch-am33xx/gpio.h
+++ b/arch/arm/include/asm/arch-am33xx/gpio.h
@@ -12,8 +12,8 @@
#define AM33XX_GPIO1_BASE 0x4804C000
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
-
-#define GPIO_22 22
+#define AM33XX_GPIO4_BASE 0x48320000
+#define AM33XX_GPIO5_BASE 0x48322000
/* GPIO CTRL register */
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0