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| author | Chunhe Lan <Chunhe.Lan@freescale.com> | 2014-05-07 10:50:20 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-05-16 16:24:26 -0500 |
| commit | f1a96ec1a9920854c3308a062caca0b339bd1e3b (patch) | |
| tree | f1cf2111f5b0b49ad7ef751db0bd19ca608c8891 /arch | |
| parent | 0f1fa36ffffbd34c8512eeacade7139bcffda47c (diff) | |
| download | u-boot-imx-f1a96ec1a9920854c3308a062caca0b339bd1e3b.zip u-boot-imx-f1a96ec1a9920854c3308a062caca0b339bd1e3b.tar.gz u-boot-imx-f1a96ec1a9920854c3308a062caca0b339bd1e3b.tar.bz2 | |
fsl/pci: Add workaround for erratum A-005434
By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 9d8acd0..3d37a76 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -299,6 +299,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 check_erratum_a007212(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + puts("Work-around for Erratum A-005434 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8a7d4d8..e124b07 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -591,6 +591,7 @@ #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A005434 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR |