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authorTom Rini <trini@ti.com>2015-02-21 22:01:09 -0500
committerTom Rini <trini@ti.com>2015-02-21 22:01:09 -0500
commitded4bc3a8ba6e96811f761b358b4c628ec927ade (patch)
treec20e768fb197b86dfdff5dad53c5530217fafdae /arch
parent46414296953410706e917cef9238926084e83a4b (diff)
parent77ef136950b4649ff4844c3b72dab107a9c565a0 (diff)
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Merge git://git.denx.de/u-boot-sunxi
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/include/asm/arch-sunxi/clock_sun4i.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index d297ed0..c28ee05 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -144,7 +144,16 @@ struct sunxi_ccm_reg {
#define PLL1_CFG_DEFAULT 0xa1005000
+#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I
+/*
+ * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz,
+ * halving the mbus frequency, so set it to 300 MHz ourselves and base the
+ * mbus divider on that.
+ */
+#define PLL6_CFG_DEFAULT 0xa1009900
+#else
#define PLL6_CFG_DEFAULT 0xa1009911
+#endif
/* nand clock */
#define NAND_CLK_SRC_OSC24 0