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authorGabor Juhos <juhosg@openwrt.org>2013-06-13 12:59:34 +0200
committerTom Rini <trini@ti.com>2013-07-24 09:51:06 -0400
commitc325916563ac67ec5f86748060c2909a9b960bee (patch)
treea98d4adeb632f03e54c4aa24760fca03732b7dde /arch
parentd707e5b713e1188556027d835a542d1fc888179d (diff)
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MIPS: mips32/cache.S: save return address in t9 register
Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/cpu/mips32/cache.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index 40bb46e..fc13d3f 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -18,7 +18,7 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
-#define RA t8
+#define RA t9
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,