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authorAneesh V <aneesh@ti.com>2011-11-21 23:34:00 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-12-06 23:59:33 +0100
commita8c686399f01c359713447c2adaecf94f3a4445b (patch)
tree764f17c29f9181533174fbd1baa57d04d8c40583 /arch
parent87d3da7b01ee083447f9fcc62f35427d5fde2e2f (diff)
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armv7: setup vector
The vector is not correctly setup in armv7 except for OMAP3. Correcting this. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: Aneesh V <aneesh@ti.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/start.S17
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index db8e9d2..f17763f 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -32,6 +32,7 @@
#include <asm-offsets.h>
#include <config.h>
#include <version.h>
+#include <asm/system.h>
.globl _start
_start: b reset
@@ -143,6 +144,22 @@ reset:
orr r0, r0, #0xd3
msr cpsr,r0
+/*
+ * Setup vector:
+ * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
+ * Continue to use ROM code vector only in OMAP4 spl)
+ */
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+ /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
+ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
+ bic r0, #CR_V @ V = 0
+ mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
+
+ /* Set vector address in CP15 VBAR register */
+ ldr r0, =_start
+ mcr p15, 0, r0, c12, c0, 0 @Set VBAR
+#endif
+
#if defined(CONFIG_OMAP34XX)
/* Copy vectors to mask ROM indirect addr */
adr r0, _start @ r0 <- current position of code