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authorAllen Martin <amartin@nvidia.com>2013-05-10 16:56:55 +0000
committerTom Warren <twarren@nvidia.com>2013-05-28 12:58:42 -0700
commita51f7de161274af05f92de0417e4e03d04334053 (patch)
tree4039cb357b0258f13e5a5fa3249a5aec629ade4e /arch
parentd56273de1522a842481236d0dfa281ad4091b5c5 (diff)
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Tegra: clk: always use find_best_divider() for periph clocks
When adjusting peripheral clocks always use find_best_divider() instead of clk_get_divider() even when a secondary divider is not available. In the case where is requested clock is too slow to be derived from the parent clock this allows a best effort to get close to the requested clock. This comes up for commands like "sf" where the user can pass a clock speed on the command line or "sspi" where the clock is hardcoded to 1MHz, but the Tegra114 SPI controller can't go that low. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/tegra-common/clock.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/cpu/tegra-common/clock.c b/arch/arm/cpu/tegra-common/clock.c
index 9156d00..268fb91 100644
--- a/arch/arm/cpu/tegra-common/clock.c
+++ b/arch/arm/cpu/tegra-common/clock.c
@@ -321,17 +321,17 @@ unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
unsigned effective_rate;
int mux_bits, divider_bits, source;
int divider;
+ int xdiv = 0;
/* work out the source clock and set it */
source = get_periph_clock_source(periph_id, parent, &mux_bits,
&divider_bits);
+ divider = find_best_divider(divider_bits, pll_rate[parent],
+ rate, &xdiv);
if (extra_div)
- divider = find_best_divider(divider_bits, pll_rate[parent],
- rate, extra_div);
- else
- divider = clk_get_divider(divider_bits, pll_rate[parent],
- rate);
+ *extra_div = xdiv;
+
assert(divider >= 0);
if (adjust_periph_pll(periph_id, source, mux_bits, divider))
return -1U;