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authorBin Meng <bmeng.cn@gmail.com>2014-12-12 21:05:25 +0800
committerSimon Glass <sjg@chromium.org>2014-12-13 22:32:05 -0700
commita2927e09bccca5b665709d77fc54919292d4bcb7 (patch)
tree0852399092f7a8184f74e8fc25f06154127a72ed /arch
parent568868dda9b8f8e901962231713fc0cb3f42c410 (diff)
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x86: Add a simple superio driver for SMSC LPC47M
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/include/asm/pnp_def.h90
1 files changed, 90 insertions, 0 deletions
diff --git a/arch/x86/include/asm/pnp_def.h b/arch/x86/include/asm/pnp_def.h
new file mode 100644
index 0000000..24b038d
--- /dev/null
+++ b/arch/x86/include/asm/pnp_def.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * Adapted from coreboot src/include/device/pnp_def.h
+ * and arch/x86/include/arch/io.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_PNP_DEF_H_
+#define _ASM_PNP_DEF_H_
+
+#include <asm/io.h>
+
+#define PNP_IDX_EN 0x30
+#define PNP_IDX_IO0 0x60
+#define PNP_IDX_IO1 0x62
+#define PNP_IDX_IO2 0x64
+#define PNP_IDX_IO3 0x66
+#define PNP_IDX_IRQ0 0x70
+#define PNP_IDX_IRQ1 0x72
+#define PNP_IDX_DRQ0 0x74
+#define PNP_IDX_DRQ1 0x75
+#define PNP_IDX_MSC0 0xf0
+#define PNP_IDX_MSC1 0xf1
+
+/* Generic functions for pnp devices */
+
+/*
+ * pnp device is a 16-bit integer composed of its i/o port address at high byte
+ * and logic function number at low byte.
+ */
+#define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC))
+
+static inline void pnp_write_config(uint16_t dev, uint8_t reg, uint8_t value)
+{
+ uint8_t port = dev >> 8;
+
+ outb(reg, port);
+ outb(value, port + 1);
+}
+
+static inline uint8_t pnp_read_config(uint16_t dev, uint8_t reg)
+{
+ uint8_t port = dev >> 8;
+
+ outb(reg, port);
+ return inb(port + 1);
+}
+
+static inline void pnp_set_logical_device(uint16_t dev)
+{
+ uint8_t device = dev & 0xff;
+
+ pnp_write_config(dev, 0x07, device);
+}
+
+static inline void pnp_set_enable(uint16_t dev, int enable)
+{
+ pnp_write_config(dev, PNP_IDX_EN, enable ? 1 : 0);
+}
+
+static inline int pnp_read_enable(uint16_t dev)
+{
+ return !!pnp_read_config(dev, PNP_IDX_EN);
+}
+
+static inline void pnp_set_iobase(uint16_t dev, uint8_t index, uint16_t iobase)
+{
+ pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff);
+ pnp_write_config(dev, index + 1, iobase & 0xff);
+}
+
+static inline uint16_t pnp_read_iobase(uint16_t dev, uint8_t index)
+{
+ return ((uint16_t)(pnp_read_config(dev, index)) << 8) |
+ pnp_read_config(dev, index + 1);
+}
+
+static inline void pnp_set_irq(uint16_t dev, uint8_t index, unsigned irq)
+{
+ pnp_write_config(dev, index, irq);
+}
+
+static inline void pnp_set_drq(uint16_t dev, uint8_t index, unsigned drq)
+{
+ pnp_write_config(dev, index, drq & 0xff);
+}
+
+#endif /* _ASM_PNP_DEF_H_ */