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authorPeter Barada <peter.barada@logicpd.com>2012-11-13 07:40:28 +0000
committerTom Rini <trini@ti.com>2012-12-10 08:54:02 -0700
commit8c4445d26633f43fcd04add3d6cdc3bc41d14841 (patch)
treee2cab89ccff5955681182e71200a8d1053585528 /arch
parentd7aff44a00e5de3de2ed18a3329edf5ff9d3aada (diff)
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Pass sdrc timing values through board_sdrc_timings structure
Instead of passing individual registers by value to board_get_mem_timings, pass a board_mem_timings structure pointer for the board files to fill in. Pass same structure pointer to write_sdrc_timings. This saves about 90 bytes of space in SPL. Signed-off-by: Peter Barada <peter.barada@logicpd.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/omap3/sdrc.c36
-rw-r--r--arch/arm/include/asm/arch-omap3/sys_proto.h13
2 files changed, 27 insertions, 22 deletions
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index f6d9b97..e32bf11 100644
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -113,18 +113,18 @@ u32 get_sdr_cs_offset(u32 cs)
* - Test CS to make sure it's OK for use
*/
static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
- u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+ struct board_sdrc_timings *timings)
{
/* Setup timings we got from the board. */
- writel(mcfg, &sdrc_base->cs[cs].mcfg);
- writel(ctrla, &sdrc_actim_base->ctrla);
- writel(ctrlb, &sdrc_actim_base->ctrlb);
- writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+ writel(timings->mcfg, &sdrc_base->cs[cs].mcfg);
+ writel(timings->ctrla, &sdrc_actim_base->ctrla);
+ writel(timings->ctrlb, &sdrc_actim_base->ctrlb);
+ writel(timings->rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
writel(CMD_NOP, &sdrc_base->cs[cs].manual);
writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
- writel(mr, &sdrc_base->cs[cs].mr);
+ writel(timings->mr, &sdrc_base->cs[cs].mr);
/*
* Test ram in this bank
@@ -143,7 +143,7 @@ static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
void do_sdrc_init(u32 cs, u32 early)
{
struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
- u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
+ struct board_sdrc_timings timings;
sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
@@ -158,7 +158,7 @@ void do_sdrc_init(u32 cs, u32 early)
* setup CS1.
*/
#ifdef CONFIG_SPL_BUILD
- get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+ get_board_mem_timings(&timings);
#endif
if (early) {
/* reset sdrc controller */
@@ -177,11 +177,9 @@ void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
#ifdef CONFIG_SPL_BUILD
- write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
- rfr_ctrl, mr);
+ write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
make_cs1_contiguous();
- write_sdrc_timings(CS1, sdrc_actim_base1, mcfg, ctrla, ctrlb,
- rfr_ctrl, mr);
+ write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
#endif
}
@@ -193,14 +191,12 @@ void do_sdrc_init(u32 cs, u32 early)
* so we may be asked now to setup CS1.
*/
if (cs == CS1) {
- mcfg = readl(&sdrc_base->cs[CS0].mcfg),
- rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
- ctrla = readl(&sdrc_actim_base0->ctrla),
- ctrlb = readl(&sdrc_actim_base0->ctrlb);
- mr = readl(&sdrc_base->cs[CS0].mr);
- write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
- rfr_ctrl, mr);
-
+ timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+ timings.rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+ timings.ctrla = readl(&sdrc_actim_base0->ctrla);
+ timings.ctrlb = readl(&sdrc_actim_base0->ctrlb);
+ timings.mr = readl(&sdrc_base->cs[CS0].mr);
+ write_sdrc_timings(cs, sdrc_actim_base1, &timings);
}
}
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h
index 9e52b12..d60f2ad 100644
--- a/arch/arm/include/asm/arch-omap3/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap3/sys_proto.h
@@ -32,6 +32,15 @@ struct emu_hal_params {
u32 param1;
};
+/* Board SDRC timing values */
+struct board_sdrc_timings {
+ u32 mcfg;
+ u32 ctrla;
+ u32 ctrlb;
+ u32 rfr_ctrl;
+ u32 mr;
+};
+
void prcm_init(void);
void per_clocks_enable(void);
void ehci_clocks_enable(void);
@@ -39,8 +48,8 @@ void ehci_clocks_enable(void);
void memif_init(void);
void sdrc_init(void);
void do_sdrc_init(u32, u32);
-void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
- u32 *mr);
+
+void get_board_mem_timings(struct board_sdrc_timings *timings);
void identify_nand_chip(int *mfr, int *id);
void emif4_init(void);
void gpmc_init(void);