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authorSimon Glass <sjg@chromium.org>2015-01-01 16:18:03 -0700
committerSimon Glass <sjg@chromium.org>2015-01-13 07:24:59 -0800
commit818f602112f5e789704096dbc4a7eb9f63fe5718 (patch)
tree992362def3352e661b445fd692767cc25d6feb6f /arch
parentd19ee5c27ec0c144bae294b4317e03738616a593 (diff)
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x86: Use cache, don't clear the display in video BIOS
There is no need to run with the cache disabled, and there is no point in clearing the display frame buffer since U-Boot does it later. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/lib/bios.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c
index d1f8933..4285348 100644
--- a/arch/x86/lib/bios.c
+++ b/arch/x86/lib/bios.c
@@ -210,8 +210,8 @@ static u8 vbe_set_mode(struct vbe_mode_info *mi)
debug("VBE: Setting VESA mode %#04x\n", mi->video_mode);
/* request linear framebuffer mode */
mi->video_mode |= (1 << 14);
- /* request clearing of framebuffer */
- mi->video_mode &= ~(1 << 15);
+ /* don't clear the framebuffer, we do that later */
+ mi->video_mode |= (1 << 15);
realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode,
0x0000, 0x0000, 0x0000, 0x0000);
@@ -262,7 +262,6 @@ void bios_run_on_x86(pci_dev_t pcidev, unsigned long addr, int vesa_mode,
/* Make sure the code is placed. */
setup_realmode_code();
- disable_caches();
debug("Calling Option ROM at %lx, pci device %#x...", addr, num_dev);
/* Option ROM entry point is at OPROM start + 3 */