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authorYork Sun <yorksun@freescale.com>2012-08-17 08:22:41 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 12:16:56 -0500
commit7e4db27ffd11f3eea7e4dfc33354fd087f9257d8 (patch)
treee0969470af32c5d761ab276b65ac920af646e14e /arch
parent45064adcae724bd5162f64f186fdb17bfef8ab42 (diff)
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powerpc/mpc8xxx DDR: Fix CAS latency calculation
Empty slot should be skipped when calculating CAS latency. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index a474a65..03a784c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -27,8 +27,10 @@ compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
/* compute the common CAS latency supported between slots */
tmp = dimm_params[0].caslat_X;
- for (i = 1; i < number_of_dimms; i++)
- tmp &= dimm_params[i].caslat_X;
+ for (i = 1; i < number_of_dimms; i++) {
+ if (dimm_params[i].n_ranks)
+ tmp &= dimm_params[i].caslat_X;
+ }
common_caslat = tmp;
/* compute the max tAAmin tCKmin between slots */