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authorHans de Goede <hdegoede@redhat.com>2014-11-02 16:55:09 +0100
committerHans de Goede <hdegoede@redhat.com>2014-11-13 14:49:01 +0100
commit6dbfda81c09f65528cc34cfda6a61375a06e69e0 (patch)
tree7aa1bfb2af5d4e34b0c15980e952dfe125a5fc77 /arch
parent9a07eb0ba02d4036317e0ca2a9b0e4769aac62bc (diff)
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sun6i: Poke magic sram controller register to avoid cache issues
Without this the cache will only work in write-through mode, and as soon as it is put in write-back mode things break. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/cpu/armv7/sunxi/board.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6c812fc..9b3e80c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
+#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
+ /* Magic (undocmented) value taken from boot0, without this DRAM
+ * access gets messed up (seems cache related) */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */