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authorYork Sun <yorksun@freescale.com>2012-08-17 08:22:42 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 12:16:56 -0500
commit62f739fe465c41a2c5be0a46b3330c12b213dc07 (patch)
tree84d1764a5c706e3618b10b999781eab6e3b02142 /arch
parent7e4db27ffd11f3eea7e4dfc33354fd087f9257d8 (diff)
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powerpc/mpc8xxx DDR: Fall back to raw timing for first controller only
Only the first DIMM of first controller should fall back to raw timing parameters if SPD is missing or corrupted. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/main.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
index 4fd4f8f..b47268c 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -383,7 +383,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
retval = compute_dimm_parameters(spd, pdimm, i);
#ifdef CONFIG_SYS_DDR_RAW_TIMING
- if (retval != 0) {
+ if (!i && !j && retval) {
printf("SPD error on controller %d! "
"Trying fallback to raw timing "
"calculation\n", i);